OV - exec - Loop 924

0x44f740 VMULPD	(%R8,%RDX,1),%XMM2,%XMM8    [1]

0x44f746 VFMADD231PD	(%R11,%RDX,1),%XMM1,%XMM8    [3]

0x44f74c VFMADD231PD	(%R10,%RDX,1),%XMM3,%XMM8    [2]

0x44f752 VFMADD231PD	(%R14,%RDX,1),%XMM4,%XMM8    [5]

0x44f758 VFMADD213PD	(%R13,%RDX,1),%XMM7,%XMM8    [4]

0x44f75f VMOVUPD	%XMM8,(%R13,%RDX,1)    [4]

0x44f766 ADD	$0x10,%RDX

0x44f76a DEC	%RCX

0x44f76d JNE	44f740

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 68 - 70

--------------------------------------------------------------------------------

68:       for (size_t n = 0; n < num_splines; n++)

69:         vals[n] += pre00 *

70:             (c[0] * coefs[n] + c[1] * coefs[n + zs] + c[2] * coefs[n + 2 * zs] +

Coverage (%)	Name	Source Location	Module
►100.00+	qmcplusplus::SPOSet::evaluateD[...]	OhmmsVector.h:178	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:217	exec
○	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:919	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:135	exec
○	main.extracted.107	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.50
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15
Bottlenecks	P0, P1,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source	MultiBsplineRef.hpp:68-70
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	1.67
CQA cycles if fully vectorized	0.63
Front-end cycles	2.17
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	1.67
P3 cycles	1.67
P4 cycles	0.50
P5 cycles	0.00
P6 cycles	1.00
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	0.00
P11 cycles	1.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	9.00
Nb uops	8.00
Nb loads	5.00
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	7.20
Nb FLOP add-sub	0.00
Nb FLOP mul	2.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	38.40
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	16.00
Stride 0	0.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.50
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15
Bottlenecks	P0, P1,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source	MultiBsplineRef.hpp:68-70
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	1.67
CQA cycles if fully vectorized	0.63
Front-end cycles	2.17
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	1.67
P3 cycles	1.67
P4 cycles	0.50
P5 cycles	0.00
P6 cycles	1.00
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	0.00
P11 cycles	1.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	9.00
Nb uops	8.00
Nb loads	5.00
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	7.20
Nb FLOP add-sub	0.00
Nb FLOP mul	2.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	38.40
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	16.00
Stride 0	0.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source file and lines	MultiBsplineRef.hpp:68-70
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:68-70.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 128 out of 512 bits (SSE/AVX-128 instructions on AVX-512 processors).

By fully vectorizing your loop, you can lower the cost of an iteration from 2.50 to 0.62 cycles (4.00x speedup).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.50 to 2.17 cycles (1.15x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 8 FMA (fused multiply-add) operations.

Type of elements and instruction set

5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 18 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
10: multiply (8 inside FMA instructions)

The binary loop is loading 80 bytes (10 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	9
nb uops	8
loop length	47
used x86 registers	7
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.17 cycles
front end	2.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.50	2.50	1.67	1.67	0.50	0.00	1.00	0.50	0.50	0.50	0.00	1.67
cycles	2.50	2.50	1.67	1.67	0.50	0.00	1.00	0.50	0.50	0.50	0.00	1.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.17
Dispatch	2.50
Data deps.	1.00
Overall L1	2.50

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

16% of peak load performance is reached (32.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 44f740

Instruction	Nb FU	P0	P1	P2	P3	P4	P6	P7	P8	P9	P11	Latency	Recip. throughput	Vectorization
VMULPD (%R8,%RDX,1),%XMM2,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD231PD (%R11,%RDX,1),%XMM1,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD231PD (%R10,%RDX,1),%XMM3,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD231PD (%R14,%RDX,1),%XMM4,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD213PD (%R13,%RDX,1),%XMM7,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VMOVUPD %XMM8,(%R13,%RDX,1)	1	0	0	0	0	0.50	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
ADD $0x10,%RDX	1	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %RCX	1	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 44f740 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x600>	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0.50	N/A

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source file and lines	MultiBsplineRef.hpp:68-70
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:68-70.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 128 out of 512 bits (SSE/AVX-128 instructions on AVX-512 processors).

By fully vectorizing your loop, you can lower the cost of an iteration from 2.50 to 0.62 cycles (4.00x speedup).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.50 to 2.17 cycles (1.15x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 8 FMA (fused multiply-add) operations.

Type of elements and instruction set

5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 18 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
10: multiply (8 inside FMA instructions)

The binary loop is loading 80 bytes (10 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	9
nb uops	8
loop length	47
used x86 registers	7
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.17 cycles
front end	2.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.50	2.50	1.67	1.67	0.50	0.00	1.00	0.50	0.50	0.50	0.00	1.67
cycles	2.50	2.50	1.67	1.67	0.50	0.00	1.00	0.50	0.50	0.50	0.00	1.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.17
Dispatch	2.50
Data deps.	1.00
Overall L1	2.50

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

16% of peak load performance is reached (32.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 44f740

Instruction	Nb FU	P0	P1	P2	P3	P4	P6	P7	P8	P9	P11	Latency	Recip. throughput	Vectorization
VMULPD (%R8,%RDX,1),%XMM2,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD231PD (%R11,%RDX,1),%XMM1,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD231PD (%R10,%RDX,1),%XMM3,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD231PD (%R14,%RDX,1),%XMM4,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD213PD (%R13,%RDX,1),%XMM7,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VMOVUPD %XMM8,(%R13,%RDX,1)	1	0	0	0	0	0.50	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
ADD $0x10,%RDX	1	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %RCX	1	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 44f740 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x600>	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code