OV - exec - Loop 1419

	Loop Id: 1419	Module: exec	Source: ParticleBConds3DSoa.h:235-256	Coverage: 1.48%

0x48db60 LEA	(%R9,%R13,1),%R15D

0x48db64 MOVSXD	%R15D,%R15

0x48db67 VMOVUPD	(%RDX,%R15,8),%YMM7    [8]

0x48db6d VMOVUPD	0x20(%RDX,%R15,8),%YMM8    [8]

0x48db74 VMOVUPD	0x40(%RDX,%R15,8),%YMM9    [8]

0x48db7b VMOVUPD	0x60(%RDX,%R15,8),%YMM11    [8]

0x48db82 VSUBPD	%YMM2,%YMM7,%YMM10

0x48db86 VSUBPD	%YMM2,%YMM8,%YMM17

0x48db8c VSUBPD	%YMM2,%YMM9,%YMM18

0x48db92 VSUBPD	%YMM2,%YMM11,%YMM19

0x48db98 VMOVUPD	(%R10,%R15,8),%YMM7    [3]

0x48db9e VMOVUPD	0x20(%R10,%R15,8),%YMM8    [3]

0x48dba5 VMOVUPD	0x40(%R10,%R15,8),%YMM9    [3]

0x48dbac VMOVUPD	0x60(%R10,%R15,8),%YMM11    [3]

0x48dbb3 VSUBPD	%YMM3,%YMM11,%YMM21

0x48dbb9 VSUBPD	%YMM3,%YMM9,%YMM22

0x48dbbf VSUBPD	%YMM3,%YMM8,%YMM24

0x48dbc5 VMOVUPD	(%RSI,%R15,8),%YMM8    [5]

0x48dbcb VMOVUPD	0x20(%RSI,%R15,8),%YMM9    [5]

0x48dbd2 VMOVUPD	0x40(%RSI,%R15,8),%YMM12    [5]

0x48dbd9 VMOVUPD	0x60(%RSI,%R15,8),%YMM13    [5]

0x48dbe0 VSUBPD	%YMM3,%YMM7,%YMM26

0x48dbe6 VSUBPD	%YMM4,%YMM8,%YMM11

0x48dbea VSUBPD	%YMM4,%YMM9,%YMM20

0x48dbf0 VSUBPD	%YMM4,%YMM12,%YMM23

0x48dbf6 VSUBPD	%YMM4,%YMM13,%YMM25

0x48dbfc VBROADCASTSD	0x48(%RDI),%YMM8    [2]

0x48dc02 VMULPD	%YMM19,%YMM8,%YMM12

0x48dc08 VMULPD	%YMM18,%YMM8,%YMM13

0x48dc0e VMULPD	%YMM17,%YMM8,%YMM7

0x48dc14 VMULPD	%YMM10,%YMM8,%YMM8

0x48dc19 VBROADCASTSD	0x50(%RDI),%YMM9    [2]

0x48dc1f VFMADD231PD	%YMM26,%YMM9,%YMM8

0x48dc25 VFMADD231PD	%YMM24,%YMM9,%YMM7

0x48dc2b VFMADD231PD	%YMM22,%YMM9,%YMM13

0x48dc31 VBROADCASTSD	0x60(%RDI),%YMM27    [2]

0x48dc38 VMULPD	%YMM10,%YMM27,%YMM15

0x48dc3e VMULPD	%YMM17,%YMM27,%YMM16

0x48dc44 VMULPD	%YMM18,%YMM27,%YMM14

0x48dc4a VFMADD231PD	%YMM9,%YMM21,%YMM12

0x48dc50 VMULPD	%YMM19,%YMM27,%YMM9

0x48dc56 VBROADCASTSD	0x68(%RDI),%YMM27    [2]

0x48dc5d VFMADD231PD	%YMM21,%YMM27,%YMM9

0x48dc63 VFMADD231PD	%YMM22,%YMM27,%YMM14

0x48dc69 VBROADCASTSD	0x78(%RDI),%YMM28    [2]

0x48dc70 VFMADD231PD	%YMM24,%YMM27,%YMM16

0x48dc76 VMULPD	%YMM19,%YMM28,%YMM19

0x48dc7c VMULPD	%YMM18,%YMM28,%YMM18

0x48dc82 VMULPD	%YMM17,%YMM28,%YMM17

0x48dc88 VMULPD	%YMM10,%YMM28,%YMM10

0x48dc8e VBROADCASTSD	0x80(%RDI),%YMM28    [2]

0x48dc95 VFMADD231PD	%YMM27,%YMM26,%YMM15

0x48dc9b VFMADD231PD	%YMM26,%YMM28,%YMM10

0x48dca1 VBROADCASTSD	0x58(%RDI),%YMM26    [2]

0x48dca8 VFMADD231PD	%YMM25,%YMM26,%YMM12

0x48dcae VFMADD231PD	%YMM23,%YMM26,%YMM13

0x48dcb4 VFMADD231PD	%YMM20,%YMM26,%YMM7

0x48dcba VFMADD231PD	%YMM26,%YMM11,%YMM8

0x48dcc0 VBROADCASTSD	0x70(%RDI),%YMM26    [2]

0x48dcc7 VFMADD231PD	%YMM11,%YMM26,%YMM15

0x48dccd VFMADD231PD	%YMM20,%YMM26,%YMM16

0x48dcd3 VFMADD231PD	%YMM23,%YMM26,%YMM14

0x48dcd9 VFMADD231PD	%YMM24,%YMM28,%YMM17

0x48dcdf VFMADD231PD	%YMM26,%YMM25,%YMM9

0x48dce5 VFMADD231PD	%YMM22,%YMM28,%YMM18

0x48dceb VFMADD231PD	%YMM21,%YMM28,%YMM19

0x48dcf1 VBROADCASTSD	0x88(%RDI),%YMM21    [2]

0x48dcf8 VFMADD231PD	%YMM25,%YMM21,%YMM19

0x48dcfe VFMADD231PD	%YMM23,%YMM21,%YMM18

0x48dd04 VMOVDQA64	%YMM6,%YMM22

0x48dd0a VFMADD231PD	%YMM20,%YMM21,%YMM17

0x48dd10 VPTERNLOGQ	$-0x8,%YMM5,%YMM8,%YMM22

0x48dd17 VADDPD	%YMM22,%YMM8,%YMM20

0x48dd1d VMOVDQA64	%YMM6,%YMM22

0x48dd23 VPTERNLOGQ	$-0x8,%YMM5,%YMM7,%YMM22

0x48dd2a VADDPD	%YMM22,%YMM7,%YMM22

0x48dd30 VRNDSCALEPD	$0xb,%YMM20,%YMM20

0x48dd37 VRNDSCALEPD	$0xb,%YMM22,%YMM22

0x48dd3e VMOVDQA64	%YMM6,%YMM23

0x48dd44 VPTERNLOGQ	$-0x8,%YMM5,%YMM13,%YMM23

0x48dd4b VADDPD	%YMM23,%YMM13,%YMM23

0x48dd51 VMOVDQA64	%YMM6,%YMM24

0x48dd57 VRNDSCALEPD	$0xb,%YMM23,%YMM23

0x48dd5e VPTERNLOGQ	$-0x8,%YMM5,%YMM12,%YMM24

0x48dd65 VADDPD	%YMM24,%YMM12,%YMM24

0x48dd6b VRNDSCALEPD	$0xb,%YMM24,%YMM24

0x48dd72 VMOVDQA64	%YMM6,%YMM25

0x48dd78 VPTERNLOGQ	$-0x8,%YMM5,%YMM9,%YMM25

0x48dd7f VADDPD	%YMM25,%YMM9,%YMM25

0x48dd85 VRNDSCALEPD	$0xb,%YMM25,%YMM25

0x48dd8c VMOVDQA64	%YMM6,%YMM26

0x48dd92 VPTERNLOGQ	$-0x8,%YMM5,%YMM14,%YMM26

0x48dd99 VADDPD	%YMM26,%YMM14,%YMM26

0x48dd9f VRNDSCALEPD	$0xb,%YMM26,%YMM26

0x48dda6 VFMADD231PD	%YMM11,%YMM21,%YMM10

0x48ddac VMOVDQA	%YMM6,%YMM11

0x48ddb0 VPTERNLOGQ	$-0x8,%YMM5,%YMM16,%YMM11

0x48ddb7 VADDPD	%YMM11,%YMM16,%YMM11

0x48ddbd VRNDSCALEPD	$0xb,%YMM11,%YMM21

0x48ddc4 VSUBPD	%YMM24,%YMM12,%YMM12

0x48ddca VSUBPD	%YMM23,%YMM13,%YMM11

0x48ddd0 VMOVDQA	%YMM6,%YMM13

0x48ddd4 VPTERNLOGQ	$-0x8,%YMM5,%YMM15,%YMM13

0x48dddb VADDPD	%YMM13,%YMM15,%YMM13

0x48dde0 VROUNDPD	$0xb,%YMM13,%YMM13

0x48dde6 VSUBPD	%YMM22,%YMM7,%YMM7

0x48ddec VSUBPD	%YMM20,%YMM8,%YMM8

0x48ddf2 VMOVDQA64	%YMM6,%YMM20

0x48ddf8 VPTERNLOGQ	$-0x8,%YMM5,%YMM10,%YMM20

0x48ddff VADDPD	%YMM20,%YMM10,%YMM20

0x48de05 VRNDSCALEPD	$0xb,%YMM20,%YMM23

0x48de0c VSUBPD	%YMM13,%YMM15,%YMM13

0x48de11 VSUBPD	%YMM21,%YMM16,%YMM15

0x48de17 VMOVDQA64	%YMM6,%YMM16

0x48de1d VPTERNLOGQ	$-0x8,%YMM5,%YMM17,%YMM16

0x48de24 VADDPD	%YMM16,%YMM17,%YMM16

0x48de2a VRNDSCALEPD	$0xb,%YMM16,%YMM24

0x48de31 VMOVDQA64	%YMM6,%YMM16

0x48de37 VSUBPD	%YMM26,%YMM14,%YMM20

0x48de3d VPTERNLOGQ	$-0x8,%YMM5,%YMM18,%YMM16

0x48de44 VADDPD	%YMM16,%YMM18,%YMM14

0x48de4a VROUNDPD	$0xb,%YMM14,%YMM14

0x48de50 VMOVDQA64	%YMM6,%YMM16

0x48de56 VPTERNLOGQ	$-0x8,%YMM5,%YMM19,%YMM16

0x48de5d VSUBPD	%YMM25,%YMM9,%YMM21

0x48de63 VADDPD	%YMM16,%YMM19,%YMM9

0x48de69 VROUNDPD	$0xb,%YMM9,%YMM9

0x48de6f VSUBPD	%YMM9,%YMM19,%YMM22

0x48de75 VBROADCASTSD	(%RDI),%YMM25    [2]

0x48de7b VSUBPD	%YMM14,%YMM18,%YMM19

0x48de81 VMULPD	%YMM8,%YMM25,%YMM9

0x48de87 VMULPD	%YMM7,%YMM25,%YMM14

0x48de8d VMULPD	%YMM11,%YMM25,%YMM16

0x48de93 VMULPD	%YMM12,%YMM25,%YMM18

0x48de99 VBROADCASTSD	0x8(%RDI),%YMM25    [2]

0x48dea0 VSUBPD	%YMM24,%YMM17,%YMM17

0x48dea6 VFMADD231PD	%YMM21,%YMM25,%YMM18

0x48deac VFMADD231PD	%YMM20,%YMM25,%YMM16

0x48deb2 VFMADD231PD	%YMM15,%YMM25,%YMM14

0x48deb8 VFMADD231PD	%YMM25,%YMM13,%YMM9

0x48debe VBROADCASTSD	0x10(%RDI),%YMM24    [2]

0x48dec5 VSUBPD	%YMM23,%YMM10,%YMM23

0x48decb VFMADD231PD	%YMM24,%YMM23,%YMM9

0x48ded1 VFMADD231PD	%YMM24,%YMM17,%YMM14

0x48ded7 VFMADD231PD	%YMM24,%YMM19,%YMM16

0x48dedd VFMADD231PD	%YMM24,%YMM22,%YMM18

0x48dee3 VMOVUPD	%YMM18,0x60(%R8,%R15,8)    [1]

0x48deeb VMOVUPD	%YMM16,0x40(%R8,%R15,8)    [1]

0x48def3 VMOVUPD	%YMM14,0x20(%R8,%R15,8)    [1]

0x48defa VMOVUPD	%YMM9,(%R8,%R15,8)    [1]

0x48df00 VBROADCASTSD	0x18(%RDI),%YMM24    [2]

0x48df07 VMULPD	%YMM12,%YMM24,%YMM10

0x48df0d VMULPD	%YMM8,%YMM24,%YMM25

0x48df13 VMULPD	%YMM7,%YMM24,%YMM26

0x48df19 VBROADCASTSD	0x20(%RDI),%YMM27    [2]

0x48df20 VMULPD	%YMM11,%YMM24,%YMM24

0x48df26 VFMADD231PD	%YMM20,%YMM27,%YMM24

0x48df2c VFMADD231PD	%YMM15,%YMM27,%YMM26

0x48df32 VFMADD231PD	%YMM13,%YMM27,%YMM25

0x48df38 VFMADD231PD	%YMM27,%YMM21,%YMM10

0x48df3e VBROADCASTSD	0x28(%RDI),%YMM27    [2]

0x48df45 VFMADD231PD	%YMM22,%YMM27,%YMM10

0x48df4b VFMADD231PD	%YMM17,%YMM27,%YMM26

0x48df51 VFMADD231PD	%YMM27,%YMM19,%YMM24

0x48df57 VMOVUPD	%YMM24,0x40(%RBX,%R15,8)    [6]

0x48df5f VMOVUPD	%YMM26,0x20(%RBX,%R15,8)    [6]

0x48df67 VFMADD231PD	%YMM23,%YMM27,%YMM25

0x48df6d VMOVUPD	%YMM25,(%RBX,%R15,8)    [6]

0x48df74 VMOVUPD	%YMM10,0x60(%RBX,%R15,8)    [6]

0x48df7b VBROADCASTSD	0x30(%RDI),%YMM27    [2]

0x48df82 VMULPD	%YMM12,%YMM27,%YMM12

0x48df88 VMULPD	%YMM8,%YMM27,%YMM8

0x48df8e VMULPD	%YMM7,%YMM27,%YMM7

0x48df94 VMULPD	%YMM11,%YMM27,%YMM11

0x48df9a VBROADCASTSD	0x38(%RDI),%YMM27    [2]

0x48dfa1 VFMADD231PD	%YMM20,%YMM27,%YMM11

0x48dfa7 VFMADD231PD	%YMM15,%YMM27,%YMM7

0x48dfad VFMADD231PD	%YMM13,%YMM27,%YMM8

0x48dfb3 VFMADD231PD	%YMM21,%YMM27,%YMM12

0x48dfb9 VBROADCASTSD	0x40(%RDI),%YMM13    [2]

0x48dfbf VFMADD231PD	%YMM22,%YMM13,%YMM12

0x48dfc5 VFMADD231PD	%YMM23,%YMM13,%YMM8

0x48dfcb VFMADD231PD	%YMM17,%YMM13,%YMM7

0x48dfd1 VFMADD231PD	%YMM19,%YMM13,%YMM11

0x48dfd7 VMULPD	%YMM16,%YMM16,%YMM13

0x48dfdd VMULPD	%YMM18,%YMM18,%YMM15

0x48dfe3 VMOVUPD	%YMM11,0x40(%R11,%R15,8)    [4]

0x48dfea VMULPD	%YMM9,%YMM9,%YMM9

0x48dfef VMULPD	%YMM14,%YMM14,%YMM14

0x48dff4 VFMADD231PD	%YMM26,%YMM26,%YMM14

0x48dffa VFMADD231PD	%YMM25,%YMM25,%YMM9

0x48e000 VMOVUPD	%YMM7,0x20(%R11,%R15,8)    [4]

0x48e007 VFMADD231PD	%YMM10,%YMM10,%YMM15

0x48e00c VFMADD231PD	%YMM24,%YMM24,%YMM13

0x48e012 VFMADD231PD	%YMM11,%YMM11,%YMM13

0x48e017 VFMADD231PD	%YMM12,%YMM12,%YMM15

0x48e01c VMOVUPD	%YMM8,(%R11,%R15,8)    [4]

0x48e022 VFMADD231PD	%YMM8,%YMM8,%YMM9

0x48e027 VFMADD231PD	%YMM7,%YMM7,%YMM14

0x48e02c VSQRTPD	%YMM14,%YMM7

0x48e031 VSQRTPD	%YMM9,%YMM8

0x48e036 VMOVUPD	%YMM12,0x60(%R11,%R15,8)    [4]

0x48e03d VSQRTPD	%YMM15,%YMM9

0x48e042 VSQRTPD	%YMM13,%YMM10

0x48e047 VMOVUPD	%YMM10,0x40(%RCX,%R15,8)    [7]

0x48e04e VMOVUPD	%YMM9,0x60(%RCX,%R15,8)    [7]

0x48e055 VMOVUPD	%YMM8,(%RCX,%R15,8)    [7]

0x48e05b VMOVUPD	%YMM7,0x20(%RCX,%R15,8)    [7]

0x48e062 ADD	$0x10,%R13D

0x48e066 CMP	%R12D,%R13D

0x48e069 JBE	48db60

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 235 - 256

--------------------------------------------------------------------------------

235:     for (int iat = first; iat < last; ++iat)

236:     {

237:       T displ_0 = px[iat] - x0;

238:       T displ_1 = py[iat] - y0;

239:       T displ_2 = pz[iat] - z0;

240:

241:       T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

242:       T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

243:       T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

244:

245:       //put them in the box

246:       ar_0 -= round(ar_0);

247:       ar_1 -= round(ar_1);

248:       ar_2 -= round(ar_2);

249:

250:       //unit2cart

251:       dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

252:       dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

253:       dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

254:

255:       temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

256:     }

Coverage (%)	Name	Source Location	Module
►40.12+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableAAOMPTarget.h:283	exec
○	qmcplusplus::ParticleSet::comp[...]	ParticleSet.cpp:343	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►37.27+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableAAOMPTarget.h:275	exec
○	qmcplusplus::ParticleSet::comp[...]	ParticleSet.cpp:343	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►9.76+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableAAOMPTarget.h:185	exec
○	qmcplusplus::ParticleSet::upda[...]	ParticleSet.cpp:242	exec
○	main.extracted.112	miniqmc.cpp:396	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►9.75+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableABOMPTarget.h:366	exec
○	qmcplusplus::ParticleSet::comp[...]	ParticleSet.cpp:343	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►3.10+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableABOMPTarget.h:361	exec
○	qmcplusplus::ParticleSet::comp[...]	ParticleSet.cpp:343	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.67
CQA speedup if fully vectorized	1.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P1,
Function	void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer > >(qmcplusplus::TinyVector const&, qmcplusplus::VectorSoAContainer > const&, double*, qmcplusplus::VectorSoAContainer >&, int, int, int) const
Source	ParticleBConds3DSoa.h:235-256
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	60.00
CQA cycles if no scalar integer	60.00
CQA cycles if FP arith vectorized	36.00
CQA cycles if fully vectorized	36.00
Front-end cycles	37.00
P0 cycles	59.00
P1 cycles	60.00
P2 cycles	10.00
P3 cycles	10.00
P4 cycles	8.00
P5 cycles	42.00
P6 cycles	2.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	2.00
P11 cycles	10.00
DIV/SQRT cycles	36.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	211.00
Nb uops	222.00
Nb loads	30.00
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	12.00
Nb FLOP add-sub	144.00
Nb FLOP mul	112.00
Nb FLOP fma	224.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	16.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.33
Bytes prefetched	0.00
Bytes loaded	528.00
Bytes stored	512.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	7.00
Vectorization ratio all	91.26
Vectorization ratio load	40.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	66.67
Vector-efficiency ratio all	46.72
Vector-efficiency ratio load	27.50
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	37.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.67
CQA speedup if fully vectorized	1.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P1,
Function	void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer > >(qmcplusplus::TinyVector const&, qmcplusplus::VectorSoAContainer > const&, double*, qmcplusplus::VectorSoAContainer >&, int, int, int) const
Source	ParticleBConds3DSoa.h:235-256
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	60.00
CQA cycles if no scalar integer	60.00
CQA cycles if FP arith vectorized	36.00
CQA cycles if fully vectorized	36.00
Front-end cycles	37.00
P0 cycles	59.00
P1 cycles	60.00
P2 cycles	10.00
P3 cycles	10.00
P4 cycles	8.00
P5 cycles	42.00
P6 cycles	2.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	2.00
P11 cycles	10.00
DIV/SQRT cycles	36.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	211.00
Nb uops	222.00
Nb loads	30.00
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	12.00
Nb FLOP add-sub	144.00
Nb FLOP mul	112.00
Nb FLOP fma	224.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	16.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.33
Bytes prefetched	0.00
Bytes loaded	528.00
Bytes stored	512.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	7.00
Vectorization ratio all	91.26
Vectorization ratio load	40.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	66.67
Vector-efficiency ratio all	46.72
Vector-efficiency ratio load	27.50
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	37.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer > >(qmcplusplus::TinyVector const&, qmcplusplus::VectorSoAContainer > const&, double*, qmcplusplus::VectorSoAContainer >&, int, int, int) const
Source file and lines	ParticleBConds3DSoa.h:235-256
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:235-256.

It is main loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 46% of vector register length is used (average across all SSE/AVX instructions).

Details

91% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

40% of SSE/AVX loads are used in vector version.
66% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 224 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VRNDSCALEPD: 9 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:246
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:246
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:246
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:246
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:247
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:247
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:247
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:248
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:248
VROUNDPD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:247
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:248
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:248

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 7 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 28 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 28 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:237
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:237
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:237
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:237
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:238
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:238
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:238
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:238
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:239
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:239
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:239
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:239
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:251
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:251
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:251
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:251
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:252
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:252
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:252
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:252
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:253
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:253
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:253
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:253
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:255
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:255
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:255
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:255

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

136 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 720 FP arithmetical operations:

368: addition or subtraction (224 inside FMA instructions)
336: multiply (224 inside FMA instructions)
16: square root

The binary loop is loading 528 bytes (66 double precision FP elements). The binary loop is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.69 FP operations per loaded or stored byte.

General properties

nb instructions	211
nb uops	222
loop length	1295
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	27
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	37.00 cycles
front end	37.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	59.00	59.00	10.00	10.00	8.00	42.00	2.00	8.00	8.00	8.00	2.00	10.00
cycles	59.00	60.00	10.00	10.00	8.00	42.00	2.00	8.00	8.00	8.00	2.00	10.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	36.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	37.00
Dispatch	60.00
DIV/SQRT	36.00
Data deps.	1.00
Overall L1	60.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	90%
load	40%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	40%

INT+FP

all	91%
load	40%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	66%

Vector efficiency ratios

INT

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	46%
load	27%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	27%

INT+FP

all	46%
load	27%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	37%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 60.00 cycles. At this rate:

4% of peak load performance is reached (8.80 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.53 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 48db60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LEA (%R9,%R13,1),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVSXD %R15D,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
VMOVUPD (%RDX,%R15,8),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%RDX,%R15,8),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%RDX,%R15,8),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x60(%RDX,%R15,8),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPD %YMM2,%YMM7,%YMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM2,%YMM8,%YMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM2,%YMM9,%YMM18	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM2,%YMM11,%YMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R10,%R15,8),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R10,%R15,8),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%R10,%R15,8),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x60(%R10,%R15,8),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPD %YMM3,%YMM11,%YMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM3,%YMM9,%YMM22	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM3,%YMM8,%YMM24	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%RSI,%R15,8),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%RSI,%R15,8),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%RSI,%R15,8),%YMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x60(%RSI,%R15,8),%YMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPD %YMM3,%YMM7,%YMM26	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM4,%YMM8,%YMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM4,%YMM9,%YMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM4,%YMM12,%YMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM4,%YMM13,%YMM25	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VBROADCASTSD 0x48(%RDI),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD %YMM19,%YMM8,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM18,%YMM8,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM17,%YMM8,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM10,%YMM8,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x50(%RDI),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM26,%YMM9,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM9,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM22,%YMM9,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x60(%RDI),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD %YMM10,%YMM27,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM17,%YMM27,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM18,%YMM27,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM9,%YMM21,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM19,%YMM27,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x68(%RDI),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM21,%YMM27,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM22,%YMM27,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x78(%RDI),%YMM28	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM24,%YMM27,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM19,%YMM28,%YMM19	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM18,%YMM28,%YMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM17,%YMM28,%YMM17	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM10,%YMM28,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x80(%RDI),%YMM28	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM27,%YMM26,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM26,%YMM28,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x58(%RDI),%YMM26	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM25,%YMM26,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM26,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM20,%YMM26,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM26,%YMM11,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x70(%RDI),%YMM26	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM11,%YMM26,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM20,%YMM26,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM26,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM28,%YMM17	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM26,%YMM25,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM22,%YMM28,%YMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM28,%YMM19	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x88(%RDI),%YMM21	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM25,%YMM21,%YMM19	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM21,%YMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVDQA64 %YMM6,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD231PD %YMM20,%YMM21,%YMM17	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM8,%YMM22	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM22,%YMM8,%YMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA64 %YMM6,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM7,%YMM22	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM22,%YMM7,%YMM22	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM20,%YMM20	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VRNDSCALEPD $0xb,%YMM22,%YMM22	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VMOVDQA64 %YMM6,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM13,%YMM23	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM23,%YMM13,%YMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA64 %YMM6,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VRNDSCALEPD $0xb,%YMM23,%YMM23	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM12,%YMM24	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM24,%YMM12,%YMM24	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM24,%YMM24	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VMOVDQA64 %YMM6,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM9,%YMM25	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM25,%YMM9,%YMM25	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM25,%YMM25	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VMOVDQA64 %YMM6,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM14,%YMM26	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM26,%YMM14,%YMM26	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM26,%YMM26	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VFMADD231PD %YMM11,%YMM21,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVDQA %YMM6,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM16,%YMM11	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM11,%YMM16,%YMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM11,%YMM21	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VSUBPD %YMM24,%YMM12,%YMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM23,%YMM13,%YMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA %YMM6,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM15,%YMM13	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM13,%YMM15,%YMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VROUNDPD $0xb,%YMM13,%YMM13	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VSUBPD %YMM22,%YMM7,%YMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM20,%YMM8,%YMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA64 %YMM6,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM10,%YMM20	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM20,%YMM10,%YMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM20,%YMM23	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VSUBPD %YMM13,%YMM15,%YMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM21,%YMM16,%YMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA64 %YMM6,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM17,%YMM16	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM16,%YMM17,%YMM16	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM16,%YMM24	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VMOVDQA64 %YMM6,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VSUBPD %YMM26,%YMM14,%YMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM18,%YMM16	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM16,%YMM18,%YMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VROUNDPD $0xb,%YMM14,%YMM14	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VMOVDQA64 %YMM6,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM19,%YMM16	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VSUBPD %YMM25,%YMM9,%YMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM16,%YMM19,%YMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VROUNDPD $0xb,%YMM9,%YMM9	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VSUBPD %YMM9,%YMM19,%YMM22	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VBROADCASTSD (%RDI),%YMM25	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VSUBPD %YMM14,%YMM18,%YMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM8,%YMM25,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM7,%YMM25,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM11,%YMM25,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM12,%YMM25,%YMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x8(%RDI),%YMM25	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VSUBPD %YMM24,%YMM17,%YMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM25,%YMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM20,%YMM25,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM25,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM25,%YMM13,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x10(%RDI),%YMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VSUBPD %YMM23,%YMM10,%YMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM23,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM17,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM19,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM22,%YMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM18,0x60(%R8,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM16,0x40(%R8,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM14,0x20(%R8,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM9,(%R8,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD 0x18(%RDI),%YMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD %YMM12,%YMM24,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM8,%YMM24,%YMM25	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM7,%YMM24,%YMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x20(%RDI),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD %YMM11,%YMM24,%YMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM20,%YMM27,%YMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM27,%YMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM13,%YMM27,%YMM25	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM27,%YMM21,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x28(%RDI),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM22,%YMM27,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM17,%YMM27,%YMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM27,%YMM19,%YMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM24,0x40(%RBX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM26,0x20(%RBX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM27,%YMM25	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM25,(%RBX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM10,0x60(%RBX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD 0x30(%RDI),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD %YMM12,%YMM27,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM8,%YMM27,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM7,%YMM27,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM11,%YMM27,%YMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x38(%RDI),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM20,%YMM27,%YMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM27,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM13,%YMM27,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM27,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x40(%RDI),%YMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM22,%YMM13,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM13,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM17,%YMM13,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM19,%YMM13,%YMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM16,%YMM16,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM18,%YMM18,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM11,0x40(%R11,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMULPD %YMM9,%YMM9,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM14,%YMM14,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM26,%YMM26,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM25,%YMM25,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM7,0x20(%R11,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VFMADD231PD %YMM10,%YMM10,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM24,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM11,%YMM11,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM12,%YMM12,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM8,(%R11,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VFMADD231PD %YMM8,%YMM8,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM7,%YMM7,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VSQRTPD %YMM14,%YMM7	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VSQRTPD %YMM9,%YMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VMOVUPD %YMM12,0x60(%R11,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VSQRTPD %YMM15,%YMM9	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VSQRTPD %YMM13,%YMM10	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VMOVUPD %YMM10,0x40(%RCX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM9,0x60(%RCX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM8,(%RCX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM7,0x20(%RCX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x10,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R12D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JBE 48db60 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0xa0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer > >(qmcplusplus::TinyVector const&, qmcplusplus::VectorSoAContainer > const&, double*, qmcplusplus::VectorSoAContainer >&, int, int, int) const
Source file and lines	ParticleBConds3DSoa.h:235-256
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 46% of vector register length is used (average across all SSE/AVX instructions).

Details

91% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

40% of SSE/AVX loads are used in vector version.
66% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 224 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VRNDSCALEPD: 9 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:246
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:246
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:246
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:246
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:247
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:247
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:247
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:248
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:248
VROUNDPD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:247
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:248
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:248

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 7 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 28 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 28 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:237
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:237
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:237
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:237
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:238
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:238
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:238
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:238
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:239
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:239
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:239
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:239
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:251
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:251
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:251
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:251
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:252
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:252
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:252
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:252
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:253
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:253
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:253
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:253
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:255
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:255
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:255
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:255

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

136 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 720 FP arithmetical operations:

368: addition or subtraction (224 inside FMA instructions)
336: multiply (224 inside FMA instructions)
16: square root

The binary loop is loading 528 bytes (66 double precision FP elements). The binary loop is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.69 FP operations per loaded or stored byte.

General properties

nb instructions	211
nb uops	222
loop length	1295
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	27
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	37.00 cycles
front end	37.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	59.00	59.00	10.00	10.00	8.00	42.00	2.00	8.00	8.00	8.00	2.00	10.00
cycles	59.00	60.00	10.00	10.00	8.00	42.00	2.00	8.00	8.00	8.00	2.00	10.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	36.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	37.00
Dispatch	60.00
DIV/SQRT	36.00
Data deps.	1.00
Overall L1	60.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	90%
load	40%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	40%

INT+FP

all	91%
load	40%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	66%

Vector efficiency ratios

INT

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	46%
load	27%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	27%

INT+FP

all	46%
load	27%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	37%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 60.00 cycles. At this rate:

4% of peak load performance is reached (8.80 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.53 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 48db60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LEA (%R9,%R13,1),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVSXD %R15D,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
VMOVUPD (%RDX,%R15,8),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%RDX,%R15,8),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%RDX,%R15,8),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x60(%RDX,%R15,8),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPD %YMM2,%YMM7,%YMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM2,%YMM8,%YMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM2,%YMM9,%YMM18	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM2,%YMM11,%YMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R10,%R15,8),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R10,%R15,8),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%R10,%R15,8),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x60(%R10,%R15,8),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPD %YMM3,%YMM11,%YMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM3,%YMM9,%YMM22	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM3,%YMM8,%YMM24	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%RSI,%R15,8),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%RSI,%R15,8),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%RSI,%R15,8),%YMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x60(%RSI,%R15,8),%YMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPD %YMM3,%YMM7,%YMM26	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM4,%YMM8,%YMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM4,%YMM9,%YMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM4,%YMM12,%YMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM4,%YMM13,%YMM25	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VBROADCASTSD 0x48(%RDI),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD %YMM19,%YMM8,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM18,%YMM8,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM17,%YMM8,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM10,%YMM8,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x50(%RDI),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM26,%YMM9,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM9,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM22,%YMM9,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x60(%RDI),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD %YMM10,%YMM27,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM17,%YMM27,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM18,%YMM27,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM9,%YMM21,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM19,%YMM27,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x68(%RDI),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM21,%YMM27,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM22,%YMM27,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x78(%RDI),%YMM28	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM24,%YMM27,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM19,%YMM28,%YMM19	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM18,%YMM28,%YMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM17,%YMM28,%YMM17	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM10,%YMM28,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x80(%RDI),%YMM28	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM27,%YMM26,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM26,%YMM28,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x58(%RDI),%YMM26	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM25,%YMM26,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM26,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM20,%YMM26,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM26,%YMM11,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x70(%RDI),%YMM26	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM11,%YMM26,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM20,%YMM26,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM26,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM28,%YMM17	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM26,%YMM25,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM22,%YMM28,%YMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM28,%YMM19	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x88(%RDI),%YMM21	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM25,%YMM21,%YMM19	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM21,%YMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVDQA64 %YMM6,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD231PD %YMM20,%YMM21,%YMM17	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM8,%YMM22	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM22,%YMM8,%YMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA64 %YMM6,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM7,%YMM22	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM22,%YMM7,%YMM22	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM20,%YMM20	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VRNDSCALEPD $0xb,%YMM22,%YMM22	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VMOVDQA64 %YMM6,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM13,%YMM23	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM23,%YMM13,%YMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA64 %YMM6,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VRNDSCALEPD $0xb,%YMM23,%YMM23	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM12,%YMM24	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM24,%YMM12,%YMM24	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM24,%YMM24	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VMOVDQA64 %YMM6,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM9,%YMM25	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM25,%YMM9,%YMM25	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM25,%YMM25	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VMOVDQA64 %YMM6,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM14,%YMM26	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM26,%YMM14,%YMM26	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM26,%YMM26	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VFMADD231PD %YMM11,%YMM21,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVDQA %YMM6,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM16,%YMM11	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM11,%YMM16,%YMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM11,%YMM21	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VSUBPD %YMM24,%YMM12,%YMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM23,%YMM13,%YMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA %YMM6,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM15,%YMM13	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM13,%YMM15,%YMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VROUNDPD $0xb,%YMM13,%YMM13	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VSUBPD %YMM22,%YMM7,%YMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM20,%YMM8,%YMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA64 %YMM6,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM10,%YMM20	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM20,%YMM10,%YMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM20,%YMM23	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VSUBPD %YMM13,%YMM15,%YMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM21,%YMM16,%YMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA64 %YMM6,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM17,%YMM16	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM16,%YMM17,%YMM16	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0xb,%YMM16,%YMM24	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VMOVDQA64 %YMM6,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VSUBPD %YMM26,%YMM14,%YMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM18,%YMM16	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM16,%YMM18,%YMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VROUNDPD $0xb,%YMM14,%YMM14	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VMOVDQA64 %YMM6,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM19,%YMM16	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VSUBPD %YMM25,%YMM9,%YMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM16,%YMM19,%YMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VROUNDPD $0xb,%YMM9,%YMM9	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VSUBPD %YMM9,%YMM19,%YMM22	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VBROADCASTSD (%RDI),%YMM25	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VSUBPD %YMM14,%YMM18,%YMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM8,%YMM25,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM7,%YMM25,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM11,%YMM25,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM12,%YMM25,%YMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x8(%RDI),%YMM25	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VSUBPD %YMM24,%YMM17,%YMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM25,%YMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM20,%YMM25,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM25,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM25,%YMM13,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x10(%RDI),%YMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VSUBPD %YMM23,%YMM10,%YMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM23,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM17,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM19,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM22,%YMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM18,0x60(%R8,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM16,0x40(%R8,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM14,0x20(%R8,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM9,(%R8,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD 0x18(%RDI),%YMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD %YMM12,%YMM24,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM8,%YMM24,%YMM25	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM7,%YMM24,%YMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x20(%RDI),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD %YMM11,%YMM24,%YMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM20,%YMM27,%YMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM27,%YMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM13,%YMM27,%YMM25	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM27,%YMM21,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x28(%RDI),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM22,%YMM27,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM17,%YMM27,%YMM26	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM27,%YMM19,%YMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM24,0x40(%RBX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM26,0x20(%RBX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM27,%YMM25	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM25,(%RBX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM10,0x60(%RBX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VBROADCASTSD 0x30(%RDI),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD %YMM12,%YMM27,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM8,%YMM27,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM7,%YMM27,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM11,%YMM27,%YMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x38(%RDI),%YMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM20,%YMM27,%YMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM27,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM13,%YMM27,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM27,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x40(%RDI),%YMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VFMADD231PD %YMM22,%YMM13,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM13,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM17,%YMM13,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM19,%YMM13,%YMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM16,%YMM16,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM18,%YMM18,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM11,0x40(%R11,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMULPD %YMM9,%YMM9,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM14,%YMM14,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM26,%YMM26,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM25,%YMM25,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM7,0x20(%R11,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VFMADD231PD %YMM10,%YMM10,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM24,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM11,%YMM11,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM12,%YMM12,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM8,(%R11,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VFMADD231PD %YMM8,%YMM8,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM7,%YMM7,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VSQRTPD %YMM14,%YMM7	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VSQRTPD %YMM9,%YMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VMOVUPD %YMM12,0x60(%R11,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VSQRTPD %YMM15,%YMM9	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VSQRTPD %YMM13,%YMM10	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VMOVUPD %YMM10,0x40(%RCX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM9,0x60(%RCX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM8,(%RCX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM7,0x20(%RCX,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x10,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R12D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JBE 48db60 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0xa0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code