OV - exec - Loop 1056

0x45f680 VMOVUPS	%XMM0,-0xb0(%RDX)    [1]

0x45f688 VMOVUPS	%XMM0,-0xa0(%RDX)    [1]

0x45f690 VMOVUPS	%XMM0,-0x90(%RDX)    [1]

0x45f698 VMOVUPS	%XMM0,-0x80(%RDX)    [1]

0x45f69d VMOVUPS	%XMM0,-0x70(%RDX)    [1]

0x45f6a2 VMOVUPS	%XMM0,-0x60(%RDX)    [1]

0x45f6a7 VMOVUPS	%XMM0,-0x50(%RDX)    [1]

0x45f6ac VMOVUPS	%XMM0,-0x40(%RDX)    [1]

0x45f6b1 VMOVUPS	%XMM0,-0x30(%RDX)    [1]

0x45f6b6 VMOVUPS	%XMM0,-0x20(%RDX)    [1]

0x45f6bb VMOVUPS	%XMM0,-0x10(%RDX)    [1]

0x45f6c0 VMOVUPS	%XMM0,(%RDX)    [1]

0x45f6c4 ADD	$0xc0,%RDX

0x45f6cb DEC	%RCX

0x45f6ce JNE	45f680

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h: 911 - 912

--------------------------------------------------------------------------------

911:       for (; __first != __last; ++__first)

912: 	*__first = __value;

Coverage (%)	Name	Source Location	Module
►54.38+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	qmcplusplus::build_WaveFunctio[...]	WaveFunction.cpp:80	exec
○	main.extracted.112	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►45.62+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	qmcplusplus::build_WaveFunctio[...]	WaveFunction.cpp:81	exec
○	main.extracted.112	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.57
Bottlenecks	P4, P7, P8, P9,
Function	miniqmcreference::DiracDeterminantRef >::resize(int, int)
Source	stl_algobase.h:911-912
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	1.50
Front-end cycles	2.33
P0 cycles	0.50
P1 cycles	0.40
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	6.00
P5 cycles	0.40
P6 cycles	0.50
P7 cycles	6.00
P8 cycles	6.00
P9 cycles	6.00
P10 cycles	0.20
P11 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	15.00
Nb uops	14.00
Nb loads	0.00
Nb stores	12.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	192.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.57
Bottlenecks	P4, P7, P8, P9,
Function	miniqmcreference::DiracDeterminantRef >::resize(int, int)
Source	stl_algobase.h:911-912
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	1.50
Front-end cycles	2.33
P0 cycles	0.50
P1 cycles	0.40
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	6.00
P5 cycles	0.40
P6 cycles	0.50
P7 cycles	6.00
P8 cycles	6.00
P9 cycles	6.00
P10 cycles	0.20
P11 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	15.00
Nb uops	14.00
Nb loads	0.00
Nb stores	12.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	192.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::DiracDeterminantRef >::resize(int, int)
Source file and lines	stl_algobase.h:911-912
Module	exec

The loop is defined in /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:911-912.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 128 out of 512 bits (SSE/AVX-128 instructions on AVX-512 processors). By fully vectorizing your loop, you can lower the cost of an iteration from 6.00 to 1.50 cycles (4.00x speedup).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck).

Workaround

Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 192 bytes.

General properties

nb instructions	15
nb uops	14
loop length	80
used x86 registers	2
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.33 cycles
front end	2.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	0.50	0.40	0.00	0.00	6.00	0.40	0.50	6.00	6.00	6.00	0.20	0.00
cycles	0.50	0.40	0.00	0.00	6.00	0.40	0.50	6.00	6.00	6.00	0.20	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.33
Dispatch	6.00
Data deps.	1.00
Overall L1	6.00

Vectorization ratios

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

25% of peak store performance is reached (32.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 45f680

Instruction	Nb FU	P0	P1	P4	P5	P6	P7	P8	P9	P10	Latency	Recip. throughput	Vectorization
VMOVUPS %XMM0,-0xb0(%RDX)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
VMOVUPS %XMM0,-0xa0(%RDX)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
VMOVUPS %XMM0,-0x90(%RDX)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
VMOVUPS %XMM0,-0x80(%RDX)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
VMOVUPS %XMM0,-0x70(%RDX)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
VMOVUPS %XMM0,-0x60(%RDX)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
VMOVUPS %XMM0,-0x50(%RDX)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
VMOVUPS %XMM0,-0x40(%RDX)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
VMOVUPS %XMM0,-0x30(%RDX)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
VMOVUPS %XMM0,-0x20(%RDX)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
VMOVUPS %XMM0,-0x10(%RDX)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
VMOVUPS %XMM0,(%RDX)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
ADD $0xc0,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
DEC %RCX	1	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 45f680 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x400>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A

Function	miniqmcreference::DiracDeterminantRef >::resize(int, int)
Source file and lines	stl_algobase.h:911-912
Module	exec

The loop is defined in /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:911-912.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 128 out of 512 bits (SSE/AVX-128 instructions on AVX-512 processors). By fully vectorizing your loop, you can lower the cost of an iteration from 6.00 to 1.50 cycles (4.00x speedup).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck).

Workaround

Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 192 bytes.

General properties

nb instructions	15
nb uops	14
loop length	80
used x86 registers	2
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.33 cycles
front end	2.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	0.50	0.40	0.00	0.00	6.00	0.40	0.50	6.00	6.00	6.00	0.20	0.00
cycles	0.50	0.40	0.00	0.00	6.00	0.40	0.50	6.00	6.00	6.00	0.20	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.33
Dispatch	6.00
Data deps.	1.00
Overall L1	6.00

Vectorization ratios

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

25% of peak store performance is reached (32.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 45f680

Instruction	Nb FU	P0	P1	P4	P5	P6	P7	P8	P9	P10	Latency	Recip. throughput	Vectorization
VMOVUPS %XMM0,-0xb0(%RDX)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
VMOVUPS %XMM0,-0xa0(%RDX)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
VMOVUPS %XMM0,-0x90(%RDX)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
VMOVUPS %XMM0,-0x80(%RDX)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
VMOVUPS %XMM0,-0x70(%RDX)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
VMOVUPS %XMM0,-0x60(%RDX)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
VMOVUPS %XMM0,-0x50(%RDX)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
VMOVUPS %XMM0,-0x40(%RDX)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
VMOVUPS %XMM0,-0x30(%RDX)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
VMOVUPS %XMM0,-0x20(%RDX)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
VMOVUPS %XMM0,-0x10(%RDX)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
VMOVUPS %XMM0,(%RDX)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
ADD $0xc0,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
DEC %RCX	1	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 45f680 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x400>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code