OV - exec - Loop 1046

0x45e410 VMOVDDUP	(%R8,%R10,1),%XMM4    [1]

0x45e416 VFMADD231SD	-0x48(%R14),%XMM4,%XMM3    [2]

0x45e41c VMOVDDUP	0x8(%R8,%R10,1),%XMM5    [1]

0x45e423 VFMADD231SD	-0x30(%R14),%XMM5,%XMM3    [2]

0x45e429 VMOVDDUP	0x10(%R8,%R10,1),%XMM6    [1]

0x45e430 VFMADD231SD	-0x18(%R14),%XMM6,%XMM3    [2]

0x45e436 VFMADD231PD	-0x58(%R14),%XMM4,%XMM2    [2]

0x45e43c VFMADD231PD	-0x40(%R14),%XMM5,%XMM2    [2]

0x45e442 VFMADD231PD	-0x28(%R14),%XMM6,%XMM2    [2]

0x45e448 VMOVDDUP	0x18(%R8,%R10,1),%XMM4    [1]

0x45e44f VFMADD231PD	-0x10(%R14),%XMM4,%XMM2    [2]

0x45e455 VFMADD231SD	(%R14),%XMM4,%XMM3    [2]

0x45e45a ADD	$0x20,%R10

0x45e45e ADD	$0x60,%R14

0x45e462 CMP	%R10,%R12

0x45e465 JNE	45e410

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 155 - 155

--------------------------------------------------------------------------------

155:   for (int i = 0; i < n; i++)

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 63 - 63

--------------------------------------------------------------------------------

63:     return (a * b);

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp: 157 - 157

--------------------------------------------------------------------------------

157:   if (UpdateMode == ORB_PBYP_RATIO)

Coverage (%)	Name	Source Location	Module
►50.81+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:249	exec
○	main.extracted.107	miniqmc.cpp:467	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►49.19+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:249	exec
○	main.extracted.107	miniqmc.cpp:467	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.73
CQA speedup if fully vectorized	6.40
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	4.00
Bottlenecks
Function	miniqmcreference::DiracDeterminantRef >::evaluateGL(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus::ParticleAttrib >&, bool)
Source	inner_product.hpp:155-155,OperatorTags.h:63-63,DiracDeterminantRef.cpp:157-157
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	9.25
CQA cycles if fully vectorized	2.50
Front-end cycles	2.50
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	15.00
Nb loads	12.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.50
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	12.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.00
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	33.33
Vectorization ratio load	33.33
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	50.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	16.67
Vector-efficiency ratio load	16.67
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	18.75
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.73
CQA speedup if fully vectorized	6.40
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	4.00
Bottlenecks
Function	miniqmcreference::DiracDeterminantRef >::evaluateGL(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus::ParticleAttrib >&, bool)
Source	inner_product.hpp:155-155,OperatorTags.h:63-63,DiracDeterminantRef.cpp:157-157
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	9.25
CQA cycles if fully vectorized	2.50
Front-end cycles	2.50
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	15.00
Nb loads	12.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.50
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	12.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.00
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	33.33
Vectorization ratio load	33.33
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	50.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	16.67
Vector-efficiency ratio load	16.67
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	18.75
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::DiracDeterminantRef >::evaluateGL(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus::ParticleAttrib >&, bool)
Source file and lines	inner_product.hpp:155-155
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:157

It is main loop of related source loop which is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 16.00 to 2.50 cycles (6.40x speedup).

Details

33% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

33% of SSE/AVX loads are used in vector version.
50% of SSE/AVX fused multiply-add instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 12 FMA (fused multiply-add) operations.

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

12: addition or subtraction (all inside FMA instructions)
12: multiply (all inside FMA instructions)

The binary loop is loading 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	16
nb uops	15
loop length	87
used x86 registers	4
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.50 cycles
front end	2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.00	4.00	4.00	4.00	0.00	0.00	1.00	0.00	0.00	0.00	0.00	4.00
cycles	4.00	4.00	4.00	4.00	0.00	0.00	1.00	0.00	0.00	0.00	0.00	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	2.50
Dispatch	4.00
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

all	33%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	16%
load	16%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

4% of peak load performance is reached (8.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 45e410

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
VMOVDDUP (%R8,%R10,1),%XMM4	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD231SD -0x48(%R14),%XMM4,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVDDUP 0x8(%R8,%R10,1),%XMM5	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD231SD -0x30(%R14),%XMM5,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVDDUP 0x10(%R8,%R10,1),%XMM6	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD231SD -0x18(%R14),%XMM6,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231PD -0x58(%R14),%XMM4,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD231PD -0x40(%R14),%XMM5,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD231PD -0x28(%R14),%XMM6,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (25.0%)
VMOVDDUP 0x18(%R8,%R10,1),%XMM4	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD231PD -0x10(%R14),%XMM4,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD231SD (%R14),%XMM4,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x20,%R10	1	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x60,%R14	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%R12	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 45e410 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x390>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	miniqmcreference::DiracDeterminantRef >::evaluateGL(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus::ParticleAttrib >&, bool)
Source file and lines	inner_product.hpp:155-155
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:157

It is main loop of related source loop which is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 16.00 to 2.50 cycles (6.40x speedup).

Details

33% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

33% of SSE/AVX loads are used in vector version.
50% of SSE/AVX fused multiply-add instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 12 FMA (fused multiply-add) operations.

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

12: addition or subtraction (all inside FMA instructions)
12: multiply (all inside FMA instructions)

The binary loop is loading 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	16
nb uops	15
loop length	87
used x86 registers	4
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.50 cycles
front end	2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.00	4.00	4.00	4.00	0.00	0.00	1.00	0.00	0.00	0.00	0.00	4.00
cycles	4.00	4.00	4.00	4.00	0.00	0.00	1.00	0.00	0.00	0.00	0.00	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	2.50
Dispatch	4.00
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

all	33%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	16%
load	16%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

4% of peak load performance is reached (8.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 45e410

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
VMOVDDUP (%R8,%R10,1),%XMM4	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD231SD -0x48(%R14),%XMM4,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVDDUP 0x8(%R8,%R10,1),%XMM5	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD231SD -0x30(%R14),%XMM5,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVDDUP 0x10(%R8,%R10,1),%XMM6	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD231SD -0x18(%R14),%XMM6,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231PD -0x58(%R14),%XMM4,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD231PD -0x40(%R14),%XMM5,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD231PD -0x28(%R14),%XMM6,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (25.0%)
VMOVDDUP 0x18(%R8,%R10,1),%XMM4	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD231PD -0x10(%R14),%XMM4,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD231SD (%R14),%XMM4,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x20,%R10	1	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x60,%R14	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%R12	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 45e410 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x390>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code