OV - exec - Function void qmcplusplus::DTD_BConds<double, 3u, 40>::computeDistances<qmcplusplus::TinyVector<double, 3u>, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 64ul> >, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 64ul> > >(qmcplusplus::TinyVector<double, 3u> const&, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 64ul> > const&, double*, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 64ul> >&, int, int, int) const

	Function: void qmcplusplus::DTD_BConds<double, 3u, 40>::computeDistances<qmcplusplus::TinyVector<dou ...	Module: exec	Source: ParticleBConds3DSoa.h:221-257 [...]	Coverage (incl. loops): 1.48% \| (excl. loops): 0.01%

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 271 - 273

--------------------------------------------------------------------------------

271:   inline T* restrict data(size_t i) { return myData + i * nGhosts; }

272:   ///return the const pointer of the i-th components

273:   inline const T* restrict data(size_t i) const { return myData + i * nGhosts; }

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 221 - 257

--------------------------------------------------------------------------------

221:   {

222:     const T x0 = pos[0];

223:     const T y0 = pos[1];

224:     const T z0 = pos[2];

[...]

234: #pragma omp simd aligned(temp_r, px, py, pz, dx, dy, dz: QMC_SIMD_ALIGNMENT)

235:     for (int iat = first; iat < last; ++iat)

236:     {

237:       T displ_0 = px[iat] - x0;

238:       T displ_1 = py[iat] - y0;

239:       T displ_2 = pz[iat] - z0;

240:

241:       T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

242:       T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

243:       T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

244:

245:       //put them in the box

246:       ar_0 -= round(ar_0);

247:       ar_1 -= round(ar_1);

248:       ar_2 -= round(ar_2);

249:

250:       //unit2cart

251:       dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

252:       dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

253:       dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

254:

255:       temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

256:     }

257:   }

0x48dac0 PUSH	%RBP

0x48dac1 MOV	%RSP,%RBP

0x48dac4 PUSH	%R15

0x48dac6 PUSH	%R14

0x48dac8 PUSH	%R13

0x48daca PUSH	%R12

0x48dacc PUSH	%RBX

0x48dacd MOV	0x10(%RBP),%EAX

0x48dad0 MOV	%EAX,%R14D

0x48dad3 SUB	%R9D,%R14D

0x48dad6 JLE	48e3b4

0x48dadc VMOVUPD	(%RSI),%XMM0

0x48dae0 VMOVSD	0x10(%RSI),%XMM1

0x48dae5 MOV	0x8(%RDX),%RSI

0x48dae9 MOV	0x18(%RDX),%RDX

0x48daed LEA	(%RDX,%RSI,8),%R10

0x48daf1 SAL	$0x4,%RSI

0x48daf5 ADD	%RDX,%RSI

0x48daf8 MOV	0x8(%R8),%R11

0x48dafc MOV	0x18(%R8),%R8

0x48db00 LEA	(%R8,%R11,8),%RBX

0x48db04 SAL	$0x4,%R11

0x48db08 ADD	%R8,%R11

0x48db0b MOV	%R14D,%R13D

0x48db0e AND	$-0x4,%R13D

0x48db12 JE	48e0c0

0x48db18 MOV	%R14D,-0x2c(%RBP)

0x48db1c VBROADCASTSD	%XMM0,%YMM2

0x48db21 AND	$-0x10,%R14D

0x48db25 JE	48e100

0x48db2b MOV	%R13,-0x38(%RBP)

0x48db2f LEA	-0x1(%R14),%R12D

0x48db33 VPERMPD	$0x55,%YMM0,%YMM3

0x48db39 VBROADCASTSD	%XMM1,%YMM4

0x48db3e XOR	%R13D,%R13D

0x48db41 VPBROADCASTQ	0xa94fe(%RIP),%YMM5

0x48db4a VPBROADCASTQ	0xaf7ed(%RIP),%YMM6

0x48db53 NOPW	%CS:(%RAX,%RAX,1)

(1419) 0x48db60 LEA	(%R9,%R13,1),%R15D

(1419) 0x48db64 MOVSXD	%R15D,%R15

(1419) 0x48db67 VMOVUPD	(%RDX,%R15,8),%YMM7

(1419) 0x48db6d VMOVUPD	0x20(%RDX,%R15,8),%YMM8

(1419) 0x48db74 VMOVUPD	0x40(%RDX,%R15,8),%YMM9

(1419) 0x48db7b VMOVUPD	0x60(%RDX,%R15,8),%YMM11

(1419) 0x48db82 VSUBPD	%YMM2,%YMM7,%YMM10

(1419) 0x48db86 VSUBPD	%YMM2,%YMM8,%YMM17

(1419) 0x48db8c VSUBPD	%YMM2,%YMM9,%YMM18

(1419) 0x48db92 VSUBPD	%YMM2,%YMM11,%YMM19

(1419) 0x48db98 VMOVUPD	(%R10,%R15,8),%YMM7

(1419) 0x48db9e VMOVUPD	0x20(%R10,%R15,8),%YMM8

(1419) 0x48dba5 VMOVUPD	0x40(%R10,%R15,8),%YMM9

(1419) 0x48dbac VMOVUPD	0x60(%R10,%R15,8),%YMM11

(1419) 0x48dbb3 VSUBPD	%YMM3,%YMM11,%YMM21

(1419) 0x48dbb9 VSUBPD	%YMM3,%YMM9,%YMM22

(1419) 0x48dbbf VSUBPD	%YMM3,%YMM8,%YMM24

(1419) 0x48dbc5 VMOVUPD	(%RSI,%R15,8),%YMM8

(1419) 0x48dbcb VMOVUPD	0x20(%RSI,%R15,8),%YMM9

(1419) 0x48dbd2 VMOVUPD	0x40(%RSI,%R15,8),%YMM12

(1419) 0x48dbd9 VMOVUPD	0x60(%RSI,%R15,8),%YMM13

(1419) 0x48dbe0 VSUBPD	%YMM3,%YMM7,%YMM26

(1419) 0x48dbe6 VSUBPD	%YMM4,%YMM8,%YMM11

(1419) 0x48dbea VSUBPD	%YMM4,%YMM9,%YMM20

(1419) 0x48dbf0 VSUBPD	%YMM4,%YMM12,%YMM23

(1419) 0x48dbf6 VSUBPD	%YMM4,%YMM13,%YMM25

(1419) 0x48dbfc VBROADCASTSD	0x48(%RDI),%YMM8

(1419) 0x48dc02 VMULPD	%YMM19,%YMM8,%YMM12

(1419) 0x48dc08 VMULPD	%YMM18,%YMM8,%YMM13

(1419) 0x48dc0e VMULPD	%YMM17,%YMM8,%YMM7

(1419) 0x48dc14 VMULPD	%YMM10,%YMM8,%YMM8

(1419) 0x48dc19 VBROADCASTSD	0x50(%RDI),%YMM9

(1419) 0x48dc1f VFMADD231PD	%YMM26,%YMM9,%YMM8

(1419) 0x48dc25 VFMADD231PD	%YMM24,%YMM9,%YMM7

(1419) 0x48dc2b VFMADD231PD	%YMM22,%YMM9,%YMM13

(1419) 0x48dc31 VBROADCASTSD	0x60(%RDI),%YMM27

(1419) 0x48dc38 VMULPD	%YMM10,%YMM27,%YMM15

(1419) 0x48dc3e VMULPD	%YMM17,%YMM27,%YMM16

(1419) 0x48dc44 VMULPD	%YMM18,%YMM27,%YMM14

(1419) 0x48dc4a VFMADD231PD	%YMM9,%YMM21,%YMM12

(1419) 0x48dc50 VMULPD	%YMM19,%YMM27,%YMM9

(1419) 0x48dc56 VBROADCASTSD	0x68(%RDI),%YMM27

(1419) 0x48dc5d VFMADD231PD	%YMM21,%YMM27,%YMM9

(1419) 0x48dc63 VFMADD231PD	%YMM22,%YMM27,%YMM14

(1419) 0x48dc69 VBROADCASTSD	0x78(%RDI),%YMM28

(1419) 0x48dc70 VFMADD231PD	%YMM24,%YMM27,%YMM16

(1419) 0x48dc76 VMULPD	%YMM19,%YMM28,%YMM19

(1419) 0x48dc7c VMULPD	%YMM18,%YMM28,%YMM18

(1419) 0x48dc82 VMULPD	%YMM17,%YMM28,%YMM17

(1419) 0x48dc88 VMULPD	%YMM10,%YMM28,%YMM10

(1419) 0x48dc8e VBROADCASTSD	0x80(%RDI),%YMM28

(1419) 0x48dc95 VFMADD231PD	%YMM27,%YMM26,%YMM15

(1419) 0x48dc9b VFMADD231PD	%YMM26,%YMM28,%YMM10

(1419) 0x48dca1 VBROADCASTSD	0x58(%RDI),%YMM26

(1419) 0x48dca8 VFMADD231PD	%YMM25,%YMM26,%YMM12

(1419) 0x48dcae VFMADD231PD	%YMM23,%YMM26,%YMM13

(1419) 0x48dcb4 VFMADD231PD	%YMM20,%YMM26,%YMM7

(1419) 0x48dcba VFMADD231PD	%YMM26,%YMM11,%YMM8

(1419) 0x48dcc0 VBROADCASTSD	0x70(%RDI),%YMM26

(1419) 0x48dcc7 VFMADD231PD	%YMM11,%YMM26,%YMM15

(1419) 0x48dccd VFMADD231PD	%YMM20,%YMM26,%YMM16

(1419) 0x48dcd3 VFMADD231PD	%YMM23,%YMM26,%YMM14

(1419) 0x48dcd9 VFMADD231PD	%YMM24,%YMM28,%YMM17

(1419) 0x48dcdf VFMADD231PD	%YMM26,%YMM25,%YMM9

(1419) 0x48dce5 VFMADD231PD	%YMM22,%YMM28,%YMM18

(1419) 0x48dceb VFMADD231PD	%YMM21,%YMM28,%YMM19

(1419) 0x48dcf1 VBROADCASTSD	0x88(%RDI),%YMM21

(1419) 0x48dcf8 VFMADD231PD	%YMM25,%YMM21,%YMM19

(1419) 0x48dcfe VFMADD231PD	%YMM23,%YMM21,%YMM18

(1419) 0x48dd04 VMOVDQA64	%YMM6,%YMM22

(1419) 0x48dd0a VFMADD231PD	%YMM20,%YMM21,%YMM17

(1419) 0x48dd10 VPTERNLOGQ	$-0x8,%YMM5,%YMM8,%YMM22

(1419) 0x48dd17 VADDPD	%YMM22,%YMM8,%YMM20

(1419) 0x48dd1d VMOVDQA64	%YMM6,%YMM22

(1419) 0x48dd23 VPTERNLOGQ	$-0x8,%YMM5,%YMM7,%YMM22

(1419) 0x48dd2a VADDPD	%YMM22,%YMM7,%YMM22

(1419) 0x48dd30 VRNDSCALEPD	$0xb,%YMM20,%YMM20

(1419) 0x48dd37 VRNDSCALEPD	$0xb,%YMM22,%YMM22

(1419) 0x48dd3e VMOVDQA64	%YMM6,%YMM23

(1419) 0x48dd44 VPTERNLOGQ	$-0x8,%YMM5,%YMM13,%YMM23

(1419) 0x48dd4b VADDPD	%YMM23,%YMM13,%YMM23

(1419) 0x48dd51 VMOVDQA64	%YMM6,%YMM24

(1419) 0x48dd57 VRNDSCALEPD	$0xb,%YMM23,%YMM23

(1419) 0x48dd5e VPTERNLOGQ	$-0x8,%YMM5,%YMM12,%YMM24

(1419) 0x48dd65 VADDPD	%YMM24,%YMM12,%YMM24

(1419) 0x48dd6b VRNDSCALEPD	$0xb,%YMM24,%YMM24

(1419) 0x48dd72 VMOVDQA64	%YMM6,%YMM25

(1419) 0x48dd78 VPTERNLOGQ	$-0x8,%YMM5,%YMM9,%YMM25

(1419) 0x48dd7f VADDPD	%YMM25,%YMM9,%YMM25

(1419) 0x48dd85 VRNDSCALEPD	$0xb,%YMM25,%YMM25

(1419) 0x48dd8c VMOVDQA64	%YMM6,%YMM26

(1419) 0x48dd92 VPTERNLOGQ	$-0x8,%YMM5,%YMM14,%YMM26

(1419) 0x48dd99 VADDPD	%YMM26,%YMM14,%YMM26

(1419) 0x48dd9f VRNDSCALEPD	$0xb,%YMM26,%YMM26

(1419) 0x48dda6 VFMADD231PD	%YMM11,%YMM21,%YMM10

(1419) 0x48ddac VMOVDQA	%YMM6,%YMM11

(1419) 0x48ddb0 VPTERNLOGQ	$-0x8,%YMM5,%YMM16,%YMM11

(1419) 0x48ddb7 VADDPD	%YMM11,%YMM16,%YMM11

(1419) 0x48ddbd VRNDSCALEPD	$0xb,%YMM11,%YMM21

(1419) 0x48ddc4 VSUBPD	%YMM24,%YMM12,%YMM12

(1419) 0x48ddca VSUBPD	%YMM23,%YMM13,%YMM11

(1419) 0x48ddd0 VMOVDQA	%YMM6,%YMM13

(1419) 0x48ddd4 VPTERNLOGQ	$-0x8,%YMM5,%YMM15,%YMM13

(1419) 0x48dddb VADDPD	%YMM13,%YMM15,%YMM13

(1419) 0x48dde0 VROUNDPD	$0xb,%YMM13,%YMM13

(1419) 0x48dde6 VSUBPD	%YMM22,%YMM7,%YMM7

(1419) 0x48ddec VSUBPD	%YMM20,%YMM8,%YMM8

(1419) 0x48ddf2 VMOVDQA64	%YMM6,%YMM20

(1419) 0x48ddf8 VPTERNLOGQ	$-0x8,%YMM5,%YMM10,%YMM20

(1419) 0x48ddff VADDPD	%YMM20,%YMM10,%YMM20

(1419) 0x48de05 VRNDSCALEPD	$0xb,%YMM20,%YMM23

(1419) 0x48de0c VSUBPD	%YMM13,%YMM15,%YMM13

(1419) 0x48de11 VSUBPD	%YMM21,%YMM16,%YMM15

(1419) 0x48de17 VMOVDQA64	%YMM6,%YMM16

(1419) 0x48de1d VPTERNLOGQ	$-0x8,%YMM5,%YMM17,%YMM16

(1419) 0x48de24 VADDPD	%YMM16,%YMM17,%YMM16

(1419) 0x48de2a VRNDSCALEPD	$0xb,%YMM16,%YMM24

(1419) 0x48de31 VMOVDQA64	%YMM6,%YMM16

(1419) 0x48de37 VSUBPD	%YMM26,%YMM14,%YMM20

(1419) 0x48de3d VPTERNLOGQ	$-0x8,%YMM5,%YMM18,%YMM16

(1419) 0x48de44 VADDPD	%YMM16,%YMM18,%YMM14

(1419) 0x48de4a VROUNDPD	$0xb,%YMM14,%YMM14

(1419) 0x48de50 VMOVDQA64	%YMM6,%YMM16

(1419) 0x48de56 VPTERNLOGQ	$-0x8,%YMM5,%YMM19,%YMM16

(1419) 0x48de5d VSUBPD	%YMM25,%YMM9,%YMM21

(1419) 0x48de63 VADDPD	%YMM16,%YMM19,%YMM9

(1419) 0x48de69 VROUNDPD	$0xb,%YMM9,%YMM9

(1419) 0x48de6f VSUBPD	%YMM9,%YMM19,%YMM22

(1419) 0x48de75 VBROADCASTSD	(%RDI),%YMM25

(1419) 0x48de7b VSUBPD	%YMM14,%YMM18,%YMM19

(1419) 0x48de81 VMULPD	%YMM8,%YMM25,%YMM9

(1419) 0x48de87 VMULPD	%YMM7,%YMM25,%YMM14

(1419) 0x48de8d VMULPD	%YMM11,%YMM25,%YMM16

(1419) 0x48de93 VMULPD	%YMM12,%YMM25,%YMM18

(1419) 0x48de99 VBROADCASTSD	0x8(%RDI),%YMM25

(1419) 0x48dea0 VSUBPD	%YMM24,%YMM17,%YMM17

(1419) 0x48dea6 VFMADD231PD	%YMM21,%YMM25,%YMM18

(1419) 0x48deac VFMADD231PD	%YMM20,%YMM25,%YMM16

(1419) 0x48deb2 VFMADD231PD	%YMM15,%YMM25,%YMM14

(1419) 0x48deb8 VFMADD231PD	%YMM25,%YMM13,%YMM9

(1419) 0x48debe VBROADCASTSD	0x10(%RDI),%YMM24

(1419) 0x48dec5 VSUBPD	%YMM23,%YMM10,%YMM23

(1419) 0x48decb VFMADD231PD	%YMM24,%YMM23,%YMM9

(1419) 0x48ded1 VFMADD231PD	%YMM24,%YMM17,%YMM14

(1419) 0x48ded7 VFMADD231PD	%YMM24,%YMM19,%YMM16

(1419) 0x48dedd VFMADD231PD	%YMM24,%YMM22,%YMM18

(1419) 0x48dee3 VMOVUPD	%YMM18,0x60(%R8,%R15,8)

(1419) 0x48deeb VMOVUPD	%YMM16,0x40(%R8,%R15,8)

(1419) 0x48def3 VMOVUPD	%YMM14,0x20(%R8,%R15,8)

(1419) 0x48defa VMOVUPD	%YMM9,(%R8,%R15,8)

(1419) 0x48df00 VBROADCASTSD	0x18(%RDI),%YMM24

(1419) 0x48df07 VMULPD	%YMM12,%YMM24,%YMM10

(1419) 0x48df0d VMULPD	%YMM8,%YMM24,%YMM25

(1419) 0x48df13 VMULPD	%YMM7,%YMM24,%YMM26

(1419) 0x48df19 VBROADCASTSD	0x20(%RDI),%YMM27

(1419) 0x48df20 VMULPD	%YMM11,%YMM24,%YMM24

(1419) 0x48df26 VFMADD231PD	%YMM20,%YMM27,%YMM24

(1419) 0x48df2c VFMADD231PD	%YMM15,%YMM27,%YMM26

(1419) 0x48df32 VFMADD231PD	%YMM13,%YMM27,%YMM25

(1419) 0x48df38 VFMADD231PD	%YMM27,%YMM21,%YMM10

(1419) 0x48df3e VBROADCASTSD	0x28(%RDI),%YMM27

(1419) 0x48df45 VFMADD231PD	%YMM22,%YMM27,%YMM10

(1419) 0x48df4b VFMADD231PD	%YMM17,%YMM27,%YMM26

(1419) 0x48df51 VFMADD231PD	%YMM27,%YMM19,%YMM24

(1419) 0x48df57 VMOVUPD	%YMM24,0x40(%RBX,%R15,8)

(1419) 0x48df5f VMOVUPD	%YMM26,0x20(%RBX,%R15,8)

(1419) 0x48df67 VFMADD231PD	%YMM23,%YMM27,%YMM25

(1419) 0x48df6d VMOVUPD	%YMM25,(%RBX,%R15,8)

(1419) 0x48df74 VMOVUPD	%YMM10,0x60(%RBX,%R15,8)

(1419) 0x48df7b VBROADCASTSD	0x30(%RDI),%YMM27

(1419) 0x48df82 VMULPD	%YMM12,%YMM27,%YMM12

(1419) 0x48df88 VMULPD	%YMM8,%YMM27,%YMM8

(1419) 0x48df8e VMULPD	%YMM7,%YMM27,%YMM7

(1419) 0x48df94 VMULPD	%YMM11,%YMM27,%YMM11

(1419) 0x48df9a VBROADCASTSD	0x38(%RDI),%YMM27

(1419) 0x48dfa1 VFMADD231PD	%YMM20,%YMM27,%YMM11

(1419) 0x48dfa7 VFMADD231PD	%YMM15,%YMM27,%YMM7

(1419) 0x48dfad VFMADD231PD	%YMM13,%YMM27,%YMM8

(1419) 0x48dfb3 VFMADD231PD	%YMM21,%YMM27,%YMM12

(1419) 0x48dfb9 VBROADCASTSD	0x40(%RDI),%YMM13

(1419) 0x48dfbf VFMADD231PD	%YMM22,%YMM13,%YMM12

(1419) 0x48dfc5 VFMADD231PD	%YMM23,%YMM13,%YMM8

(1419) 0x48dfcb VFMADD231PD	%YMM17,%YMM13,%YMM7

(1419) 0x48dfd1 VFMADD231PD	%YMM19,%YMM13,%YMM11

(1419) 0x48dfd7 VMULPD	%YMM16,%YMM16,%YMM13

(1419) 0x48dfdd VMULPD	%YMM18,%YMM18,%YMM15

(1419) 0x48dfe3 VMOVUPD	%YMM11,0x40(%R11,%R15,8)

(1419) 0x48dfea VMULPD	%YMM9,%YMM9,%YMM9

(1419) 0x48dfef VMULPD	%YMM14,%YMM14,%YMM14

(1419) 0x48dff4 VFMADD231PD	%YMM26,%YMM26,%YMM14

(1419) 0x48dffa VFMADD231PD	%YMM25,%YMM25,%YMM9

(1419) 0x48e000 VMOVUPD	%YMM7,0x20(%R11,%R15,8)

(1419) 0x48e007 VFMADD231PD	%YMM10,%YMM10,%YMM15

(1419) 0x48e00c VFMADD231PD	%YMM24,%YMM24,%YMM13

(1419) 0x48e012 VFMADD231PD	%YMM11,%YMM11,%YMM13

(1419) 0x48e017 VFMADD231PD	%YMM12,%YMM12,%YMM15

(1419) 0x48e01c VMOVUPD	%YMM8,(%R11,%R15,8)

(1419) 0x48e022 VFMADD231PD	%YMM8,%YMM8,%YMM9

(1419) 0x48e027 VFMADD231PD	%YMM7,%YMM7,%YMM14

(1419) 0x48e02c VSQRTPD	%YMM14,%YMM7

(1419) 0x48e031 VSQRTPD	%YMM9,%YMM8

(1419) 0x48e036 VMOVUPD	%YMM12,0x60(%R11,%R15,8)

(1419) 0x48e03d VSQRTPD	%YMM15,%YMM9

(1419) 0x48e042 VSQRTPD	%YMM13,%YMM10

(1419) 0x48e047 VMOVUPD	%YMM10,0x40(%RCX,%R15,8)

(1419) 0x48e04e VMOVUPD	%YMM9,0x60(%RCX,%R15,8)

(1419) 0x48e055 VMOVUPD	%YMM8,(%RCX,%R15,8)

(1419) 0x48e05b VMOVUPD	%YMM7,0x20(%RCX,%R15,8)

(1419) 0x48e062 ADD	$0x10,%R13D

(1419) 0x48e066 CMP	%R12D,%R13D

(1419) 0x48e069 JBE	48db60

0x48e06f MOV	-0x38(%RBP),%R13

0x48e073 CMP	%R14D,%R13D

0x48e076 JNE	48e103

0x48e07c CMP	%R13D,-0x2c(%RBP)

0x48e080 JNE	48e267

0x48e086 JMP	48e3b4

0x48e08b NOPW	%CS:(%RAX,%RAX,1)

0x48e09a NOPW	%CS:(%RAX,%RAX,1)

0x48e0a9 NOPW	%CS:(%RAX,%RAX,1)

0x48e0b8 NOPL	(%RAX,%RAX,1)

0x48e0c0 XOR	%R14D,%R14D

0x48e0c3 JMP	48e267

0x48e0c8 NOPW	%CS:(%RAX,%RAX,1)

0x48e0d7 NOPW	%CS:(%RAX,%RAX,1)

0x48e0e6 NOPW	%CS:(%RAX,%RAX,1)

0x48e0f5 NOPW	%CS:(%RAX,%RAX,1)

0x48e100 XOR	%R14D,%R14D

0x48e103 LEA	-0x1(%R13),%R15D

0x48e107 VPERMPD	$0x55,%YMM0,%YMM3

0x48e10d VBROADCASTSD	%XMM1,%YMM4

0x48e112 VPBROADCASTQ	0xa8f2d(%RIP),%YMM5

0x48e11b VPBROADCASTQ	0xaf21c(%RIP),%YMM6

0x48e124 NOPW	%CS:(%RAX,%RAX,1)

(1418) 0x48e130 LEA	(%R9,%R14,1),%R12D

(1418) 0x48e134 MOVSXD	%R12D,%R12

(1418) 0x48e137 VMOVUPD	(%RDX,%R12,8),%YMM7

(1418) 0x48e13d VSUBPD	%YMM2,%YMM7,%YMM7

(1418) 0x48e141 VMOVUPD	(%R10,%R12,8),%YMM8

(1418) 0x48e147 VSUBPD	%YMM3,%YMM8,%YMM8

(1418) 0x48e14b VMOVUPD	(%RSI,%R12,8),%YMM9

(1418) 0x48e151 VSUBPD	%YMM4,%YMM9,%YMM9

(1418) 0x48e155 VMULPD	0x48(%RDI){1to4},%YMM7,%YMM10

(1418) 0x48e15c VFMADD231PD	0x50(%RDI){1to4},%YMM8,%YMM10

(1418) 0x48e163 VFMADD231PD	0x58(%RDI){1to4},%YMM9,%YMM10

(1418) 0x48e16a VMULPD	0x60(%RDI){1to4},%YMM7,%YMM11

(1418) 0x48e171 VFMADD231PD	0x68(%RDI){1to4},%YMM8,%YMM11

(1418) 0x48e178 VFMADD231PD	0x70(%RDI){1to4},%YMM9,%YMM11

(1418) 0x48e17f VMULPD	0x78(%RDI){1to4},%YMM7,%YMM7

(1418) 0x48e186 VFMADD231PD	0x80(%RDI){1to4},%YMM8,%YMM7

(1418) 0x48e18d VFMADD231PD	0x88(%RDI){1to4},%YMM9,%YMM7

(1418) 0x48e194 VMOVDQA	%YMM6,%YMM8

(1418) 0x48e198 VPTERNLOGQ	$-0x8,%YMM5,%YMM10,%YMM8

(1418) 0x48e19f VADDPD	%YMM8,%YMM10,%YMM8

(1418) 0x48e1a4 VROUNDPD	$0xb,%YMM8,%YMM8

(1418) 0x48e1aa VMOVDQA	%YMM6,%YMM9

(1418) 0x48e1ae VSUBPD	%YMM8,%YMM10,%YMM8

(1418) 0x48e1b3 VPTERNLOGQ	$-0x8,%YMM5,%YMM11,%YMM9

(1418) 0x48e1ba VADDPD	%YMM9,%YMM11,%YMM9

(1418) 0x48e1bf VROUNDPD	$0xb,%YMM9,%YMM9

(1418) 0x48e1c5 VMOVDQA	%YMM6,%YMM10

(1418) 0x48e1c9 VPTERNLOGQ	$-0x8,%YMM5,%YMM7,%YMM10

(1418) 0x48e1d0 VSUBPD	%YMM9,%YMM11,%YMM9

(1418) 0x48e1d5 VADDPD	%YMM7,%YMM10,%YMM10

(1418) 0x48e1d9 VROUNDPD	$0xb,%YMM10,%YMM10

(1418) 0x48e1df VMULPD	(%RDI){1to4},%YMM8,%YMM11

(1418) 0x48e1e5 VSUBPD	%YMM10,%YMM7,%YMM7

(1418) 0x48e1ea VFMADD231PD	0x8(%RDI){1to4},%YMM9,%YMM11

(1418) 0x48e1f1 VFMADD231PD	0x10(%RDI){1to4},%YMM7,%YMM11

(1418) 0x48e1f8 VMOVUPD	%YMM11,(%R8,%R12,8)

(1418) 0x48e1fe VMULPD	0x18(%RDI){1to4},%YMM8,%YMM10

(1418) 0x48e205 VFMADD231PD	0x20(%RDI){1to4},%YMM9,%YMM10

(1418) 0x48e20c VFMADD231PD	0x28(%RDI){1to4},%YMM7,%YMM10

(1418) 0x48e213 VMOVUPD	%YMM10,(%RBX,%R12,8)

(1418) 0x48e219 VMULPD	0x30(%RDI){1to4},%YMM8,%YMM8

(1418) 0x48e220 VFMADD231PD	0x38(%RDI){1to4},%YMM9,%YMM8

(1418) 0x48e227 VFMADD231PD	0x40(%RDI){1to4},%YMM7,%YMM8

(1418) 0x48e22e VMULPD	%YMM11,%YMM11,%YMM7

(1418) 0x48e233 VFMADD231PD	%YMM10,%YMM10,%YMM7

(1418) 0x48e238 VMOVUPD	%YMM8,(%R11,%R12,8)

(1418) 0x48e23e VFMADD231PD	%YMM8,%YMM8,%YMM7

(1418) 0x48e243 VSQRTPD	%YMM7,%YMM7

(1418) 0x48e247 VMOVUPD	%YMM7,(%RCX,%R12,8)

(1418) 0x48e24d ADD	$0x4,%R14D

(1418) 0x48e251 CMP	%R15D,%R14D

(1418) 0x48e254 JBE	48e130

0x48e25a MOV	%R13D,%R14D

0x48e25d CMP	%R13D,-0x2c(%RBP)

0x48e261 JE	48e3b4

0x48e267 ADD	%R9D,%R14D

0x48e26a VMOVQ	0xaf0ce(%RIP),%XMM2

0x48e272 VPBROADCASTQ	0xa9f8d(%RIP),%XMM3

0x48e27b VPBROADCASTQ	0xaf0bc(%RIP),%XMM4

0x48e284 VPBROADCASTQ	0xa8dbb(%RIP),%XMM5

0x48e28d NOPL	(%RAX)

(1417) 0x48e290 MOVSXD	%R14D,%R14

(1417) 0x48e293 VMOVSD	(%RSI,%R14,8),%XMM6

(1417) 0x48e299 VSUBSD	%XMM1,%XMM6,%XMM6

(1417) 0x48e29d VMOVUPD	0x60(%RDI),%XMM7

(1417) 0x48e2a2 VMOVUPD	0x70(%RDI),%XMM8

(1417) 0x48e2a7 VMOVSD	(%RDX,%R14,8),%XMM9

(1417) 0x48e2ad VMOVHPD	(%R10,%R14,8),%XMM9,%XMM9

(1417) 0x48e2b3 VSUBPD	%XMM0,%XMM9,%XMM9

(1417) 0x48e2b7 VMULPD	0x48(%RDI),%XMM9,%XMM10

(1417) 0x48e2bc VSHUFPD	$0x1,%XMM10,%XMM10,%XMM11

(1417) 0x48e2c2 VADDSD	%XMM10,%XMM11,%XMM10

(1417) 0x48e2c7 VFMADD231SD	0x58(%RDI),%XMM6,%XMM10

(1417) 0x48e2cd VMOVSD	0x68(%RDI),%XMM11

(1417) 0x48e2d2 VPUNPCKLQDQ	0x78(%RDI),%XMM11,%XMM11

(1417) 0x48e2d7 VSHUFPD	$0x1,%XMM9,%XMM9,%XMM12

(1417) 0x48e2dd VMULPD	%XMM12,%XMM11,%XMM11

(1417) 0x48e2e2 VMOVHPD	0x80(%RDI),%XMM7,%XMM7

(1417) 0x48e2ea VMOVHPD	0x88(%RDI),%XMM8,%XMM8

(1417) 0x48e2f2 VFMADD213PD	%XMM11,%XMM9,%XMM7

(1417) 0x48e2f7 VMOVDDUP	%XMM6,%XMM6

(1417) 0x48e2fb VMOVAPD	%XMM10,%XMM9

(1417) 0x48e300 VPTERNLOGQ	$-0x28,%XMM3,%XMM2,%XMM9

(1417) 0x48e307 VADDSD	%XMM9,%XMM10,%XMM9

(1417) 0x48e30c VROUNDSD	$0xb,%XMM9,%XMM9,%XMM9

(1417) 0x48e312 VFMADD213PD	%XMM7,%XMM8,%XMM6

(1417) 0x48e317 VSUBSD	%XMM9,%XMM10,%XMM7

(1417) 0x48e31c VMOVDQA	%XMM4,%XMM8

(1417) 0x48e320 VPTERNLOGQ	$-0x8,%XMM5,%XMM6,%XMM8

(1417) 0x48e327 VADDPD	%XMM6,%XMM8,%XMM8

(1417) 0x48e32b VROUNDPD	$0xb,%XMM8,%XMM8

(1417) 0x48e331 VSUBPD	%XMM8,%XMM6,%XMM6

(1417) 0x48e336 VMULSD	(%RDI),%XMM7,%XMM8

(1417) 0x48e33a VFMADD231SD	0x8(%RDI),%XMM6,%XMM8

(1417) 0x48e340 VSHUFPD	$0x1,%XMM6,%XMM6,%XMM9

(1417) 0x48e345 VFMADD231SD	0x10(%RDI),%XMM9,%XMM8

(1417) 0x48e34b VMOVSD	%XMM8,(%R8,%R14,8)

(1417) 0x48e351 VMULSD	0x18(%RDI),%XMM7,%XMM10

(1417) 0x48e356 VFMADD231SD	0x20(%RDI),%XMM6,%XMM10

(1417) 0x48e35c VFMADD231SD	0x28(%RDI),%XMM9,%XMM10

(1417) 0x48e362 VMOVSD	%XMM10,(%RBX,%R14,8)

(1417) 0x48e368 VMOVUPD	0x38(%RDI),%XMM9

(1417) 0x48e36d VMOVHPD	0x40(%RDI),%XMM9,%XMM9

(1417) 0x48e372 VMULPD	%XMM6,%XMM9,%XMM6

(1417) 0x48e376 VMOVAPD	%XMM6,%XMM9

(1417) 0x48e37a VFMADD231SD	0x30(%RDI),%XMM7,%XMM9

(1417) 0x48e380 VSHUFPD	$0x1,%XMM6,%XMM6,%XMM6

(1417) 0x48e385 VADDSD	%XMM6,%XMM9,%XMM6

(1417) 0x48e389 VMOVSD	%XMM6,(%R11,%R14,8)

(1417) 0x48e38f VMULSD	%XMM8,%XMM8,%XMM7

(1417) 0x48e394 VFMADD231SD	%XMM10,%XMM10,%XMM7

(1417) 0x48e399 VFMADD231SD	%XMM6,%XMM6,%XMM7

(1417) 0x48e39e VSQRTSD	%XMM7,%XMM7,%XMM6

(1417) 0x48e3a2 VMOVSD	%XMM6,(%RCX,%R14,8)

(1417) 0x48e3a8 INC	%R14D

(1417) 0x48e3ab CMP	%R14D,%EAX

(1417) 0x48e3ae JNE	48e290

0x48e3b4 POP	%RBX

0x48e3b5 POP	%R12

0x48e3b7 POP	%R13

0x48e3b9 POP	%R14

0x48e3bb POP	%R15

0x48e3bd POP	%RBP

0x48e3be VZEROUPPER

0x48e3c1 RET

0x48e3c2 NOPW	%CS:(%RAX,%RAX,1)

0x48e3cc NOPW	%CS:(%RAX,%RAX,1)

0x48e3d6 NOPW	%CS:(%RAX,%RAX,1)

0x48e3e0 NOPW	%CS:(%RAX,%RAX,1)

0x48e3ea NOPW	%CS:(%RAX,%RAX,1)

0x48e3f4 NOPW	%CS:(%RAX,%RAX,1)

0x48e3fe XCHG	%AX,%AX

Coverage (%)	Name	Source Location	Module
►39.97+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableAAOMPTarget.h:283	exec
○	qmcplusplus::ParticleSet::comp[...]	ParticleSet.cpp:343	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►37.20+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableAAOMPTarget.h:275	exec
○	qmcplusplus::ParticleSet::comp[...]	ParticleSet.cpp:343	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►9.89+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableABOMPTarget.h:366	exec
○	qmcplusplus::ParticleSet::comp[...]	ParticleSet.cpp:343	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►9.80+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableAAOMPTarget.h:185	exec
○	qmcplusplus::ParticleSet::upda[...]	ParticleSet.cpp:242	exec
○	main.extracted.112	miniqmc.cpp:396	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►3.10+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableABOMPTarget.h:361	exec
○	qmcplusplus::ParticleSet::comp[...]	ParticleSet.cpp:343	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run icx_4

Source file and lines	ParticleBConds3DSoa.h:221-257
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:271-273
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:221-224,234-257

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.33 to 5.00 cycles (2.87x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:257

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 140 bytes. The binary function is storing 12 bytes.

General properties

nb instructions	85
nb uops	86
loop length	483
used x86 registers	14
used mmx registers	0
used xmm registers	6
used ymm registers	6
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.33 cycles
front end	14.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.10	5.00	8.33	8.33	4.00	5.00	4.90	4.00	4.00	4.00	5.00	8.33
cycles	5.10	5.00	8.33	8.33	4.00	5.00	4.90	4.00	4.00	4.00	5.00	8.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.33
Dispatch	8.33
Overall L1	14.33

Vectorization ratios

INT

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	42%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

INT+FP

all	19%
load	8%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Vector efficiency ratios

INT

all	11%
load	11%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	25%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

INT+FP

all	16%
load	12%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.33 cycles. At this rate:

5% of peak load performance is reached (9.77 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.84 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 14.33 to 8.33 cycles (1.72x speedup).

ASM code

In the binary file, the address of the function is: 48dac0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV 0x10(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R9D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JLE 48e3b4 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x8f4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPD (%RSI),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0x10(%RSI),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%RDX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RDX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%RSI,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x4,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x8(%R8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%R8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R8,%R11,8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x4,%R11	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %R8,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R14D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 48e0c0 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x600>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14D,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VBROADCASTSD %XMM0,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
AND $-0x10,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 48e100 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x640>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R13,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA -0x1(%R14),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPERMPD $0x55,%YMM0,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VBROADCASTSD %XMM1,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ 0xa94fe(%RIP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xaf7ed(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x38(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R14D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 48e103 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x643>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R13D,-0x2c(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JNE 48e267 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x7a7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 48e3b4 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x8f4>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 48e267 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x7a7>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x1(%R13),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPERMPD $0x55,%YMM0,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VBROADCASTSD %XMM1,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPBROADCASTQ 0xa8f2d(%RIP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xaf21c(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R13D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13D,-0x2c(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 48e3b4 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x8f4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %R9D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVQ 0xaf0ce(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPBROADCASTQ 0xa9f8d(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xaf0bc(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xa8dbb(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run icx_4

Source file and lines	ParticleBConds3DSoa.h:221-257
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:271-273
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:221-224,234-257

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.33 to 5.00 cycles (2.87x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:257

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 140 bytes. The binary function is storing 12 bytes.

General properties

nb instructions	85
nb uops	86
loop length	483
used x86 registers	14
used mmx registers	0
used xmm registers	6
used ymm registers	6
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.33 cycles
front end	14.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.10	5.00	8.33	8.33	4.00	5.00	4.90	4.00	4.00	4.00	5.00	8.33
cycles	5.10	5.00	8.33	8.33	4.00	5.00	4.90	4.00	4.00	4.00	5.00	8.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.33
Dispatch	8.33
Overall L1	14.33

Vectorization ratios

INT

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	42%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

INT+FP

all	19%
load	8%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Vector efficiency ratios

INT

all	11%
load	11%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	25%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

INT+FP

all	16%
load	12%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.33 cycles. At this rate:

5% of peak load performance is reached (9.77 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.84 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 48dac0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV 0x10(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R9D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JLE 48e3b4 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x8f4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPD (%RSI),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0x10(%RSI),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%RDX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RDX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%RSI,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x4,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x8(%R8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%R8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R8,%R11,8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x4,%R11	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %R8,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R14D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 48e0c0 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x600>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14D,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VBROADCASTSD %XMM0,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
AND $-0x10,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 48e100 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x640>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R13,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA -0x1(%R14),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPERMPD $0x55,%YMM0,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VBROADCASTSD %XMM1,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ 0xa94fe(%RIP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xaf7ed(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x38(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R14D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 48e103 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x643>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R13D,-0x2c(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JNE 48e267 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x7a7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 48e3b4 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x8f4>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 48e267 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x7a7>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x1(%R13),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPERMPD $0x55,%YMM0,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VBROADCASTSD %XMM1,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPBROADCASTQ 0xa8f2d(%RIP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xaf21c(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R13D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13D,-0x2c(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 48e3b4 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x8f4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %R9D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVQ 0xaf0ce(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPBROADCASTQ 0xa9f8d(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xaf0bc(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xa8dbb(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer–	1.48	1.27
○Loop 1419 - ParticleBConds3DSoa.h:235-256 - exec	1.48	1.25
○Loop 1418 - ParticleBConds3DSoa.h:235-256 - exec	0.00	0.01
○Loop 1417 - ParticleBConds3DSoa.h:235-255 - exec	0.00	0.00

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512-bits vectorization

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Matching between your function (in the source code) and the binary function

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ASM code

Code clean check

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Vectorization

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Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code