OV - exec - Function miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::evaluateGL(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib<qmcplusplus::TinyVector<double, 3u>, std::allocator<qmcplusplus::TinyVector<double, 3u> > >&, qmcplusplus::ParticleAttrib<double, std::allocator<double> >&, bool)

	Function: miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::evalua ...	Module: exec	Source: DiracDeterminantRef.cpp:156-181 [...]	Coverage (incl. loops): 0.86% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 82 - 155

--------------------------------------------------------------------------------

82:   for (int i = 0; i < n; i++)

83:     res += a[i] * b[i];

[...]

155:   for (int i = 0; i < n; i++)

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 63 - 94

--------------------------------------------------------------------------------

63:     return (a * b);

[...]

94:     (const_cast<T1&>(a) += b);

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorOps.h: 111 - 131

--------------------------------------------------------------------------------

111:       ret[d] = op(lhs, rhs[d]);

[...]

131:       res += lhs[d] * rhs[d];

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp: 156 - 181

--------------------------------------------------------------------------------

156: {

157:   if (UpdateMode == ORB_PBYP_RATIO)

158:   { //need to compute dpsiM and d2psiM. Do not touch psiM!

159:     SPOVGLTimer->start();

160:     Phi->evaluate_notranspose(P, FirstIndex, LastIndex, psiM_temp, dpsiM, d2psiM);

161:     SPOVGLTimer->stop();

162:   }

163:

164:   if (NumPtcls == 1)

165:   {

166:     ValueType y = psiM(0, 0);

167:     GradType rv = y * dpsiM(0, 0);

168:     G[FirstIndex] += rv;

169:     L[FirstIndex] += y * d2psiM(0, 0) - dot(rv, rv);

170:   }

171:   else

172:   {

173:     for (size_t i = 0, iat = FirstIndex; i < NumPtcls; ++i, ++iat)

174:     {

175:       mValueType dot_temp = simd::dot(psiM[i], d2psiM[i], NumOrbitals);

176:       mGradType rv        = simd::dot(psiM[i], dpsiM[i], NumOrbitals);

177:       G[iat] += rv;

178:       L[iat] += dot_temp - dot(rv, rv);

179:     }

180:   }

181: }

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h: 217 - 217

--------------------------------------------------------------------------------

217:   inline Type_t* operator[](size_type i) { return X.data() + i * D2; }

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 62 - 169

--------------------------------------------------------------------------------

62:       X[d] = T(0);

[...]

169:   inline Type_t& operator[](unsigned int i) { return X[i]; }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/unique_ptr.h: 173 - 173

--------------------------------------------------------------------------------

173:       pointer    _M_ptr() const { return std::get<0>(_M_t); }

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 248

--------------------------------------------------------------------------------

223:     return X[i];

[...]

248:   inline pointer data() { return X; }

0x45e080 PUSH	%RBP

0x45e081 MOV	%RSP,%RBP

0x45e084 PUSH	%R15

0x45e086 PUSH	%R14

0x45e088 PUSH	%R13

0x45e08a PUSH	%R12

0x45e08c PUSH	%RBX

0x45e08d SUB	$0x38,%RSP

0x45e091 MOV	%RDI,%RBX

0x45e094 CMPL	$0,0xc(%RDI)

0x45e098 JNE	45e0f7

0x45e09a MOV	0x468(%RBX),%RDI

0x45e0a1 MOV	%RCX,%R15

0x45e0a4 MOV	%RDX,%R12

0x45e0a7 MOV	%RSI,%R14

0x45e0aa CALL	4b6140 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>

0x45e0af MOV	0x470(%RBX),%RDI

0x45e0b6 MOV	0x478(%RBX),%EDX

0x45e0bc MOV	0x47c(%RBX),%ECX

0x45e0c2 LEA	0x90(%RBX),%R8

0x45e0c9 LEA	0x110(%RBX),%R9

0x45e0d0 LEA	0x150(%RBX),%RAX

0x45e0d7 MOV	(%RDI),%R10

0x45e0da MOV	%RAX,(%RSP)

0x45e0de MOV	%R14,%RSI

0x45e0e1 CALLQ	0x28(%R10)

0x45e0e5 MOV	0x468(%RBX),%RDI

0x45e0ec CALL	4b63c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>

0x45e0f1 MOV	%R12,%RDX

0x45e0f4 MOV	%R15,%RCX

0x45e0f7 MOVSXD	0x484(%RBX),%RAX

0x45e0fe TEST	%RAX,%RAX

0x45e101 JE	45e198

0x45e107 CMP	$0x1,%EAX

0x45e10a JNE	45e1c0

0x45e110 MOV	0x100(%RBX),%RAX

0x45e117 VMOVDDUP	(%RAX),%XMM0

0x45e11b MOV	0x140(%RBX),%RAX

0x45e122 MOVQ	$0,-0x30(%RBP)

0x45e12a VMULPD	(%RAX),%XMM0,%XMM1

0x45e12e VMOVUPD	%XMM1,-0x40(%RBP)

0x45e133 VMULSD	0x10(%RAX),%XMM0,%XMM2

0x45e138 VMOVSD	%XMM2,-0x30(%RBP)

0x45e13d MOVSXD	0x478(%RBX),%RAX

0x45e144 MOV	0x18(%RDX),%RDX

0x45e148 LEA	(%RAX,%RAX,2),%RSI

0x45e14c VADDPD	(%RDX,%RSI,8),%XMM1,%XMM2

0x45e151 VMOVUPD	%XMM2,(%RDX,%RSI,8)

0x45e156 VMOVSD	0x10(%RDX,%RSI,8),%XMM2

0x45e15c VADDSD	-0x30(%RBP),%XMM2,%XMM2

0x45e161 VMOVSD	%XMM2,0x10(%RDX,%RSI,8)

0x45e167 MOV	0x180(%RBX),%RDX

0x45e16e VMOVUPD	-0x38(%RBP),%XMM2

0x45e173 VMULPD	%XMM2,%XMM2,%XMM2

0x45e177 VSHUFPD	$0x1,%XMM2,%XMM2,%XMM3

0x45e17c VADDSD	%XMM3,%XMM2,%XMM2

0x45e180 VFMADD231SD	%XMM1,%XMM1,%XMM2

0x45e185 VFMSUB231SD	(%RDX),%XMM0,%XMM2

0x45e18a MOV	0x18(%RCX),%RCX

0x45e18e VADDSD	(%RCX,%RAX,8),%XMM2,%XMM0

0x45e193 VMOVSD	%XMM0,(%RCX,%RAX,8)

0x45e198 ADD	$0x38,%RSP

0x45e19c POP	%RBX

0x45e19d POP	%R12

0x45e19f POP	%R13

0x45e1a1 POP	%R14

0x45e1a3 POP	%R15

0x45e1a5 POP	%RBP

0x45e1a6 VZEROUPPER

0x45e1a9 RET

0x45e1aa NOPW	%CS:(%RAX,%RAX,1)

0x45e1b9 NOPL	(%RAX)

0x45e1c0 MOVSXD	0x478(%RBX),%RSI

0x45e1c7 MOV	%RSI,-0x58(%RBP)

0x45e1cb MOV	0xd8(%RBX),%R14

0x45e1d2 MOV	0x100(%RBX),%R8

0x45e1d9 MOV	0x180(%RBX),%R9

0x45e1e0 MOV	0x158(%RBX),%R15

0x45e1e7 MOV	0x480(%RBX),%R11D

0x45e1ee MOV	0x140(%RBX),%RDI

0x45e1f5 MOV	0x118(%RBX),%RSI

0x45e1fc MOV	0x18(%RDX),%RDX

0x45e200 MOV	0x18(%RCX),%RCX

0x45e204 DEC	%RAX

0x45e207 MOV	%R11D,%R10D

0x45e20a SHR	$0x2,%R10D

0x45e20e MOV	%R11D,%EBX

0x45e211 AND	$0x7ffffffc,%EBX

0x45e217 SAL	$0x3,%R14

0x45e21b MOV	%R14,-0x50(%RBP)

0x45e21f SAL	$0x3,%R15

0x45e223 MOV	%R15,-0x48(%RBP)

0x45e227 SAL	$0x3,%RSI

0x45e22b LEA	(%RSI,%RSI,2),%R15

0x45e22f MOV	%R10,%R12

0x45e232 SAL	$0x5,%R12

0x45e236 AND	$0x1fffffff,%R10D

0x45e23d LEA	(%R10,%R10,2),%RSI

0x45e241 SAL	$0x5,%RSI

0x45e245 LEA	0x10(%RSI,%RDI,1),%R13

0x45e24a ADD	$0x58,%RDI

0x45e24e VXORPD	%XMM0,%XMM0,%XMM0

0x45e252 XOR	%ESI,%ESI

0x45e254 JMP	45e2fb

0x45e259 NOPW	%CS:(%RAX,%RAX,1)

0x45e268 NOPW	%CS:(%RAX,%RAX,1)

0x45e277 NOPW	(%RAX,%RAX,1)

(1044) 0x45e280 VMOVUPD	%XMM2,-0x40(%RBP)

(1044) 0x45e285 VMOVSD	%XMM3,-0x30(%RBP)

(1044) 0x45e28a MOV	-0x58(%RBP),%R10

(1044) 0x45e28e ADD	%RSI,%R10

(1044) 0x45e291 LEA	(%R10,%R10,2),%R14

(1044) 0x45e295 VMOVUPD	-0x40(%RBP),%XMM2

(1044) 0x45e29a VADDPD	(%RDX,%R14,8),%XMM2,%XMM3

(1044) 0x45e2a0 VMOVUPD	%XMM3,(%RDX,%R14,8)

(1044) 0x45e2a6 VMOVSD	0x10(%RDX,%R14,8),%XMM3

(1044) 0x45e2ad VADDSD	-0x30(%RBP),%XMM3,%XMM3

(1044) 0x45e2b2 VMOVSD	%XMM3,0x10(%RDX,%R14,8)

(1044) 0x45e2b9 VMOVUPD	-0x38(%RBP),%XMM3

(1044) 0x45e2be VMULPD	%XMM3,%XMM3,%XMM3

(1044) 0x45e2c2 VSHUFPD	$0x1,%XMM3,%XMM3,%XMM4

(1044) 0x45e2c7 VADDSD	%XMM4,%XMM3,%XMM3

(1044) 0x45e2cb VFNMSUB231SD	%XMM2,%XMM2,%XMM3

(1044) 0x45e2d0 VADDSD	%XMM3,%XMM1,%XMM1

(1044) 0x45e2d4 VADDSD	(%RCX,%R10,8),%XMM1,%XMM1

(1044) 0x45e2da VMOVSD	%XMM1,(%RCX,%R10,8)

(1044) 0x45e2e0 ADD	-0x50(%RBP),%R8

(1044) 0x45e2e4 ADD	-0x48(%RBP),%R9

(1044) 0x45e2e8 ADD	%R15,%RDI

(1044) 0x45e2eb ADD	%R15,%R13

(1044) 0x45e2ee CMP	%RAX,%RSI

(1044) 0x45e2f1 LEA	0x1(%RSI),%RSI

(1044) 0x45e2f5 JE	45e198

(1044) 0x45e2fb TEST	%R11D,%R11D

(1044) 0x45e2fe JLE	45e380

(1044) 0x45e304 TEST	%RBX,%RBX

(1044) 0x45e307 JE	45e3c0

(1044) 0x45e30d VXORPD	%XMM1,%XMM1,%XMM1

(1044) 0x45e311 XOR	%R10D,%R10D

(1044) 0x45e314 NOPW	%CS:(%RAX,%RAX,1)

  (1048) 0x45e320 VMOVUPD	(%R9,%R10,8),%YMM2

  (1048) 0x45e326 VFMADD231PD	(%R8,%R10,8),%YMM2,%YMM1

  (1048) 0x45e32c ADD	$0x4,%R10

  (1048) 0x45e330 CMP	%RBX,%R10

  (1048) 0x45e333 JB	45e320

(1044) 0x45e335 VEXTRACTF128	$0x1,%YMM1,%XMM2

(1044) 0x45e33b VADDPD	%XMM2,%XMM1,%XMM1

(1044) 0x45e33f VSHUFPD	$0x1,%XMM1,%XMM1,%XMM2

(1044) 0x45e344 VADDSD	%XMM2,%XMM1,%XMM1

(1044) 0x45e348 MOV	%RBX,%R10

(1044) 0x45e34b CMP	%R11D,%EBX

(1044) 0x45e34e JNE	45e3d0

(1044) 0x45e354 JMP	45e3e4

0x45e359 NOPW	%CS:(%RAX,%RAX,1)

0x45e368 NOPW	%CS:(%RAX,%RAX,1)

0x45e377 NOPW	(%RAX,%RAX,1)

(1044) 0x45e380 VXORPD	%XMM1,%XMM1,%XMM1

(1044) 0x45e384 JMP	45e3e4

0x45e386 NOPW	%CS:(%RAX,%RAX,1)

0x45e395 NOPW	%CS:(%RAX,%RAX,1)

0x45e3a4 NOPW	%CS:(%RAX,%RAX,1)

0x45e3b3 NOPW	%CS:(%RAX,%RAX,1)

(1044) 0x45e3c0 VXORPD	%XMM1,%XMM1,%XMM1

(1044) 0x45e3c4 XOR	%R10D,%R10D

(1044) 0x45e3c7 NOPW	(%RAX,%RAX,1)

  (1047) 0x45e3d0 VMOVSD	(%R9,%R10,8),%XMM2

  (1047) 0x45e3d6 VFMADD231SD	(%R8,%R10,8),%XMM2,%XMM1

  (1047) 0x45e3dc INC	%R10

  (1047) 0x45e3df CMP	%R10,%R11

  (1047) 0x45e3e2 JNE	45e3d0

(1044) 0x45e3e4 VMOVUPD	%XMM0,-0x40(%RBP)

(1044) 0x45e3e9 MOVQ	$0,-0x30(%RBP)

(1044) 0x45e3f1 TEST	%R11D,%R11D

(1044) 0x45e3f4 JLE	45e28a

(1044) 0x45e3fa VXORPD	%XMM2,%XMM2,%XMM2

(1044) 0x45e3fe VXORPD	%XMM3,%XMM3,%XMM3

(1044) 0x45e402 CMP	$0x4,%R11D

(1044) 0x45e406 JB	45e467

(1044) 0x45e408 MOV	%RDI,%R14

(1044) 0x45e40b XOR	%R10D,%R10D

(1044) 0x45e40e XCHG	%AX,%AX

  (1046) 0x45e410 VMOVDDUP	(%R8,%R10,1),%XMM4

  (1046) 0x45e416 VFMADD231SD	-0x48(%R14),%XMM4,%XMM3

  (1046) 0x45e41c VMOVDDUP	0x8(%R8,%R10,1),%XMM5

  (1046) 0x45e423 VFMADD231SD	-0x30(%R14),%XMM5,%XMM3

  (1046) 0x45e429 VMOVDDUP	0x10(%R8,%R10,1),%XMM6

  (1046) 0x45e430 VFMADD231SD	-0x18(%R14),%XMM6,%XMM3

  (1046) 0x45e436 VFMADD231PD	-0x58(%R14),%XMM4,%XMM2

  (1046) 0x45e43c VFMADD231PD	-0x40(%R14),%XMM5,%XMM2

  (1046) 0x45e442 VFMADD231PD	-0x28(%R14),%XMM6,%XMM2

  (1046) 0x45e448 VMOVDDUP	0x18(%R8,%R10,1),%XMM4

  (1046) 0x45e44f VFMADD231PD	-0x10(%R14),%XMM4,%XMM2

  (1046) 0x45e455 VFMADD231SD	(%R14),%XMM4,%XMM3

  (1046) 0x45e45a ADD	$0x20,%R10

  (1046) 0x45e45e ADD	$0x60,%R14

  (1046) 0x45e462 CMP	%R10,%R12

  (1046) 0x45e465 JNE	45e410

(1044) 0x45e467 CMP	%R11D,%EBX

(1044) 0x45e46a JE	45e280

(1044) 0x45e470 MOV	%R13,%R10

(1044) 0x45e473 MOV	%RBX,%R14

(1044) 0x45e476 NOPW	%CS:(%RAX,%RAX,1)

  (1045) 0x45e480 VMOVDDUP	(%R8,%R14,8),%XMM4

  (1045) 0x45e486 VFMADD231PD	-0x10(%R10),%XMM4,%XMM2

  (1045) 0x45e48c VFMADD231SD	(%R10),%XMM4,%XMM3

  (1045) 0x45e491 INC	%R14

  (1045) 0x45e494 ADD	$0x18,%R10

  (1045) 0x45e498 CMP	%R14,%R11

  (1045) 0x45e49b JNE	45e480

(1044) 0x45e49d JMP	45e280

0x45e4a2 NOPW	%CS:(%RAX,%RAX,1)

0x45e4ac NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►50.89+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:249	exec
○	main.extracted.107	miniqmc.cpp:467	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►49.11+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:249	exec
○	main.extracted.107	miniqmc.cpp:467	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_4

Source file and lines	DiracDeterminantRef.cpp:156-181
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83,155
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorOps.h:111,131
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:156-181
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:217
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62,169
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/unique_ptr.h:173
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,248

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.50 to 5.67 cycles (3.62x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 20.50 to 1.80 cycles (11.39x speedup).

Details

22% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

20% of SSE/AVX loads are used in vector version.
20% of SSE/AVX stores are used in vector version.
25% of SSE/AVX addition or subtraction instructions are used in vector version.
66% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
23% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 2 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

qmcplusplus::TimerType
::start(): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:159
qmcplusplus::TimerType
::stop(): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:161
unknown: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:160

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:181

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 14 FP arithmetical operations:

7: addition or subtraction (2 inside FMA instructions)
7: multiply (2 inside FMA instructions)

The binary function is loading 268 bytes (33 double precision FP elements). The binary function is storing 96 bytes (12 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	116
nb uops	121
loop length	623
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	7
ADD-SUB / MUL ratio	1.33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.50 cycles
front end	20.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.00	4.90	13.67	13.67	9.50	4.80	6.50	9.50	9.50	9.50	4.80	13.67
cycles	7.00	4.90	13.67	13.67	9.50	4.80	6.50	9.50	9.50	9.50	4.80	13.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	20.50
Dispatch	13.67
Overall L1	20.50

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	42%
load	33%
store	40%
mul	66%
add-sub	25%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	22%
load	20%
store	20%
mul	66%
add-sub	25%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Vector efficiency ratios

INT

all	11%
load	10%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	17%
load	16%
store	17%
mul	20%
add-sub	15%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	14%
load	14%
store	14%
mul	20%
add-sub	15%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.50 cycles. At this rate:

6% of peak load performance is reached (13.07 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.68 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 20.50 to 13.67 cycles (1.50x speedup).

ASM code

In the binary file, the address of the function is: 45e080

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMPL $0,0xc(%RDI)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JNE 45e0f7 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x77>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x468(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 4b6140 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x470(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x478(%RBX),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x47c(%RBX),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x90(%RBX),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x110(%RBX),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x150(%RBX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDI),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALLQ 0x28(%R10)	3	0.70	0.20	0.33	0.33	0.50	0.20	0.70	0.50	0.50	0.50	0.20	0.33	0	2.27	N/A
MOV 0x468(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 4b63c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD 0x484(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 45e198 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x118>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 45e1c0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x140>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x100(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVDDUP (%RAX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x140(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVQ $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMULPD (%RAX),%XMM0,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VMOVUPD %XMM1,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMULSD 0x10(%RAX),%XMM0,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD 0x478(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RDX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RAX,%RAX,2),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VADDPD (%RDX,%RSI,8),%XMM1,%XMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (25.0%)
VMOVUPD %XMM2,(%RDX,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD 0x10(%RDX,%RSI,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD -0x30(%RBP),%XMM2,%XMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM2,0x10(%RDX,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x180(%RBX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD -0x38(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMULPD %XMM2,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM2,%XMM2,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM3,%XMM2,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD231SD %XMM1,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMSUB231SD (%RDX),%XMM0,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV 0x18(%RCX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VADDSD (%RCX,%RAX,8),%XMM2,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVSXD 0x478(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd8(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x100(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x180(%RBX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x158(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x480(%RBX),%R11D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x140(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x118(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RDX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RCX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DEC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x2,%R10D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %R11D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7ffffffc,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SAL $0x3,%R14	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %R14,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SAL $0x3,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %R15,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SAL $0x3,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%RSI,%RSI,2),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x5,%R12	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
AND $0x1fffffff,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%R10,%R10,2),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x5,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA 0x10(%RSI,%RDI,1),%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD $0x58,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 45e2fb <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x27b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_4

Source file and lines	DiracDeterminantRef.cpp:156-181
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83,155
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorOps.h:111,131
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:156-181
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:217
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62,169
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/unique_ptr.h:173
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,248

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.50 to 5.67 cycles (3.62x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

22% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

20% of SSE/AVX loads are used in vector version.
20% of SSE/AVX stores are used in vector version.
25% of SSE/AVX addition or subtraction instructions are used in vector version.
66% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
23% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 2 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

CALL instructions

Detected function call instructions.

Details

qmcplusplus::TimerType
::start(): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:159
qmcplusplus::TimerType
::stop(): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:161
unknown: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:160

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:181

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 14 FP arithmetical operations:

7: addition or subtraction (2 inside FMA instructions)
7: multiply (2 inside FMA instructions)

The binary function is loading 268 bytes (33 double precision FP elements). The binary function is storing 96 bytes (12 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	116
nb uops	121
loop length	623
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	7
ADD-SUB / MUL ratio	1.33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.50 cycles
front end	20.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.00	4.90	13.67	13.67	9.50	4.80	6.50	9.50	9.50	9.50	4.80	13.67
cycles	7.00	4.90	13.67	13.67	9.50	4.80	6.50	9.50	9.50	9.50	4.80	13.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	20.50
Dispatch	13.67
Overall L1	20.50

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	42%
load	33%
store	40%
mul	66%
add-sub	25%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	22%
load	20%
store	20%
mul	66%
add-sub	25%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Vector efficiency ratios

INT

all	11%
load	10%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	17%
load	16%
store	17%
mul	20%
add-sub	15%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	14%
load	14%
store	14%
mul	20%
add-sub	15%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.50 cycles. At this rate:

6% of peak load performance is reached (13.07 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.68 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 45e080

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMPL $0,0xc(%RDI)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JNE 45e0f7 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x77>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x468(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 4b6140 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x470(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x478(%RBX),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x47c(%RBX),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x90(%RBX),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x110(%RBX),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x150(%RBX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDI),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALLQ 0x28(%R10)	3	0.70	0.20	0.33	0.33	0.50	0.20	0.70	0.50	0.50	0.50	0.20	0.33	0	2.27	N/A
MOV 0x468(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 4b63c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD 0x484(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 45e198 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x118>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 45e1c0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x140>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x100(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVDDUP (%RAX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x140(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVQ $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMULPD (%RAX),%XMM0,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VMOVUPD %XMM1,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMULSD 0x10(%RAX),%XMM0,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD 0x478(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RDX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RAX,%RAX,2),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VADDPD (%RDX,%RSI,8),%XMM1,%XMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (25.0%)
VMOVUPD %XMM2,(%RDX,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD 0x10(%RDX,%RSI,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD -0x30(%RBP),%XMM2,%XMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM2,0x10(%RDX,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x180(%RBX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD -0x38(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMULPD %XMM2,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM2,%XMM2,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM3,%XMM2,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD231SD %XMM1,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMSUB231SD (%RDX),%XMM0,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV 0x18(%RCX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VADDSD (%RCX,%RAX,8),%XMM2,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVSXD 0x478(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd8(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x100(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x180(%RBX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x158(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x480(%RBX),%R11D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x140(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x118(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RDX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RCX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DEC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x2,%R10D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %R11D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7ffffffc,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SAL $0x3,%R14	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %R14,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SAL $0x3,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %R15,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SAL $0x3,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%RSI,%RSI,2),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x5,%R12	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
AND $0x1fffffff,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%R10,%R10,2),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x5,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA 0x10(%RSI,%RDI,1),%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD $0x58,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 45e2fb <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x27b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::DiracDeterminantRef >::evaluateGL(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus:...–	0.86	0.74
▼Loop 1044 - inner_product.hpp:82-155 - exec–	0.00	0.01
○Loop 1046 - inner_product.hpp:155-155 - exec	0.62	0.53
○Loop 1048 - inner_product.hpp:82-83 - exec	0.24	0.20
○Loop 1045 - inner_product.hpp:155-155 - exec	0.00	0.00
○Loop 1047 - inner_product.hpp:82-83 - exec	0.00	0.00

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Code clean check

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Execution units bottlenecks

FMA

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CALL instructions

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Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code