OV - exec - Function miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector<double, std::allocator<double> >&, qmcplusplus::Vector<qmcplusplus::TinyVector<double, 3u>, std::allocator<qmcplusplus::TinyVector<double, 3u> > >&, qmcplusplus::Vector<double, std::allocator<double> >&)

	Function: miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int ...	Module: exec	Source: einspline_spo_ref.hpp:203-230 [...]	Coverage (incl. loops): 11.09% \| (excl. loops): 0.01%

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 231 - 271

--------------------------------------------------------------------------------

231:   inline const AoSElement_t operator[](size_t i) const { return AoSElement_t(myData + i, nGhosts); }

[...]

265:   inline T* data() { return myData; }

[...]

271:   inline T* restrict data(size_t i) { return myData + i * nGhosts; }

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h: 150 - 152

--------------------------------------------------------------------------------

150:     return TinyVector<Type_t, 3>(lhs[0] * rhs[0] + lhs[1] * rhs[3] + lhs[2] * rhs[6],

151:                                  lhs[0] * rhs[1] + lhs[1] * rhs[4] + lhs[2] * rhs[7],

152:                                  lhs[0] * rhs[2] + lhs[1] * rhs[5] + lhs[2] * rhs[8]);

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 203 - 230

--------------------------------------------------------------------------------

203:     ScopedTimer local_timer(timer);

204:

205:     auto u = Lattice.toUnit_floor(P.activeR(iat));

206:     for (int i = 0; i < nBlocks; ++i)

207:       MultiBsplineEvalRef::evaluate_vgh(einsplines[i], u[0], u[1], u[2], psi[i].data(), grad[i].data(), hess[i].data(),

208:                                         nSplinesPerBlock);

[...]

216:   {

217:     evaluate_vgh(P, iat);

218:

219:     for (int i = 0; i < nBlocks; ++i)

220:     {

221:       // in real simulation, phase needs to be applied. Here just fake computation

222:       const int first = i * nBlocks;

223:       for (int j = first; j < std::min((i + 1) * nSplinesPerBlock, OrbitalSetSize); j++)

224:       {

225:         psi_v[j]   = psi[i][j - first];

226:         dpsi_v[j]  = grad[i][j - first];

227:         d2psi_v[j] = hess[i].data(0)[j - first];

228:       }

229:     }

230:   }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 1046 - 1169

--------------------------------------------------------------------------------

1046: 	return *(this->_M_impl._M_start + __n);

[...]

1169:       { return _M_data_ptr(this->_M_impl._M_start); }

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h: 170 - 170

--------------------------------------------------------------------------------

170:       if (-std::numeric_limits<T1>::epsilon() < val_dot[i] && val_dot[i] < 0)

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h: 235 - 924

--------------------------------------------------------------------------------

235:       if (__b < __a)

[...]

923:       for (; __first != __last; ++__first)

924: 	*__first = __tmp;

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 61 - 145

--------------------------------------------------------------------------------

61:     for (size_t d = 0; d < D; ++d)

[...]

145:       X[i] = base[i * offset];

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp: 45 - 47

--------------------------------------------------------------------------------

45:   T sf = std::floor(x);

46:   T dx2 = x - sf;

47:   int ind2 = std::min(std::max(0, static_cast<int>(sf)), nmax);

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 223

--------------------------------------------------------------------------------

223:     return X[i];

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 143 - 143

--------------------------------------------------------------------------------

143:     return (active_ptcl_ == iat) ? active_pos_ : R[iat];

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp: 68 - 79

--------------------------------------------------------------------------------

68:     a[0]   = ((A00 * tx + A01) * tx + A02) * tx + A03;

69:     a[1]   = ((A10 * tx + A11) * tx + A12) * tx + A13;

70:     a[2]   = ((A20 * tx + A21) * tx + A22) * tx + A23;

71:     a[3]   = ((A30 * tx + A31) * tx + A32) * tx + A33;

72:     da[0]  = (dA01 * tx + dA02) * tx + dA03;

73:     da[1]  = (dA11 * tx + dA12) * tx + dA13;

74:     da[2]  = (dA21 * tx + dA22) * tx + dA23;

75:     da[3]  = (dA31 * tx + dA32) * tx + dA33;

76:     d2a[0] = d2A02 * tx + d2A03;

77:     d2a[1] = d2A12 * tx + d2A13;

78:     d2a[2] = d2A22 * tx + d2A23;

79:     d2a[3] = d2A32 * tx + d2A33;

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 187 - 286

--------------------------------------------------------------------------------

187:   x -= spline_m->x_grid.start;

188:   y -= spline_m->y_grid.start;

189:   z -= spline_m->z_grid.start;

190:   spline2::getSplineBound(x * spline_m->x_grid.delta_inv, tx, ix, spline_m->x_grid.num - 1);

191:   spline2::getSplineBound(y * spline_m->y_grid.delta_inv, ty, iy, spline_m->y_grid.num - 1);

192:   spline2::getSplineBound(z * spline_m->z_grid.delta_inv, tz, iz, spline_m->z_grid.num - 1);

[...]

198:   const intptr_t xs = spline_m->x_stride;

199:   const intptr_t ys = spline_m->y_stride;

200:   const intptr_t zs = spline_m->z_stride;

201:

202:   const size_t out_offset = spline_m->num_splines;

[...]

226:   for (int i = 0; i < 4; i++)

227:     for (int j = 0; j < 4; j++)

228:     {

229:       const T* restrict coefs    = spline_m->coefs + (ix + i) * xs + (iy + j) * ys + iz * zs;

230:       const T* restrict coefszs  = coefs + zs;

231:       const T* restrict coefs2zs = coefs + 2 * zs;

232:       const T* restrict coefs3zs = coefs + 3 * zs;

233:

234:       const T pre20 = d2a[i] * b[j];

235:       const T pre10 = da[i] * b[j];

236:       const T pre00 = a[i] * b[j];

237:       const T pre11 = da[i] * db[j];

238:       const T pre01 = a[i] * db[j];

239:       const T pre02 = a[i] * d2b[j];

240:

241:       const int iSplitPoint = num_splines;

242:       for (int n = 0; n < iSplitPoint; n++)

243:       {

244:         T coefsv    = coefs[n];

245:         T coefsvzs  = coefszs[n];

246:         T coefsv2zs = coefs2zs[n];

247:         T coefsv3zs = coefs3zs[n];

248:

249:         T sum0 = c[0] * coefsv + c[1] * coefsvzs + c[2] * coefsv2zs + c[3] * coefsv3zs;

250:         T sum1 = dc[0] * coefsv + dc[1] * coefsvzs + dc[2] * coefsv2zs + dc[3] * coefsv3zs;

251:         T sum2 = d2c[0] * coefsv + d2c[1] * coefsvzs + d2c[2] * coefsv2zs + d2c[3] * coefsv3zs;

252:

253:         hxx[n] += pre20 * sum0;

254:         hxy[n] += pre11 * sum0;

255:         hxz[n] += pre10 * sum1;

256:         hyy[n] += pre02 * sum0;

257:         hyz[n] += pre01 * sum1;

258:         hzz[n] += pre00 * sum2;

259:         gx[n] += pre10 * sum0;

260:         gy[n] += pre01 * sum0;

261:         gz[n] += pre00 * sum1;

262:         vals[n] += pre00 * sum0;

[...]

269:   const T dxx   = dxInv * dxInv;

270:   const T dyy   = dyInv * dyInv;

271:   const T dzz   = dzInv * dzInv;

272:   const T dxy   = dxInv * dyInv;

273:   const T dxz   = dxInv * dzInv;

274:   const T dyz   = dyInv * dzInv;

275:

276:   for (int n = 0; n < num_splines; n++)

277:   {

278:     gx[n] *= dxInv;

279:     gy[n] *= dyInv;

280:     gz[n] *= dzInv;

281:     hxx[n] *= dxx;

282:     hyy[n] *= dyy;

283:     hzz[n] *= dzz;

284:     hxy[n] *= dxy;

285:     hxz[n] *= dxz;

286:     hyz[n] *= dyz;

0x450100 PUSH	%RBP

0x450101 MOV	%RSP,%RBP

0x450104 PUSH	%R15

0x450106 PUSH	%R14

0x450108 PUSH	%R13

0x45010a PUSH	%R12

0x45010c PUSH	%RBX

0x45010d AND	$-0x20,%RSP

0x450111 SUB	$0x3c0,%RSP

0x450118 MOV	%R9,%R15

0x45011b MOV	%R8,%R12

0x45011e MOV	%RCX,%R13

0x450121 MOV	%EDX,0x30(%RSP)

0x450125 MOV	%RSI,%R14

0x450128 MOV	%RDI,%RBX

0x45012b MOV	0x358(%RDI),%RDI

0x450132 MOV	%RDI,0x70(%RSP)

0x450137 CALL	4b6140 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>

0x45013c MOVSXD	0x30(%RSP),%RAX

0x450141 LEA	(%RAX,%RAX,2),%RCX

0x450145 SAL	$0x3,%RCX

0x450149 ADD	0x40(%R14),%RCX

0x45014d CMP	%EAX,0x124(%R14)

0x450154 LEA	0x128(%R14),%RAX

0x45015b MOV	%RBX,%R14

0x45015e CMOVNE	%RCX,%RAX

0x450162 MOVSXD	0x30(%RBX),%RCX

0x450166 MOV	%RCX,0x48(%RSP)

0x45016b TEST	%RCX,%RCX

0x45016e MOV	%RBX,0x58(%RSP)

0x450173 JLE	451340

0x450179 VMOVSD	(%RAX),%XMM0

0x45017d VMULSD	0xd8(%R14),%XMM0,%XMM1

0x450186 VMOVSD	0x8(%RAX),%XMM2

0x45018b VFMADD231SD	0xf0(%R14),%XMM2,%XMM1

0x450194 VMOVSD	0x10(%RAX),%XMM3

0x450199 VFMADD231SD	0x108(%R14),%XMM3,%XMM1

0x4501a2 VMULSD	0xe0(%R14),%XMM0,%XMM4

0x4501ab VFMADD231SD	0xf8(%R14),%XMM2,%XMM4

0x4501b4 VFMADD231SD	0x110(%R14),%XMM3,%XMM4

0x4501bd VMULSD	0xe8(%R14),%XMM0,%XMM0

0x4501c6 VFMADD231SD	0x100(%R14),%XMM2,%XMM0

0x4501cf VFMADD231SD	0x118(%R14),%XMM3,%XMM0

0x4501d8 VROUNDSD	$0x9,%XMM1,%XMM1,%XMM2

0x4501de VSUBSD	%XMM2,%XMM1,%XMM6

0x4501e2 VXORPD	%XMM2,%XMM2,%XMM2

0x4501e6 VCMPSD	$0x1,%XMM2,%XMM1,%K1

0x4501ed VMOVAPD	%XMM6,%XMM3

0x4501f1 VMOVSD	%XMM2,%XMM3,%XMM3{%K1}

0x4501f7 VMOVSD	0xe9c29(%RIP),%XMM5

0x4501ff VCMPSD	$0x1,%XMM1,%XMM5,%K1

0x450206 VMOVSD	%XMM3,%XMM6,%XMM6{%K1}

0x45020c VMOVUPD	%XMM6,0x1c0(%RSP)

0x450215 VROUNDSD	$0x9,%XMM4,%XMM4,%XMM1

0x45021b VSUBSD	%XMM1,%XMM4,%XMM6

0x45021f VCMPSD	$0x1,%XMM2,%XMM4,%K1

0x450226 VMOVAPD	%XMM6,%XMM1

0x45022a VMOVSD	%XMM2,%XMM1,%XMM1{%K1}

0x450230 VCMPSD	$0x1,%XMM4,%XMM5,%K1

0x450237 VROUNDSD	$0x9,%XMM0,%XMM0,%XMM3

0x45023d VMOVSD	%XMM1,%XMM6,%XMM6{%K1}

0x450243 VMOVUPD	%XMM6,0x1b0(%RSP)

0x45024c VSUBSD	%XMM3,%XMM0,%XMM3

0x450250 VCMPSD	$0x1,%XMM2,%XMM0,%K1

0x450257 VMOVAPD	%XMM3,%XMM1

0x45025b VMOVSD	%XMM2,%XMM1,%XMM1{%K1}

0x450261 VCMPSD	$0x1,%XMM0,%XMM5,%K1

0x450268 VMOVSD	%XMM1,%XMM3,%XMM3{%K1}

0x45026e VMOVUPD	%XMM3,0x1a0(%RSP)

0x450277 MOV	0x2f8(%R14),%RAX

0x45027e MOV	%RAX,0xa0(%RSP)

0x450286 MOV	0x310(%R14),%RAX

0x45028d MOV	%RAX,0x98(%RSP)

0x450295 MOV	0x328(%R14),%RAX

0x45029c MOV	%RAX,0x90(%RSP)

0x4502a4 MOV	0x340(%R14),%RAX

0x4502ab MOV	%RAX,0x88(%RSP)

0x4502b3 MOVSXD	0x40(%R14),%R11

0x4502b7 LEA	(,%R11,8),%RAX

0x4502bf MOV	%RAX,0x80(%RSP)

0x4502c7 DECQ	0x48(%RSP)

0x4502cc MOV	%R11D,%EAX

0x4502cf AND	$0x7fffffff,%EAX

0x4502d4 MOV	%RAX,0x30(%RSP)

0x4502d9 MOV	%R11D,%EAX

0x4502dc AND	$0x7ffffffc,%EAX

0x4502e1 MOV	%RAX,0x68(%RSP)

0x4502e6 MOV	%R11,%R10

0x4502e9 AND	$-0x4,%R10

0x4502ed XOR	%EDX,%EDX

0x4502ef VMOVSD	0xe9b37(%RIP),%XMM16

0x4502f9 VMOVSD	0xe6d1d(%RIP),%XMM22

0x450303 VMOVDDUP	0xe6d15(%RIP),%XMM0

0x45030b VMOVUPS	%XMM0,0x190(%RSP)

0x450314 VMOVSD	0xe6d1a(%RIP),%XMM23

0x45031e VMOVSD	0xe6d18(%RIP),%XMM24

0x450328 VMOVSD	0xe9b0e(%RIP),%XMM26

0x450332 VMOVSD	0xe6d44(%RIP),%XMM27

0x45033c VMOVSD	0xe7eb2(%RIP),%XMM28

0x450346 VMOVDDUP	0xe6d32(%RIP),%XMM0

0x45034e VMOVUPD	%XMM0,0x180(%RSP)

0x450357 MOV	%R15,0xb8(%RSP)

0x45035f MOV	%R12,0xb0(%RSP)

0x450367 MOV	%R13,0xa8(%RSP)

0x45036f MOV	%R11,0x60(%RSP)

0x450374 MOV	%R10,0x78(%RSP)

0x450379 JMP	4503a7

0x45037b NOPL	(%RAX,%RAX,1)

(927) 0x450380 MOV	0xc0(%RSP),%RDX

(927) 0x450388 CMP	0x48(%RSP),%RDX

(927) 0x45038d LEA	0x1(%RDX),%RDX

(927) 0x450391 MOV	0xb8(%RSP),%R15

(927) 0x450399 MOV	0xb0(%RSP),%R12

(927) 0x4503a1 JE	451340

(927) 0x4503a7 LEA	(,%RDX,8),%RAX

(927) 0x4503af MOV	0xa0(%RSP),%RCX

(927) 0x4503b7 MOV	(%RCX,%RDX,8),%R10

(927) 0x4503bb MOV	%RDX,0xc0(%RSP)

(927) 0x4503c3 LEA	(%RDX,%RDX,2),%RCX

(927) 0x4503c7 MOV	0x98(%RSP),%RDX

(927) 0x4503cf MOV	(%RDX,%RCX,8),%R14

(927) 0x4503d3 LEA	(%RAX,%RAX,4),%RAX

(927) 0x4503d7 MOV	0x90(%RSP),%RCX

(927) 0x4503df MOV	0x18(%RCX,%RAX,1),%RCX

(927) 0x4503e4 MOV	%RCX,0x18(%RSP)

(927) 0x4503e9 VMOVUPD	0x1c0(%RSP),%XMM0

(927) 0x4503f2 VSUBSD	0x28(%R10),%XMM0,%XMM0

(927) 0x4503f8 MOV	0x88(%RSP),%RCX

(927) 0x450400 MOV	0x18(%RCX,%RAX,1),%RBX

(927) 0x450405 VMOVUPD	0x1b0(%RSP),%XMM1

(927) 0x45040e VSUBSD	0x50(%R10),%XMM1,%XMM1

(927) 0x450414 VMOVUPD	0x1a0(%RSP),%XMM2

(927) 0x45041d VSUBSD	0x78(%R10),%XMM2,%XMM2

(927) 0x450423 VMOVSD	0x48(%R10),%XMM3

(927) 0x450429 VMOVSD	0x70(%R10),%XMM4

(927) 0x45042f VMOVUPD	%XMM3,0x1f0(%RSP)

(927) 0x450438 VMULSD	%XMM0,%XMM3,%XMM0

(927) 0x45043c MOVSXD	0x38(%R10),%RAX

(927) 0x450440 MOV	%RAX,0x8(%RSP)

(927) 0x450445 VRNDSCALESD	$0x9,%XMM0,%XMM0,%XMM19

(927) 0x45044c VSUBSD	%XMM19,%XMM0,%XMM3

(927) 0x450452 VMOVUPD	%XMM4,0x1e0(%RSP)

(927) 0x45045b VMULSD	%XMM1,%XMM4,%XMM1

(927) 0x45045f MOVSXD	0x60(%R10),%R13

(927) 0x450463 VRNDSCALESD	$0x9,%XMM1,%XMM1,%XMM25

(927) 0x45046a VMOVSD	0x98(%R10),%XMM0

(927) 0x450473 VMOVUPD	%XMM0,0x1d0(%RSP)

(927) 0x45047c VMULSD	%XMM2,%XMM0,%XMM0

(927) 0x450480 MOVSXD	0x88(%R10),%RAX

(927) 0x450487 MOV	%RAX,0x20(%RSP)

(927) 0x45048c VRNDSCALESD	$0x9,%XMM0,%XMM0,%XMM20

(927) 0x450493 VMULSD	%XMM16,%XMM3,%XMM2

(927) 0x450499 VSUBSD	%XMM2,%XMM22,%XMM4

(927) 0x45049f VMULSD	%XMM3,%XMM3,%XMM5

(927) 0x4504a3 VMOVDDUP	%XMM3,%XMM6

(927) 0x4504a7 VMOVUPD	0x190(%RSP),%XMM8

(927) 0x4504b0 VBLENDPD	$0x1,%XMM4,%XMM8,%XMM4

(927) 0x4504b6 VMULPD	%XMM4,%XMM6,%XMM4

(927) 0x4504ba VMOVUPD	0xe99ae(%RIP),%XMM9

(927) 0x4504c2 VADDPD	%XMM4,%XMM9,%XMM7

(927) 0x4504c6 VPUNPCKLQDQ	%XMM5,%XMM6,%XMM6

(927) 0x4504ca VMOVUPD	0xe99ae(%RIP),%XMM10

(927) 0x4504d2 VFMADD213PD	%XMM10,%XMM7,%XMM6

(927) 0x4504d7 VMOVUPD	%XMM6,0x2e0(%RSP)

(927) 0x4504e0 VMULSD	%XMM23,%XMM3,%XMM6

(927) 0x4504e6 VADDSD	%XMM22,%XMM6,%XMM7

(927) 0x4504ec VFMADD213SD	%XMM22,%XMM3,%XMM7

(927) 0x4504f2 VFMADD213SD	%XMM16,%XMM3,%XMM7

(927) 0x4504f8 VMOVSD	%XMM7,0x2f0(%RSP)

(927) 0x450501 VMULSD	%XMM5,%XMM2,%XMM2

(927) 0x450505 VMOVSD	%XMM2,0x2f8(%RSP)

(927) 0x45050e VADDSD	%XMM24,%XMM6,%XMM2

(927) 0x450514 VFMADD213SD	%XMM23,%XMM3,%XMM2

(927) 0x45051a VMOVSD	%XMM2,0x160(%RSP)

(927) 0x450523 VMULSD	%XMM26,%XMM3,%XMM2

(927) 0x450529 VADDSD	%XMM27,%XMM2,%XMM5

(927) 0x45052f VMULSD	%XMM3,%XMM5,%XMM5

(927) 0x450533 VMOVSD	%XMM5,0x168(%RSP)

(927) 0x45053c VSUBSD	%XMM2,%XMM24,%XMM2

(927) 0x450542 VFMADD213SD	%XMM22,%XMM3,%XMM2

(927) 0x450548 VMOVSD	%XMM2,0x170(%RSP)

(927) 0x450551 VSHUFPD	$0x1,%XMM4,%XMM4,%XMM2

(927) 0x450556 VMULSD	%XMM3,%XMM2,%XMM2

(927) 0x45055a VMOVSD	%XMM2,0x178(%RSP)

(927) 0x450563 VMULSD	%XMM28,%XMM3,%XMM2

(927) 0x450569 VMOVDDUP	%XMM2,%XMM4

(927) 0x45056d VSUBSD	%XMM3,%XMM24,%XMM5

(927) 0x450573 VMOVUPD	0x180(%RSP),%XMM7

(927) 0x45057c VADDSD	%XMM7,%XMM4,%XMM4

(927) 0x450580 VMOVDDUP	%XMM4,%XMM4

(927) 0x450584 VBLENDPD	$0x1,%XMM5,%XMM4,%XMM4

(927) 0x45058a VMOVUPD	%XMM4,0x2a0(%RSP)

(927) 0x450593 VSUBSD	%XMM25,%XMM1,%XMM1

(927) 0x450599 VSUBSD	%XMM2,%XMM24,%XMM2

(927) 0x45059f VMOVSD	%XMM2,0x2b0(%RSP)

(927) 0x4505a8 VMOVSD	%XMM3,0x2b8(%RSP)

(927) 0x4505b1 VMULSD	%XMM16,%XMM1,%XMM2

(927) 0x4505b7 VSUBSD	%XMM2,%XMM22,%XMM3

(927) 0x4505bd VMULSD	%XMM1,%XMM1,%XMM4

(927) 0x4505c1 VMOVDDUP	%XMM1,%XMM5

(927) 0x4505c5 VBLENDPD	$0x1,%XMM3,%XMM8,%XMM3

(927) 0x4505cb VMULPD	%XMM3,%XMM5,%XMM3

(927) 0x4505cf VADDPD	%XMM3,%XMM9,%XMM6

(927) 0x4505d3 VPUNPCKLQDQ	%XMM4,%XMM5,%XMM5

(927) 0x4505d7 VFMADD213PD	%XMM10,%XMM6,%XMM5

(927) 0x4505dc VMOVUPD	%XMM5,0x2c0(%RSP)

(927) 0x4505e5 VMULSD	%XMM23,%XMM1,%XMM5

(927) 0x4505eb VADDSD	%XMM22,%XMM5,%XMM6

(927) 0x4505f1 VFMADD213SD	%XMM22,%XMM1,%XMM6

(927) 0x4505f7 VFMADD213SD	%XMM16,%XMM1,%XMM6

(927) 0x4505fd VMOVSD	%XMM6,0x2d0(%RSP)

(927) 0x450606 VMULSD	%XMM4,%XMM2,%XMM2

(927) 0x45060a VMOVSD	%XMM2,0x2d8(%RSP)

(927) 0x450613 VADDSD	%XMM24,%XMM5,%XMM2

(927) 0x450619 VFMADD213SD	%XMM23,%XMM1,%XMM2

(927) 0x45061f VMOVSD	%XMM2,0x140(%RSP)

(927) 0x450628 VMULSD	%XMM26,%XMM1,%XMM2

(927) 0x45062e VADDSD	%XMM27,%XMM2,%XMM4

(927) 0x450634 VMULSD	%XMM1,%XMM4,%XMM4

(927) 0x450638 VMOVSD	%XMM4,0x148(%RSP)

(927) 0x450641 VSUBSD	%XMM20,%XMM0,%XMM21

(927) 0x450647 VSUBSD	%XMM2,%XMM24,%XMM0

(927) 0x45064d VFMADD213SD	%XMM22,%XMM1,%XMM0

(927) 0x450653 VMOVSD	%XMM0,0x150(%RSP)

(927) 0x45065c VSHUFPD	$0x1,%XMM3,%XMM3,%XMM0

(927) 0x450661 VMULSD	%XMM1,%XMM0,%XMM0

(927) 0x450665 VMOVSD	%XMM0,0x158(%RSP)

(927) 0x45066e VMULSD	%XMM28,%XMM1,%XMM0

(927) 0x450674 VMOVDDUP	%XMM0,%XMM2

(927) 0x450678 VSUBSD	%XMM1,%XMM24,%XMM3

(927) 0x45067e VADDSD	%XMM7,%XMM2,%XMM2

(927) 0x450682 VMOVDDUP	%XMM2,%XMM2

(927) 0x450686 VBLENDPD	$0x1,%XMM3,%XMM2,%XMM2

(927) 0x45068c VMOVUPD	%XMM2,0x280(%RSP)

(927) 0x450695 VSUBSD	%XMM0,%XMM24,%XMM0

(927) 0x45069b VMOVSD	%XMM0,0x290(%RSP)

(927) 0x4506a4 VMOVSD	%XMM1,0x298(%RSP)

(927) 0x4506ad VMULSD	%XMM21,%XMM21,%XMM17

(927) 0x4506b3 VMULSD	%XMM23,%XMM21,%XMM18

(927) 0x4506b9 VADDSD	%XMM22,%XMM18,%XMM0

(927) 0x4506bf VMOVDDUP	0xe6959(%RIP),%XMM1

(927) 0x4506c7 VPUNPCKLQDQ	%XMM0,%XMM1,%XMM0

(927) 0x4506cb VMOVDDUP	%XMM21,%XMM1

(927) 0x4506d1 VMULPD	%XMM0,%XMM1,%XMM15

(927) 0x4506d5 VADDPD	0xe97c3(%RIP),%XMM15,%XMM0

(927) 0x4506dd VPUNPCKLQDQ	%XMM1,%XMM17,%XMM1

(927) 0x4506e3 VFMADD213PD	0xe97c4(%RIP),%XMM0,%XMM1

(927) 0x4506ec VMOVUPD	%YMM1,0x300(%RSP)

(927) 0x4506f5 MOV	0x10(%R10),%RAX

(927) 0x4506f9 MOV	%RAX,0x38(%RSP)

(927) 0x4506fe MOV	0x18(%R10),%RAX

(927) 0x450702 MOV	%RAX,0x40(%RSP)

(927) 0x450707 MOV	0x20(%R10),%RAX

(927) 0x45070b MOV	%RAX,0x10(%RSP)

(927) 0x450710 MOVSXD	0xe8(%R10),%RAX

(927) 0x450717 MOV	0x80(%RSP),%R15

(927) 0x45071f TEST	%R15,%R15

(927) 0x450722 MOV	%RAX,(%RSP)

(927) 0x450726 VMOVUPD	%XMM15,0x130(%RSP)

(927) 0x45072f JE	450805

(927) 0x450735 MOV	%R14,%RDI

(927) 0x450738 XOR	%ESI,%ESI

(927) 0x45073a MOV	%R15,%RDX

(927) 0x45073d MOV	%R10,0x28(%RSP)

(927) 0x450742 VZEROUPPER

(927) 0x450745 CALL	534740 <__intel_avx_rep_memset>

(927) 0x45074a MOV	0x18(%RSP),%R12

(927) 0x45074f MOV	%R12,%RDI

(927) 0x450752 XOR	%ESI,%ESI

(927) 0x450754 MOV	%R15,%RDX

(927) 0x450757 CALL	534740 <__intel_avx_rep_memset>

(927) 0x45075c MOV	(%RSP),%RAX

(927) 0x450760 LEA	(%R12,%RAX,8),%RDI

(927) 0x450764 XOR	%ESI,%ESI

(927) 0x450766 MOV	%R15,%RDX

(927) 0x450769 CALL	534740 <__intel_avx_rep_memset>

(927) 0x45076e MOV	(%RSP),%RAX

(927) 0x450772 SAL	$0x4,%RAX

(927) 0x450776 LEA	(%R12,%RAX,1),%RDI

(927) 0x45077a MOV	%RAX,%R12

(927) 0x45077d XOR	%ESI,%ESI

(927) 0x45077f MOV	%R15,%RDX

(927) 0x450782 CALL	534740 <__intel_avx_rep_memset>

(927) 0x450787 MOV	%RBX,%RDI

(927) 0x45078a XOR	%ESI,%ESI

(927) 0x45078c MOV	%R15,%RDX

(927) 0x45078f CALL	534740 <__intel_avx_rep_memset>

(927) 0x450794 MOV	(%RSP),%RAX

(927) 0x450798 LEA	(%RBX,%RAX,8),%RDI

(927) 0x45079c XOR	%ESI,%ESI

(927) 0x45079e MOV	%R15,%RDX

(927) 0x4507a1 CALL	534740 <__intel_avx_rep_memset>

(927) 0x4507a6 ADD	%RBX,%R12

(927) 0x4507a9 MOV	%R12,%RDI

(927) 0x4507ac XOR	%ESI,%ESI

(927) 0x4507ae MOV	%R15,%RDX

(927) 0x4507b1 CALL	534740 <__intel_avx_rep_memset>

(927) 0x4507b6 MOV	(%RSP),%RAX

(927) 0x4507ba LEA	(%RAX,%RAX,2),%RAX

(927) 0x4507be LEA	(%RBX,%RAX,8),%RDI

(927) 0x4507c2 XOR	%ESI,%ESI

(927) 0x4507c4 MOV	%R15,%RDX

(927) 0x4507c7 CALL	534740 <__intel_avx_rep_memset>

(927) 0x4507cc MOV	(%RSP),%RDI

(927) 0x4507d0 SAL	$0x5,%RDI

(927) 0x4507d4 ADD	%RBX,%RDI

(927) 0x4507d7 XOR	%ESI,%ESI

(927) 0x4507d9 MOV	%R15,%RDX

(927) 0x4507dc CALL	534740 <__intel_avx_rep_memset>

(927) 0x4507e1 MOV	(%RSP),%RAX

(927) 0x4507e5 LEA	(%RAX,%RAX,4),%RAX

(927) 0x4507e9 LEA	(%RBX,%RAX,8),%RDI

(927) 0x4507ed XOR	%ESI,%ESI

(927) 0x4507ef MOV	%R15,%RDX

(927) 0x4507f2 CALL	534740 <__intel_avx_rep_memset>

(927) 0x4507f7 MOV	0x28(%RSP),%R10

(927) 0x4507fc VMOVUPD	0x130(%RSP),%XMM15

(927) 0x450805 VCVTTSD2SI	%XMM19,%ECX

(927) 0x45080b VCVTTSD2SI	%XMM25,%EDX

(927) 0x450811 VCVTTSD2SI	%XMM20,%EAX

(927) 0x450817 MOV	0x20(%RSP),%RDI

(927) 0x45081c DEC	%RDI

(927) 0x45081f MOV	%EAX,%ESI

(927) 0x450821 SAR	$0x1f,%ESI

(927) 0x450824 ANDN	%EAX,%ESI,%EAX

(927) 0x450829 CMP	%RAX,%RDI

(927) 0x45082c CMOVGE	%RAX,%RDI

(927) 0x450830 MOV	0x10(%RSP),%RSI

(927) 0x450835 MOV	%RSI,%RAX

(927) 0x450838 MOV	%RSI,%R9

(927) 0x45083b IMUL	%RDI,%RAX

(927) 0x45083f MOV	%RAX,0x20(%RSP)

(927) 0x450844 DEC	%R13

(927) 0x450847 MOV	%EDX,%ESI

(927) 0x450849 SAR	$0x1f,%ESI

(927) 0x45084c ANDN	%EDX,%ESI,%EDX

(927) 0x450851 CMP	%RDX,%R13

(927) 0x450854 CMOVGE	%RDX,%R13

(927) 0x450858 MOV	0x40(%RSP),%R8

(927) 0x45085d MOV	%R8,%RDX

(927) 0x450860 IMUL	%R13,%RDX

(927) 0x450864 MOV	0x8(%RSP),%RAX

(927) 0x450869 DEC	%RAX

(927) 0x45086c MOV	%ECX,%ESI

(927) 0x45086e SAR	$0x1f,%ESI

(927) 0x450871 ANDN	%ECX,%ESI,%ECX

(927) 0x450876 CMP	%RCX,%RAX

(927) 0x450879 CMOVGE	%RCX,%RAX

(927) 0x45087d MOV	0x38(%RSP),%RCX

(927) 0x450882 MOV	%RCX,%RSI

(927) 0x450885 IMUL	%RAX,%RSI

(927) 0x450889 ADD	%RDX,%RSI

(927) 0x45088c MOV	%RSI,0x8(%RSP)

(927) 0x450891 SAL	$0x3,%R8

(927) 0x450895 MOV	%R8,0x40(%RSP)

(927) 0x45089a IMUL	%R8,%R13

(927) 0x45089e SAL	$0x3,%RCX

(927) 0x4508a2 MOV	%RCX,0x38(%RSP)

(927) 0x4508a7 IMUL	%RCX,%RAX

(927) 0x4508ab LEA	(%R13,%RAX,1),%RCX

(927) 0x4508b0 LEA	(,%R9,8),%R11

(927) 0x4508b8 LEA	0x3(%RDI),%R9

(927) 0x4508bc LEA	0x2(%RDI),%R8

(927) 0x4508c0 MOV	%R11,%R15

(927) 0x4508c3 LEA	0x1(%RDI),%RDX

(927) 0x4508c7 MOV	%R11,%R12

(927) 0x4508ca IMUL	%R11,%RDI

(927) 0x4508ce IMUL	%R9,%R11

(927) 0x4508d2 ADD	%RCX,%R11

(927) 0x4508d5 IMUL	%R8,%R15

(927) 0x4508d9 ADD	%RCX,%R15

(927) 0x4508dc IMUL	%RDX,%R12

(927) 0x4508e0 ADD	%RCX,%R12

(927) 0x4508e3 VMULSD	%XMM16,%XMM21,%XMM7

(927) 0x4508e9 VSUBSD	%XMM7,%XMM22,%XMM0

(927) 0x4508ef VFMADD213SD	%XMM23,%XMM21,%XMM0

(927) 0x4508f5 VFMADD213SD	%XMM16,%XMM21,%XMM0

(927) 0x4508fb VADDSD	%XMM24,%XMM18,%XMM1

(927) 0x450901 VFMADD213SD	%XMM23,%XMM21,%XMM1

(927) 0x450907 VMULSD	%XMM26,%XMM21,%XMM3

(927) 0x45090d VADDSD	%XMM27,%XMM3,%XMM2

(927) 0x450913 VSUBSD	%XMM3,%XMM24,%XMM3

(927) 0x450919 VFMADD213SD	%XMM22,%XMM21,%XMM3

(927) 0x45091f VSUBSD	%XMM21,%XMM24,%XMM8

(927) 0x450925 VMULSD	%XMM28,%XMM21,%XMM6

(927) 0x45092b VADDSD	%XMM27,%XMM6,%XMM9

(927) 0x450931 VSUBSD	%XMM6,%XMM24,%XMM10

(927) 0x450937 MOV	0x8(%R10),%R10

(927) 0x45093b VMULSD	%XMM17,%XMM7,%XMM11

(927) 0x450941 VBROADCASTSD	%XMM0,%YMM19

(927) 0x450947 VMOVUPD	0x300(%RSP),%YMM16

(927) 0x45094f VBROADCASTSD	%XMM16,%YMM18

(927) 0x450955 VPERMPD	$0x55,%YMM16,%YMM22

(927) 0x45095c VBROADCASTSD	%XMM11,%YMM25

(927) 0x450962 VBROADCASTSD	%XMM1,%YMM26

(927) 0x450968 VBROADCASTSD	%XMM2,%YMM27

(927) 0x45096e VBROADCASTSD	%XMM3,%YMM28

(927) 0x450974 VBROADCASTSD	%XMM15,%YMM4

(927) 0x450979 VMOVUPD	%YMM4,0x380(%RSP)

(927) 0x450982 VMOVAPD	%XMM8,%XMM4

(927) 0x450986 VBROADCASTSD	%XMM21,%YMM17

(927) 0x45098c VBROADCASTSD	%XMM8,%YMM5

(927) 0x450991 VMOVUPD	%YMM5,0x360(%RSP)

(927) 0x45099a VMOVAPD	%XMM9,%XMM5

(927) 0x45099e VBROADCASTSD	%XMM9,%YMM6

(927) 0x4509a3 VMOVUPD	%YMM6,0x340(%RSP)

(927) 0x4509ac VMOVAPD	%XMM10,%XMM6

(927) 0x4509b0 VBROADCASTSD	%XMM10,%YMM7

(927) 0x4509b5 VMOVUPD	%YMM7,0x320(%RSP)

(927) 0x4509be VMOVAPD	%XMM11,%XMM7

(927) 0x4509c2 ADD	%RAX,%RDI

(927) 0x4509c5 MOV	(%RSP),%RAX

(927) 0x4509c9 MOV	%RAX,%RCX

(927) 0x4509cc SAL	$0x4,%RCX

(927) 0x4509d0 ADD	%R10,%R13

(927) 0x4509d3 ADD	%RDI,%R13

(927) 0x4509d6 MOV	%RCX,0x50(%RSP)

(927) 0x4509db MOV	0x18(%RSP),%RSI

(927) 0x4509e0 ADD	%RSI,%RCX

(927) 0x4509e3 MOV	0x10(%RSP),%RDI

(927) 0x4509e8 IMUL	%RDI,%R9

(927) 0x4509ec MOV	%R9,%RSI

(927) 0x4509ef IMUL	%RDI,%R8

(927) 0x4509f3 IMUL	%RDX,%RDI

(927) 0x4509f7 LEA	(,%RAX,8),%R9

(927) 0x4509ff MOV	0x8(%RSP),%RDX

(927) 0x450a04 ADD	%RDX,%RSI

(927) 0x450a07 ADD	%RDX,%R8

(927) 0x450a0a ADD	%RDX,%RDI

(927) 0x450a0d MOV	%RDI,0x10(%RSP)

(927) 0x450a12 ADD	0x20(%RSP),%RDX

(927) 0x450a17 MOV	%RDX,0x8(%RSP)

(927) 0x450a1c MOV	0x18(%RSP),%RDX

(927) 0x450a21 LEA	(%RDX,%RAX,8),%RDX

(927) 0x450a25 ADD	%R10,%R11

(927) 0x450a28 ADD	%R10,%R15

(927) 0x450a2b ADD	%R10,%R12

(927) 0x450a2e LEA	(%R10,%RSI,8),%RAX

(927) 0x450a32 MOV	%R11,%RDI

(927) 0x450a35 LEA	(%R10,%R8,8),%R11

(927) 0x450a39 MOV	0x10(%RSP),%RSI

(927) 0x450a3e LEA	(%R10,%RSI,8),%R8

(927) 0x450a42 MOV	0x8(%RSP),%RSI

(927) 0x450a47 LEA	(%R10,%RSI,8),%RSI

(927) 0x450a4b MOV	%RAX,%R10

(927) 0x450a4e XOR	%EAX,%EAX

(927) 0x450a50 VMOVUPD	%XMM1,0x270(%RSP)

(927) 0x450a59 VMOVUPD	%XMM0,0x260(%RSP)

(927) 0x450a62 VMOVUPD	%XMM2,0x250(%RSP)

(927) 0x450a6b VMOVUPD	%XMM3,0x240(%RSP)

(927) 0x450a74 VMOVUPD	%XMM8,0x230(%RSP)

(927) 0x450a7d VMOVUPD	%XMM9,0x220(%RSP)

(927) 0x450a86 VMOVUPD	%XMM10,0x210(%RSP)

(927) 0x450a8f VMOVUPD	%XMM11,0x200(%RSP)

(927) 0x450a98 JMP	450b33

0x450a9d NOPW	%CS:(%RAX,%RAX,1)

0x450aac NOPW	%CS:(%RAX,%RAX,1)

0x450abb NOPL	(%RAX,%RAX,1)

  (930) 0x450ac0 MOV	0x38(%RSP),%RAX

  (930) 0x450ac5 MOV	0xf0(%RSP),%RDI

  (930) 0x450acd ADD	%RAX,%RDI

  (930) 0x450ad0 MOV	0x100(%RSP),%R15

  (930) 0x450ad8 ADD	%RAX,%R15

  (930) 0x450adb MOV	0xf8(%RSP),%R12

  (930) 0x450ae3 ADD	%RAX,%R12

  (930) 0x450ae6 MOV	0x108(%RSP),%R13

  (930) 0x450aee ADD	%RAX,%R13

  (930) 0x450af1 MOV	0xe8(%RSP),%R10

  (930) 0x450af9 ADD	%RAX,%R10

  (930) 0x450afc MOV	0xe0(%RSP),%R11

  (930) 0x450b04 ADD	%RAX,%R11

  (930) 0x450b07 MOV	0xd8(%RSP),%R8

  (930) 0x450b0f ADD	%RAX,%R8

  (930) 0x450b12 MOV	0xd0(%RSP),%RSI

  (930) 0x450b1a ADD	%RAX,%RSI

  (930) 0x450b1d MOV	0xc8(%RSP),%RAX

  (930) 0x450b25 CMP	$0x3,%RAX

  (930) 0x450b29 LEA	0x1(%RAX),%RAX

  (930) 0x450b2d JE	4510c0

  (930) 0x450b33 VMOVSD	0x2a0(%RSP,%RAX,8),%XMM8

  (930) 0x450b3c VMOVSD	%XMM8,0x120(%RSP)

  (930) 0x450b45 VMOVSD	0x160(%RSP,%RAX,8),%XMM8

  (930) 0x450b4e VMOVSD	%XMM8,0x118(%RSP)

  (930) 0x450b57 MOV	%RAX,0xc8(%RSP)

  (930) 0x450b5f VMOVSD	0x2e0(%RSP,%RAX,8),%XMM8

  (930) 0x450b68 VMOVSD	%XMM8,0x110(%RSP)

  (930) 0x450b71 MOV	%RSI,0xd0(%RSP)

  (930) 0x450b79 MOV	%R8,0xd8(%RSP)

  (930) 0x450b81 MOV	%R8,0x8(%RSP)

  (930) 0x450b86 MOV	%R11,0xe0(%RSP)

  (930) 0x450b8e MOV	%R10,0xe8(%RSP)

  (930) 0x450b96 MOV	%R13,0x108(%RSP)

  (930) 0x450b9e MOV	%R12,0xf8(%RSP)

  (930) 0x450ba6 MOV	%R15,0x100(%RSP)

  (930) 0x450bae MOV	%R15,%R8

  (930) 0x450bb1 MOV	%R12,%R15

  (930) 0x450bb4 MOV	%R8,%R12

  (930) 0x450bb7 MOV	%RDI,0xf0(%RSP)

  (930) 0x450bbf MOV	%RDI,%RAX

  (930) 0x450bc2 MOVQ	$0,0x10(%RSP)

  (930) 0x450bcb JMP	450c47

0x450bcd NOPW	%CS:(%RAX,%RAX,1)

0x450bdc NOPW	%CS:(%RAX,%RAX,1)

0x450beb NOPW	%CS:(%RAX,%RAX,1)

0x450bfa NOPW	(%RAX,%RAX,1)

    (931) 0x450c00 MOV	0x40(%RSP),%RDI

    (931) 0x450c05 MOV	%RAX,%R8

    (931) 0x450c08 MOV	0x28(%RSP),%RAX

    (931) 0x450c0d ADD	%RDI,%RAX

    (931) 0x450c10 ADD	%RDI,%R12

    (931) 0x450c13 ADD	%RDI,%R15

    (931) 0x450c16 MOV	0x20(%RSP),%R13

    (931) 0x450c1b ADD	%RDI,%R13

    (931) 0x450c1e ADD	%RDI,%R10

    (931) 0x450c21 ADD	%RDI,%R11

    (931) 0x450c24 ADD	%RDI,%R8

    (931) 0x450c27 MOV	%R8,0x8(%RSP)

    (931) 0x450c2c ADD	%RDI,%RSI

    (931) 0x450c2f MOV	0x10(%RSP),%RDI

    (931) 0x450c34 CMP	$0x3,%RDI

    (931) 0x450c38 LEA	0x1(%RDI),%RDI

    (931) 0x450c3c MOV	%RDI,0x10(%RSP)

    (931) 0x450c41 JE	450ac0

    (931) 0x450c47 MOV	%RAX,0x28(%RSP)

    (931) 0x450c4c MOV	%R13,0x20(%RSP)

    (931) 0x450c51 CMPL	$0,0x60(%RSP)

    (931) 0x450c56 MOV	0x8(%RSP),%RAX

    (931) 0x450c5b JLE	450c00

    (931) 0x450c5d MOV	0x10(%RSP),%RDI

    (931) 0x450c62 VMOVSD	0x2c0(%RSP,%RDI,8),%XMM8

    (931) 0x450c6b VMULSD	0x120(%RSP),%XMM8,%XMM23

    (931) 0x450c73 VMOVSD	0x118(%RSP),%XMM9

    (931) 0x450c7c VMULSD	%XMM9,%XMM8,%XMM20

    (931) 0x450c82 VMOVSD	0x110(%RSP),%XMM10

    (931) 0x450c8b VMULSD	%XMM10,%XMM8,%XMM24

    (931) 0x450c91 VMOVSD	0x140(%RSP,%RDI,8),%XMM8

    (931) 0x450c9a VMULSD	%XMM9,%XMM8,%XMM29

    (931) 0x450ca0 VMULSD	%XMM10,%XMM8,%XMM30

    (931) 0x450ca6 VMULSD	0x280(%RSP,%RDI,8),%XMM10,%XMM31

    (931) 0x450cae MOV	0x68(%RSP),%R8

    (931) 0x450cb3 TEST	%R8,%R8

    (931) 0x450cb6 JE	450f40

    (931) 0x450cbc MOV	%RSI,0x128(%RSP)

    (931) 0x450cc4 VMOVAPD	%YMM26,%YMM0

    (931) 0x450cca VBROADCASTSD	%XMM23,%YMM26

    (931) 0x450cd0 VMOVAPD	%YMM28,%YMM3

    (931) 0x450cd6 VBROADCASTSD	%XMM29,%YMM28

    (931) 0x450cdc VMOVAPD	%YMM25,%YMM1

    (931) 0x450ce2 VMOVAPD	%YMM18,%YMM25

    (931) 0x450ce8 VMOVAPD	%YMM19,%YMM18

    (931) 0x450cee VBROADCASTSD	%XMM20,%YMM19

    (931) 0x450cf4 VMOVAPD	%YMM27,%YMM2

    (931) 0x450cfa VMOVAPD	%YMM22,%YMM27

    (931) 0x450d00 VBROADCASTSD	%XMM31,%YMM22

    (931) 0x450d06 VBROADCASTSD	%XMM30,%YMM16

    (931) 0x450d0c VBROADCASTSD	%XMM24,%YMM8

    (931) 0x450d12 XOR	%R13D,%R13D

    (931) 0x450d15 MOV	0x18(%RSP),%RDI

    (931) 0x450d1a VMOVUPD	0x380(%RSP),%YMM4

    (931) 0x450d23 VMOVUPD	0x360(%RSP),%YMM5

    (931) 0x450d2c VMOVUPD	0x340(%RSP),%YMM6

    (931) 0x450d35 VMOVUPD	0x320(%RSP),%YMM7

    (931) 0x450d3e MOV	%R12,%RSI

    (931) 0x450d41 MOV	%R15,%R12

    (931) 0x450d44 MOV	0x20(%RSP),%R15

    (931) 0x450d49 MOV	0x28(%RSP),%RAX

    (931) 0x450d4e XCHG	%AX,%AX

      (933) 0x450d50 VMOVUPD	(%R15,%R13,8),%YMM10

      (933) 0x450d56 VMOVUPD	(%R12,%R13,8),%YMM11

      (933) 0x450d5c VMOVUPD	(%RSI,%R13,8),%YMM12

      (933) 0x450d62 VMOVUPD	(%RAX,%R13,8),%YMM13

      (933) 0x450d68 VMULPD	%YMM18,%YMM10,%YMM9

      (933) 0x450d6e VFMADD231PD	%YMM25,%YMM11,%YMM9

      (933) 0x450d74 VFMADD231PD	%YMM27,%YMM12,%YMM9

      (933) 0x450d7a VFMADD231PD	%YMM13,%YMM1,%YMM9

      (933) 0x450d7f VMULPD	%YMM0,%YMM10,%YMM14

      (933) 0x450d83 VMULPD	%YMM2,%YMM11,%YMM15

      (933) 0x450d87 VFMADD231PD	%YMM4,%YMM13,%YMM15

      (933) 0x450d8c VFMADD231PD	%YMM3,%YMM12,%YMM14

      (933) 0x450d91 VFMADD231PD	%YMM15,%YMM17,%YMM14

      (933) 0x450d97 LEA	(%RBX,%R13,8),%R8

      (933) 0x450d9b VMOVUPD	(%RBX,%R13,8),%YMM15

      (933) 0x450da1 VFMADD231PD	%YMM9,%YMM26,%YMM15

      (933) 0x450da7 VMOVUPD	%YMM15,(%RBX,%R13,8)

      (933) 0x450dad VMOVUPD	(%R9,%R8,1),%YMM15

      (933) 0x450db3 VFMADD231PD	%YMM9,%YMM28,%YMM15

      (933) 0x450db9 VMOVUPD	%YMM15,(%R9,%R8,1)

      (933) 0x450dbf VMULPD	%YMM5,%YMM10,%YMM10

      (933) 0x450dc3 LEA	(%R8,%R9,1),%R8

      (933) 0x450dc7 VMOVUPD	(%R9,%R8,1),%YMM15

      (933) 0x450dcd VFMADD231PD	%YMM19,%YMM14,%YMM15

      (933) 0x450dd3 VMOVUPD	%YMM15,(%R9,%R8,1)

      (933) 0x450dd9 VFMADD231PD	%YMM11,%YMM6,%YMM10

      (933) 0x450dde LEA	(%R8,%R9,1),%R8

      (933) 0x450de2 VMOVUPD	(%R9,%R8,1),%YMM11

      (933) 0x450de8 VFMADD231PD	%YMM9,%YMM22,%YMM11

      (933) 0x450dee VMOVUPD	%YMM11,(%R9,%R8,1)

      (933) 0x450df4 VFMADD231PD	%YMM12,%YMM7,%YMM10

      (933) 0x450df9 LEA	(%R8,%R9,1),%R8

      (933) 0x450dfd VMOVUPD	(%R9,%R8,1),%YMM11

      (933) 0x450e03 VFMADD231PD	%YMM16,%YMM14,%YMM11

      (933) 0x450e09 VMOVUPD	%YMM11,(%R9,%R8,1)

      (933) 0x450e0f VFMADD231PD	%YMM13,%YMM17,%YMM10

      (933) 0x450e15 LEA	(%R8,%R9,1),%R8

      (933) 0x450e19 VFMADD213PD	(%R9,%R8,1),%YMM8,%YMM10

      (933) 0x450e1f VMOVUPD	%YMM10,(%R9,%R8,1)

      (933) 0x450e25 MOV	0x68(%RSP),%R8

      (933) 0x450e2a VMOVUPD	(%RDI,%R13,8),%YMM10

      (933) 0x450e30 VFMADD231PD	%YMM19,%YMM9,%YMM10

      (933) 0x450e36 VMOVUPD	%YMM10,(%RDI,%R13,8)

      (933) 0x450e3c VMOVUPD	(%RDX,%R13,8),%YMM10

      (933) 0x450e42 VFMADD231PD	%YMM16,%YMM9,%YMM10

      (933) 0x450e48 VMOVUPD	%YMM10,(%RDX,%R13,8)

      (933) 0x450e4e VFMADD213PD	(%RCX,%R13,8),%YMM8,%YMM14

      (933) 0x450e54 VMOVUPD	%YMM14,(%RCX,%R13,8)

      (933) 0x450e5a VFMADD213PD	(%R14,%R13,8),%YMM8,%YMM9

      (933) 0x450e60 VMOVUPD	%YMM9,(%R14,%R13,8)

      (933) 0x450e66 ADD	$0x4,%R13

      (933) 0x450e6a CMP	%R8,%R13

      (933) 0x450e6d JB	450d50

    (931) 0x450e73 MOV	%R8,%R13

    (931) 0x450e76 MOV	%R8,%RAX

    (931) 0x450e79 MOV	0x30(%RSP),%R8

    (931) 0x450e7e CMP	%R8D,%EAX

    (931) 0x450e81 VMOVUPD	0x130(%RSP),%XMM15

    (931) 0x450e8a VMOVUPD	0x300(%RSP),%YMM16

    (931) 0x450e92 VMOVAPD	%YMM18,%YMM19

    (931) 0x450e98 VMOVAPD	%YMM25,%YMM18

    (931) 0x450e9e VMOVAPD	%YMM27,%YMM22

    (931) 0x450ea4 VMOVAPD	%YMM1,%YMM25

    (931) 0x450eaa VMOVUPD	0x270(%RSP),%XMM1

    (931) 0x450eb3 VMOVAPD	%YMM0,%YMM26

    (931) 0x450eb9 VMOVUPD	0x260(%RSP),%XMM0

    (931) 0x450ec2 VMOVAPD	%YMM2,%YMM27

    (931) 0x450ec8 VMOVUPD	0x250(%RSP),%XMM2

    (931) 0x450ed1 VMOVAPD	%YMM3,%YMM28

    (931) 0x450ed7 VMOVUPD	0x240(%RSP),%XMM3

    (931) 0x450ee0 VMOVUPD	0x230(%RSP),%XMM4

    (931) 0x450ee9 VMOVUPD	0x220(%RSP),%XMM5

    (931) 0x450ef2 VMOVUPD	0x210(%RSP),%XMM6

    (931) 0x450efb VMOVUPD	0x200(%RSP),%XMM7

    (931) 0x450f04 MOV	%R12,%R15

    (931) 0x450f07 MOV	%RSI,%R12

    (931) 0x450f0a MOV	0x128(%RSP),%RSI

    (931) 0x450f12 MOV	0x8(%RSP),%RAX

    (931) 0x450f17 JNE	450f50

    (931) 0x450f19 JMP	450c00

0x450f1e NOPW	%CS:(%RAX,%RAX,1)

0x450f2d NOPW	%CS:(%RAX,%RAX,1)

0x450f3c NOPL	(%RAX)

    (931) 0x450f40 XOR	%R13D,%R13D

    (931) 0x450f43 MOV	0x18(%RSP),%RDI

    (931) 0x450f48 NOPL	(%RAX,%RAX,1)

      (932) 0x450f50 VMOVSD	(%RSI,%R13,8),%XMM8

      (932) 0x450f56 VMOVSD	(%RAX,%R13,8),%XMM9

      (932) 0x450f5c VMOVSD	(%R11,%R13,8),%XMM10

      (932) 0x450f62 VMOVSD	(%R10,%R13,8),%XMM11

      (932) 0x450f68 VPUNPCKLQDQ	%XMM10,%XMM9,%XMM12

      (932) 0x450f6d VMULPD	%XMM16,%XMM12,%XMM12

      (932) 0x450f73 VMOVAPD	%XMM0,%XMM13

      (932) 0x450f77 VFMADD213SD	%XMM12,%XMM8,%XMM13

      (932) 0x450f7c VSHUFPD	$0x1,%XMM12,%XMM12,%XMM12

      (932) 0x450f82 VADDSD	%XMM12,%XMM13,%XMM12

      (932) 0x450f87 VFMADD231SD	%XMM11,%XMM7,%XMM12

      (932) 0x450f8c VMULSD	%XMM1,%XMM8,%XMM13

      (932) 0x450f90 VMULSD	%XMM2,%XMM9,%XMM14

      (932) 0x450f94 VFMADD231SD	%XMM15,%XMM11,%XMM14

      (932) 0x450f99 VFMADD231SD	%XMM3,%XMM10,%XMM13

      (932) 0x450f9e VFMADD231SD	%XMM14,%XMM21,%XMM13

      (932) 0x450fa4 LEA	(%RBX,%R13,8),%R8

      (932) 0x450fa8 VMOVSD	(%RBX,%R13,8),%XMM14

      (932) 0x450fae VFMADD231SD	%XMM12,%XMM23,%XMM14

      (932) 0x450fb4 VMOVSD	%XMM14,(%RBX,%R13,8)

      (932) 0x450fba VMOVSD	(%R9,%R8,1),%XMM14

      (932) 0x450fc0 VFMADD231SD	%XMM12,%XMM29,%XMM14

      (932) 0x450fc6 VMOVSD	%XMM14,(%R9,%R8,1)

      (932) 0x450fcc VMULSD	%XMM4,%XMM8,%XMM8

      (932) 0x450fd0 LEA	(%R8,%R9,1),%R8

      (932) 0x450fd4 VMOVSD	(%R9,%R8,1),%XMM14

      (932) 0x450fda VFMADD231SD	%XMM20,%XMM13,%XMM14

      (932) 0x450fe0 VMOVSD	%XMM14,(%R9,%R8,1)

      (932) 0x450fe6 VFMADD231SD	%XMM9,%XMM5,%XMM8

      (932) 0x450feb LEA	(%R8,%R9,1),%R8

      (932) 0x450fef VMOVSD	(%R9,%R8,1),%XMM9

      (932) 0x450ff5 VFMADD231SD	%XMM12,%XMM31,%XMM9

      (932) 0x450ffb VMOVSD	%XMM9,(%R9,%R8,1)

      (932) 0x451001 VFMADD231SD	%XMM10,%XMM6,%XMM8

      (932) 0x451006 LEA	(%R8,%R9,1),%R8

      (932) 0x45100a VMOVSD	(%R9,%R8,1),%XMM9

      (932) 0x451010 VFMADD231SD	%XMM30,%XMM13,%XMM9

      (932) 0x451016 VMOVSD	%XMM9,(%R9,%R8,1)

      (932) 0x45101c VFMADD231SD	%XMM11,%XMM21,%XMM8

      (932) 0x451022 LEA	(%R8,%R9,1),%R8

      (932) 0x451026 VFMADD213SD	(%R9,%R8,1),%XMM24,%XMM8

      (932) 0x45102d VMOVSD	%XMM8,(%R9,%R8,1)

      (932) 0x451033 VMOVSD	(%RDI,%R13,8),%XMM8

      (932) 0x451039 VFMADD231SD	%XMM20,%XMM12,%XMM8

      (932) 0x45103f VMOVSD	%XMM8,(%RDI,%R13,8)

      (932) 0x451045 VMOVSD	(%RDX,%R13,8),%XMM8

      (932) 0x45104b VFMADD231SD	%XMM30,%XMM12,%XMM8

      (932) 0x451051 VMOVSD	%XMM8,(%RDX,%R13,8)

      (932) 0x451057 VFMADD213SD	(%RCX,%R13,8),%XMM24,%XMM13

      (932) 0x45105e VMOVSD	%XMM13,(%RCX,%R13,8)

      (932) 0x451064 VFMADD213SD	(%R14,%R13,8),%XMM24,%XMM12

      (932) 0x45106b VMOVSD	%XMM12,(%R14,%R13,8)

      (932) 0x451071 INC	%R13

      (932) 0x451074 MOV	0x30(%RSP),%R8

      (932) 0x451079 CMP	%R13,%R8

      (932) 0x45107c JNE	450f50

    (931) 0x451082 JMP	450c00

0x451087 NOPW	%CS:(%RAX,%RAX,1)

0x451096 NOPW	%CS:(%RAX,%RAX,1)

0x4510a5 NOPW	%CS:(%RAX,%RAX,1)

0x4510b4 NOPW	%CS:(%RAX,%RAX,1)

(927) 0x4510c0 MOV	0x60(%RSP),%R11

(927) 0x4510c5 TEST	%R11D,%R11D

(927) 0x4510c8 MOV	0xa8(%RSP),%R13

(927) 0x4510d0 MOV	0x58(%RSP),%R14

(927) 0x4510d5 MOV	0x78(%RSP),%R10

(927) 0x4510da VMOVSD	0xe8d4c(%RIP),%XMM16

(927) 0x4510e4 VMOVSD	0xe5f32(%RIP),%XMM22

(927) 0x4510ee VMOVSD	0xe5f40(%RIP),%XMM23

(927) 0x4510f8 VMOVSD	0xe5f3e(%RIP),%XMM24

(927) 0x451102 VMOVSD	0xe8d34(%RIP),%XMM26

(927) 0x45110c VMOVSD	0xe5f6a(%RIP),%XMM27

(927) 0x451116 VMOVSD	0xe70d8(%RIP),%XMM28

(927) 0x451120 MOV	0x18(%RSP),%R15

(927) 0x451125 VMOVUPD	0x1f0(%RSP),%XMM17

(927) 0x45112d VMOVUPD	0x1e0(%RSP),%XMM18

(927) 0x451135 VMOVUPD	0x1d0(%RSP),%XMM19

(927) 0x45113d MOV	0x50(%RSP),%R12

(927) 0x451142 JE	450380

(927) 0x451148 VMULSD	%XMM17,%XMM17,%XMM0

(927) 0x45114e VMULSD	%XMM18,%XMM18,%XMM1

(927) 0x451154 VMULSD	%XMM19,%XMM19,%XMM2

(927) 0x45115a VMULSD	%XMM17,%XMM18,%XMM3

(927) 0x451160 VMULSD	%XMM17,%XMM19,%XMM4

(927) 0x451166 VMULSD	%XMM18,%XMM19,%XMM5

(927) 0x45116c TEST	%R10,%R10

(927) 0x45116f JE	451280

(927) 0x451175 VBROADCASTSD	%XMM17,%YMM6

(927) 0x45117b VBROADCASTSD	%XMM18,%YMM7

(927) 0x451181 VBROADCASTSD	%XMM19,%YMM8

(927) 0x451187 VBROADCASTSD	%XMM0,%YMM9

(927) 0x45118c VBROADCASTSD	%XMM1,%YMM10

(927) 0x451191 VBROADCASTSD	%XMM2,%YMM11

(927) 0x451196 VBROADCASTSD	%XMM3,%YMM12

(927) 0x45119b VBROADCASTSD	%XMM4,%YMM13

(927) 0x4511a0 VBROADCASTSD	%XMM5,%YMM14

(927) 0x4511a5 MOV	(%RSP),%R9

(927) 0x4511a9 MOV	%R9,%RAX

(927) 0x4511ac SAL	$0x5,%RAX

(927) 0x4511b0 ADD	%RBX,%RAX

(927) 0x4511b3 LEA	(%R9,%R9,4),%RSI

(927) 0x4511b7 LEA	(%RBX,%RSI,8),%RSI

(927) 0x4511bb LEA	(%R9,%R9,2),%RDI

(927) 0x4511bf LEA	(%RBX,%RDI,8),%RDI

(927) 0x4511c3 LEA	(%RBX,%R12,1),%R8

(927) 0x4511c7 LEA	(%RBX,%R9,8),%R9

(927) 0x4511cb MOV	%R10,%R12

(927) 0x4511ce XOR	%R10D,%R10D

(927) 0x4511d1 NOPW	%CS:(%RAX,%RAX,1)

  (929) 0x4511e0 VMULPD	(%R15,%R10,8),%YMM6,%YMM15

  (929) 0x4511e6 VMOVUPD	%YMM15,(%R15,%R10,8)

  (929) 0x4511ec VMULPD	(%RDX,%R10,8),%YMM7,%YMM15

  (929) 0x4511f2 VMOVUPD	%YMM15,(%RDX,%R10,8)

  (929) 0x4511f8 VMULPD	(%RCX,%R10,8),%YMM8,%YMM15

  (929) 0x4511fe VMOVUPD	%YMM15,(%RCX,%R10,8)

  (929) 0x451204 VMULPD	(%RBX,%R10,8),%YMM9,%YMM15

  (929) 0x45120a VMOVUPD	%YMM15,(%RBX,%R10,8)

  (929) 0x451210 VMULPD	(%RDI,%R10,8),%YMM10,%YMM15

  (929) 0x451216 VMOVUPD	%YMM15,(%RDI,%R10,8)

  (929) 0x45121c VMULPD	(%RSI,%R10,8),%YMM11,%YMM15

  (929) 0x451222 VMOVUPD	%YMM15,(%RSI,%R10,8)

  (929) 0x451228 VMULPD	(%R9,%R10,8),%YMM12,%YMM15

  (929) 0x45122e VMOVUPD	%YMM15,(%R9,%R10,8)

  (929) 0x451234 VMULPD	(%R8,%R10,8),%YMM13,%YMM15

  (929) 0x45123a VMOVUPD	%YMM15,(%R8,%R10,8)

  (929) 0x451240 VMULPD	(%RAX,%R10,8),%YMM14,%YMM15

  (929) 0x451246 VMOVUPD	%YMM15,(%RAX,%R10,8)

  (929) 0x45124c ADD	$0x4,%R10

  (929) 0x451250 CMP	%R12,%R10

  (929) 0x451253 JL	4511e0

(927) 0x451255 MOV	%R12,%RAX

(927) 0x451258 CMP	%R11,%R12

(927) 0x45125b MOV	0x50(%RSP),%R12

(927) 0x451260 JE	450380

(927) 0x451266 JMP	451282

0x451268 NOPW	%CS:(%RAX,%RAX,1)

0x451277 NOPW	(%RAX,%RAX,1)

(927) 0x451280 XOR	%EAX,%EAX

(927) 0x451282 MOV	(%RSP),%R9

(927) 0x451286 MOV	%R9,%RSI

(927) 0x451289 SAL	$0x5,%RSI

(927) 0x45128d ADD	%RBX,%RSI

(927) 0x451290 LEA	(%R9,%R9,4),%RDI

(927) 0x451294 LEA	(%RBX,%RDI,8),%RDI

(927) 0x451298 LEA	(%R9,%R9,2),%R8

(927) 0x45129c LEA	(%RBX,%R8,8),%R8

(927) 0x4512a0 ADD	%RBX,%R12

(927) 0x4512a3 LEA	(%RBX,%R9,8),%R9

(927) 0x4512a7 NOPW	(%RAX,%RAX,1)

  (928) 0x4512b0 VMULSD	(%R15,%RAX,8),%XMM17,%XMM6

  (928) 0x4512b7 VMOVSD	%XMM6,(%R15,%RAX,8)

  (928) 0x4512bd VMULSD	(%RDX,%RAX,8),%XMM18,%XMM6

  (928) 0x4512c4 VMOVSD	%XMM6,(%RDX,%RAX,8)

  (928) 0x4512c9 VMULSD	(%RCX,%RAX,8),%XMM19,%XMM6

  (928) 0x4512d0 VMOVSD	%XMM6,(%RCX,%RAX,8)

  (928) 0x4512d5 VMULSD	(%RBX,%RAX,8),%XMM0,%XMM6

  (928) 0x4512da VMOVSD	%XMM6,(%RBX,%RAX,8)

  (928) 0x4512df VMULSD	(%R8,%RAX,8),%XMM1,%XMM6

  (928) 0x4512e5 VMOVSD	%XMM6,(%R8,%RAX,8)

  (928) 0x4512eb VMULSD	(%RDI,%RAX,8),%XMM2,%XMM6

  (928) 0x4512f0 VMOVSD	%XMM6,(%RDI,%RAX,8)

  (928) 0x4512f5 VMULSD	(%R9,%RAX,8),%XMM3,%XMM6

  (928) 0x4512fb VMOVSD	%XMM6,(%R9,%RAX,8)

  (928) 0x451301 VMULSD	(%R12,%RAX,8),%XMM4,%XMM6

  (928) 0x451307 VMOVSD	%XMM6,(%R12,%RAX,8)

  (928) 0x45130d VMULSD	(%RSI,%RAX,8),%XMM5,%XMM6

  (928) 0x451312 VMOVSD	%XMM6,(%RSI,%RAX,8)

  (928) 0x451317 INC	%RAX

  (928) 0x45131a CMP	%RAX,%R11

  (928) 0x45131d JNE	4512b0

(927) 0x45131f JMP	450380

0x451324 NOPW	%CS:(%RAX,%RAX,1)

0x451333 NOPW	%CS:(%RAX,%RAX,1)

0x451340 MOV	0x70(%RSP),%RDI

0x451345 VZEROUPPER

0x451348 CALL	4b63c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>

0x45134d MOV	0x30(%R14),%ESI

0x451351 TEST	%ESI,%ESI

0x451353 JLE	451480

0x451359 MOV	0x8(%R14),%ECX

0x45135d MOV	0x40(%R14),%EDX

0x451361 XOR	%EAX,%EAX

0x451363 JMP	45138c

0x451365 NOPW	%CS:(%RAX,%RAX,1)

0x451374 NOPW	%CS:(%RAX,%RAX,1)

(925) 0x451380 MOVSXD	%ESI,%RDI

(925) 0x451383 CMP	%RDI,%RAX

(925) 0x451386 JGE	451480

(925) 0x45138c MOV	%RAX,%R10

(925) 0x45138f MOV	%R10D,%EDI

(925) 0x451392 IMUL	%ESI,%EDI

(925) 0x451395 INC	%RAX

(925) 0x451398 MOV	%EDX,%R8D

(925) 0x45139b IMUL	%EAX,%R8D

(925) 0x45139f CMP	%R8D,%ECX

(925) 0x4513a2 CMOVL	%ECX,%R8D

(925) 0x4513a6 CMP	%R8D,%EDI

(925) 0x4513a9 JGE	451380

(925) 0x4513ab MOVSXD	%EDI,%RSI

(925) 0x4513ae LEA	(,%RSI,8),%RDI

(925) 0x4513b6 LEA	0x2(%RSI,%RSI,2),%R8

(925) 0x4513bb LEA	(%R10,%R10,2),%R9

(925) 0x4513bf SAL	$0x3,%R10

(925) 0x4513c3 LEA	(%R10,%R10,4),%R10

(925) 0x4513c7 XOR	%R11D,%R11D

(925) 0x4513ca NOPW	(%RAX,%RAX,1)

  (926) 0x4513d0 MOV	0x310(%R14),%RCX

  (926) 0x4513d7 MOV	(%RCX,%R9,8),%RCX

  (926) 0x4513db MOV	0x18(%R13),%RDX

  (926) 0x4513df ADD	%RDI,%RDX

  (926) 0x4513e2 VMOVSD	(%RCX,%R11,8),%XMM0

  (926) 0x4513e8 VMOVSD	%XMM0,(%RDX,%R11,8)

  (926) 0x4513ee MOV	0x328(%R14),%RCX

  (926) 0x4513f5 MOV	0x18(%RCX,%R10,1),%RDX

  (926) 0x4513fa MOVSXD	0x8(%RCX,%R10,1),%RCX

  (926) 0x4513ff LEA	(%R11,%RCX,1),%RBX

  (926) 0x451403 VMOVSD	(%RDX,%R11,8),%XMM0

  (926) 0x451409 VMOVHPS	(%RDX,%RBX,8),%XMM0,%XMM0

  (926) 0x45140e LEA	(%R11,%RCX,2),%RCX

  (926) 0x451412 VMOVSD	(%RDX,%RCX,8),%XMM1

  (926) 0x451417 MOV	0x18(%R12),%RCX

  (926) 0x45141c VMOVUPS	%XMM0,-0x10(%RCX,%R8,8)

  (926) 0x451423 VMOVSD	%XMM1,(%RCX,%R8,8)

  (926) 0x451429 MOV	0x340(%R14),%RCX

  (926) 0x451430 MOV	0x18(%RCX,%R10,1),%RCX

  (926) 0x451435 VMOVSD	(%RCX,%R11,8),%XMM0

  (926) 0x45143b MOV	0x18(%R15),%RCX

  (926) 0x45143f ADD	%RDI,%RCX

  (926) 0x451442 VMOVSD	%XMM0,(%RCX,%R11,8)

  (926) 0x451448 MOV	0x8(%R14),%ECX

  (926) 0x45144c MOV	0x40(%R14),%EDX

  (926) 0x451450 MOV	%EDX,%EBX

  (926) 0x451452 IMUL	%EAX,%EBX

  (926) 0x451455 CMP	%EBX,%ECX

  (926) 0x451457 CMOVL	%ECX,%EBX

  (926) 0x45145a MOVSXD	%EBX,%RBX

  (926) 0x45145d ADD	$0x3,%R8

  (926) 0x451461 LEA	0x1(%RSI,%R11,1),%R14

  (926) 0x451466 INC	%R11

  (926) 0x451469 CMP	%RBX,%R14

  (926) 0x45146c MOV	0x58(%RSP),%R14

  (926) 0x451471 JL	4513d0

(925) 0x451477 MOV	0x30(%R14),%ESI

(925) 0x45147b JMP	451380

0x451480 LEA	-0x28(%RBP),%RSP

0x451484 POP	%RBX

0x451485 POP	%R12

0x451487 POP	%R13

0x451489 POP	%R14

0x45148b POP	%R15

0x45148d POP	%RBP

0x45148e RET

0x45148f NOPW	%CS:(%RAX,%RAX,1)

0x45149e NOPW	%CS:(%RAX,%RAX,1)

0x4514ad NOPW	%CS:(%RAX,%RAX,1)

0x4514bc NOPL	(%RAX)

0x4514c0 MOV	%RAX,%RDI

0x4514c3 CALL	410460 <__clang_call_terminate>

0x4514c8 NOPW	%CS:(%RAX,%RAX,1)

0x4514d2 NOPW	%CS:(%RAX,%RAX,1)

0x4514dc NOPW	%CS:(%RAX,%RAX,1)

0x4514e6 NOPW	%CS:(%RAX,%RAX,1)

0x4514f0 NOPW	%CS:(%RAX,%RAX,1)

0x4514fa NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►84.29+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►8.00+	qmcplusplus::SPOSet::evaluate_[...]	OhmmsVector.h:144	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:263	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:238	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:171	exec
○	main.extracted.112	miniqmc.cpp:397	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►7.68+	qmcplusplus::SPOSet::evaluate_[...]	OhmmsVector.h:144	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:263	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:238	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:170	exec
○	main.extracted.112	miniqmc.cpp:397	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run icx_4

Source file and lines	einspline_spo_ref.hpp:203-230
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231,265,271
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h:150-152
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:203-208,216-230
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046,1169
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:235,923-924
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:61,145
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:45-47
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:143
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:68-79
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:187-192,198-202,226-262,269-286

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 27.83 to 10.33 cycles (2.69x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 27.83 to 2.53 cycles (10.99x speedup).

Details

12% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
22% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
17% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__clang_call_terminate: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249
qmcplusplus::TimerType
::start(): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242
qmcplusplus::TimerType
::stop(): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DEC: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:923
VROUNDSD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249

Type of elements and instruction set

21 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 18 FP arithmetical operations:

9: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 268 bytes (33 double precision FP elements). The binary function is storing 212 bytes (26 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	158
nb uops	167
loop length	1061
used x86 registers	16
used mmx registers	0
used xmm registers	14
used ymm registers	0
used zmm registers	0
nb stack references	21
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	27.83 cycles
front end	27.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.50	10.50	14.67	14.67	15.50	10.50	6.70	15.50	15.50	15.50	6.80	14.67
cycles	10.50	10.50	14.67	14.67	15.50	10.50	6.70	15.50	15.50	15.50	6.80	14.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	27.83
Dispatch	15.50
Overall L1	27.83

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	18%
load	0%
store	100%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

INT+FP

all	12%
load	0%
store	22%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Vector efficiency ratios

INT

all	11%
load	8%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	14%
load	12%
store	25%
mul	12%
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	13%
load	11%
store	15%
mul	12%
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 27.83 cycles. At this rate:

5% of peak load performance is reached (9.63 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.62 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 27.83 to 15.50 cycles (1.80x speedup).

ASM code

In the binary file, the address of the function is: 450100

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x20,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x3c0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %EDX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x358(%RDI),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4b6140 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOVSXD 0x30(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RAX,%RAX,2),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
ADD 0x40(%R14),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
CMP %EAX,0x124(%R14)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
LEA 0x128(%R14),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVNE %RCX,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOVSXD 0x30(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %RCX,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %RBX,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JLE 451340 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x1240>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RAX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD 0xd8(%R14),%XMM0,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x8(%RAX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD231SD 0xf0(%R14),%XMM2,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x10(%RAX),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD231SD 0x108(%R14),%XMM3,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMULSD 0xe0(%R14),%XMM0,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0xf8(%R14),%XMM2,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0x110(%R14),%XMM3,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMULSD 0xe8(%R14),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0x100(%R14),%XMM2,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0x118(%R14),%XMM3,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VROUNDSD $0x9,%XMM1,%XMM1,%XMM2	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VSUBSD %XMM2,%XMM1,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCMPSD $0x1,%XMM2,%XMM1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM6,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD %XMM2,%XMM3,%XMM3{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VMOVSD 0xe9c29(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCMPSD $0x1,%XMM1,%XMM5,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM3,%XMM6,%XMM6{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VMOVUPD %XMM6,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VROUNDSD $0x9,%XMM4,%XMM4,%XMM1	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VSUBSD %XMM1,%XMM4,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VCMPSD $0x1,%XMM2,%XMM4,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM6,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD %XMM2,%XMM1,%XMM1{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VCMPSD $0x1,%XMM4,%XMM5,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VROUNDSD $0x9,%XMM0,%XMM0,%XMM3	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VMOVSD %XMM1,%XMM6,%XMM6{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VMOVUPD %XMM6,0x1b0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VSUBSD %XMM3,%XMM0,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VCMPSD $0x1,%XMM2,%XMM0,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD %XMM2,%XMM1,%XMM1{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VCMPSD $0x1,%XMM0,%XMM5,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM1,%XMM3,%XMM3{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VMOVUPD %XMM3,0x1a0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x2f8(%R14),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x310(%R14),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x328(%R14),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x90(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x340(%R14),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x88(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD 0x40(%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R11,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
DECQ 0x48(%RSP)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV %R11D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7fffffff,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RAX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7ffffffc,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RAX,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x4,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVSD 0xe9b37(%RIP),%XMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe6d1d(%RIP),%XMM22	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVDDUP 0xe6d15(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPS %XMM0,0x190(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD 0xe6d1a(%RIP),%XMM23	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe6d18(%RIP),%XMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe9b0e(%RIP),%XMM26	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe6d44(%RIP),%XMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe7eb2(%RIP),%XMM28	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVDDUP 0xe6d32(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD %XMM0,0x180(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %R15,0xb8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,0xb0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,0xa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 4503a7 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x2a7>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x70(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4b63c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x30(%R14),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %ESI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JLE 451480 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x1380>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x8(%R14),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x40(%R14),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 45138c <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x128c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 410460 <__clang_call_terminate>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run icx_4

Source file and lines	einspline_spo_ref.hpp:203-230
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231,265,271
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h:150-152
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:203-208,216-230
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046,1169
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:235,923-924
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:61,145
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:45-47
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:143
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:68-79
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:187-192,198-202,226-262,269-286

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

12% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
22% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
17% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

CALL instructions

Detected function call instructions.

Details

__clang_call_terminate: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249
qmcplusplus::TimerType
::start(): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242
qmcplusplus::TimerType
::stop(): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DEC: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:923
VROUNDSD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249

Type of elements and instruction set

21 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 18 FP arithmetical operations:

9: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 268 bytes (33 double precision FP elements). The binary function is storing 212 bytes (26 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	158
nb uops	167
loop length	1061
used x86 registers	16
used mmx registers	0
used xmm registers	14
used ymm registers	0
used zmm registers	0
nb stack references	21
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	27.83 cycles
front end	27.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.50	10.50	14.67	14.67	15.50	10.50	6.70	15.50	15.50	15.50	6.80	14.67
cycles	10.50	10.50	14.67	14.67	15.50	10.50	6.70	15.50	15.50	15.50	6.80	14.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	27.83
Dispatch	15.50
Overall L1	27.83

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	18%
load	0%
store	100%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

INT+FP

all	12%
load	0%
store	22%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Vector efficiency ratios

INT

all	11%
load	8%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	14%
load	12%
store	25%
mul	12%
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	13%
load	11%
store	15%
mul	12%
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 27.83 cycles. At this rate:

5% of peak load performance is reached (9.63 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.62 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 450100

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x20,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x3c0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %EDX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x358(%RDI),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4b6140 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOVSXD 0x30(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RAX,%RAX,2),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
ADD 0x40(%R14),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
CMP %EAX,0x124(%R14)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
LEA 0x128(%R14),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVNE %RCX,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOVSXD 0x30(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %RCX,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %RBX,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JLE 451340 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x1240>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RAX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD 0xd8(%R14),%XMM0,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x8(%RAX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD231SD 0xf0(%R14),%XMM2,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x10(%RAX),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD231SD 0x108(%R14),%XMM3,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMULSD 0xe0(%R14),%XMM0,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0xf8(%R14),%XMM2,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0x110(%R14),%XMM3,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMULSD 0xe8(%R14),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0x100(%R14),%XMM2,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0x118(%R14),%XMM3,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VROUNDSD $0x9,%XMM1,%XMM1,%XMM2	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VSUBSD %XMM2,%XMM1,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCMPSD $0x1,%XMM2,%XMM1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM6,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD %XMM2,%XMM3,%XMM3{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VMOVSD 0xe9c29(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCMPSD $0x1,%XMM1,%XMM5,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM3,%XMM6,%XMM6{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VMOVUPD %XMM6,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VROUNDSD $0x9,%XMM4,%XMM4,%XMM1	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VSUBSD %XMM1,%XMM4,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VCMPSD $0x1,%XMM2,%XMM4,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM6,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD %XMM2,%XMM1,%XMM1{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VCMPSD $0x1,%XMM4,%XMM5,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VROUNDSD $0x9,%XMM0,%XMM0,%XMM3	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VMOVSD %XMM1,%XMM6,%XMM6{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VMOVUPD %XMM6,0x1b0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VSUBSD %XMM3,%XMM0,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VCMPSD $0x1,%XMM2,%XMM0,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD %XMM2,%XMM1,%XMM1{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VCMPSD $0x1,%XMM0,%XMM5,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM1,%XMM3,%XMM3{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VMOVUPD %XMM3,0x1a0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x2f8(%R14),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x310(%R14),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x328(%R14),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x90(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x340(%R14),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x88(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD 0x40(%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R11,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
DECQ 0x48(%RSP)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV %R11D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7fffffff,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RAX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7ffffffc,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RAX,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x4,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVSD 0xe9b37(%RIP),%XMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe6d1d(%RIP),%XMM22	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVDDUP 0xe6d15(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPS %XMM0,0x190(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD 0xe6d1a(%RIP),%XMM23	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe6d18(%RIP),%XMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe9b0e(%RIP),%XMM26	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe6d44(%RIP),%XMM27	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe7eb2(%RIP),%XMM28	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVDDUP 0xe6d32(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD %XMM0,0x180(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %R15,0xb8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,0xb0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,0xa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 4503a7 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x2a7>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x70(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4b63c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x30(%R14),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %ESI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JLE 451480 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x1380>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x8(%R14),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x40(%R14),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 45138c <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x128c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 410460 <__clang_call_terminate>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator >...–	11.09	9.49
▼Loop 927 - MultiBsplineRef.hpp:187-286 - exec–	0.01	0.01
○Loop 929 - MultiBsplineRef.hpp:276-286 - exec	0.20	0.17
▼Loop 930 - MultiBsplineRef.hpp:226-262 - exec–	0.00	0.01
▼Loop 931 - MultiBsplineRef.hpp:227-262 - exec–	0.00	0.01
○Loop 933 - MultiBsplineRef.hpp:242-262 - exec	10.24	8.65
○Loop 932 - MultiBsplineRef.hpp:242-262 - exec	0.00	0.00
○Loop 928 - MultiBsplineRef.hpp:276-286 - exec	0.00	0.00
▼Loop 925 - einspline_spo_ref.hpp:219-227 - exec–	0.00	0.01
○Loop 926 - einspline_spo_ref.hpp:223-227 - exec	0.63	0.53

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