OV - exec - Function miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector<double, std::allocator<double> >&)

	Function: miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int ...	Module: exec	Source: einspline_spo_ref.hpp:172-189 [...]	Coverage (incl. loops): 19.93% \| (excl. loops): 0.01%

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h: 150 - 152

--------------------------------------------------------------------------------

150:     return TinyVector<Type_t, 3>(lhs[0] * rhs[0] + lhs[1] * rhs[3] + lhs[2] * rhs[6],

151:                                  lhs[0] * rhs[1] + lhs[1] * rhs[4] + lhs[2] * rhs[7],

152:                                  lhs[0] * rhs[2] + lhs[1] * rhs[5] + lhs[2] * rhs[8]);

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 172 - 189

--------------------------------------------------------------------------------

172:     ScopedTimer local_timer(timer);

173:

174:     auto u = Lattice.toUnit_floor(P.activeR(iat));

175:     for (int i = 0; i < nBlocks; ++i)

176:       MultiBsplineEvalRef::evaluate_v(einsplines[i], u[0], u[1], u[2], psi[i].data(), nSplinesPerBlock);

177:   }

178:

179:   inline void evaluate(const ParticleSet& P, int iat, ValueVector_t& psi_v)

180:   {

181:     evaluate_v(P, iat);

182:

183:     for (int i = 0; i < nBlocks; ++i)

184:     {

185:       // in real simulation, phase needs to be applied. Here just fake computation

186:       const int first = i * nBlocks;

187:       std::copy_n(psi[i].data(), std::min((i + 1) * nSplinesPerBlock, OrbitalSetSize) - first, psi_v.data() + first);

188:     }

189:   }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 1046 - 1169

--------------------------------------------------------------------------------

1046: 	return *(this->_M_impl._M_start + __n);

[...]

1169:       { return _M_data_ptr(this->_M_impl._M_start); }

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h: 170 - 170

--------------------------------------------------------------------------------

170:       if (-std::numeric_limits<T1>::epsilon() < val_dot[i] && val_dot[i] < 0)

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h: 235 - 924

--------------------------------------------------------------------------------

235:       if (__b < __a)

[...]

429: 	  const ptrdiff_t _Num = __last - __first;

430: 	  if (_Num)

431: 	    __builtin_memmove(__result, __first, sizeof(_Tp) * _Num);

[...]

923:       for (; __first != __last; ++__first)

924: 	*__first = __tmp;

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 61 - 61

--------------------------------------------------------------------------------

61:     for (size_t d = 0; d < D; ++d)

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algo.h: 725 - 751

--------------------------------------------------------------------------------

725:     { return std::copy(__first, __first + __n, __result); }

[...]

751:       if (__n2 <= 0)

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp: 45 - 47

--------------------------------------------------------------------------------

45:   T sf = std::floor(x);

46:   T dx2 = x - sf;

47:   int ind2 = std::min(std::max(0, static_cast<int>(sf)), nmax);

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 143 - 143

--------------------------------------------------------------------------------

143:     return (active_ptcl_ == iat) ? active_pos_ : R[iat];

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp: 54 - 57

--------------------------------------------------------------------------------

54:     a[0] = ((A00 * tx + A01) * tx + A02) * tx + A03;

55:     a[1] = ((A10 * tx + A11) * tx + A12) * tx + A13;

56:     a[2] = ((A20 * tx + A21) * tx + A22) * tx + A23;

57:     a[3] = ((A30 * tx + A31) * tx + A32) * tx + A33;

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 42 - 71

--------------------------------------------------------------------------------

42:   x -= spline_m->x_grid.start;

43:   y -= spline_m->y_grid.start;

44:   z -= spline_m->z_grid.start;

45:   T tx, ty, tz;

46:   int ix, iy, iz;

47:   spline2::getSplineBound(x * spline_m->x_grid.delta_inv, tx, ix, spline_m->x_grid.num - 1);

48:   spline2::getSplineBound(y * spline_m->y_grid.delta_inv, ty, iy, spline_m->y_grid.num - 1);

49:   spline2::getSplineBound(z * spline_m->z_grid.delta_inv, tz, iz, spline_m->z_grid.num - 1);

[...]

56:   const intptr_t xs = spline_m->x_stride;

57:   const intptr_t ys = spline_m->y_stride;

58:   const intptr_t zs = spline_m->z_stride;

59:

60:   constexpr T zero(0);

61:   std::fill(vals, vals + num_splines, zero);

62:

63:   for (size_t i = 0; i < 4; i++)

64:     for (size_t j = 0; j < 4; j++)

65:     {

66:       const T pre00           = a[i] * b[j];

67:       const T* restrict coefs = spline_m->coefs + (ix + i) * xs + (iy + j) * ys + iz * zs;

68:       for (size_t n = 0; n < num_splines; n++)

69:         vals[n] += pre00 *

70:             (c[0] * coefs[n] + c[1] * coefs[n + zs] + c[2] * coefs[n + 2 * zs] +

71:              c[3] * coefs[n + 3 * zs]);

0x44f140 PUSH	%RBP

0x44f141 MOV	%RSP,%RBP

0x44f144 PUSH	%R15

0x44f146 PUSH	%R14

0x44f148 PUSH	%R13

0x44f14a PUSH	%R12

0x44f14c PUSH	%RBX

0x44f14d SUB	$0xf8,%RSP

0x44f154 MOV	%RCX,-0x108(%RBP)

0x44f15b MOV	%EDX,%R12D

0x44f15e MOV	%RSI,%R13

0x44f161 MOV	%RDI,%RBX

0x44f164 MOV	0x358(%RDI),%RDI

0x44f16b MOV	%RDI,-0x110(%RBP)

0x44f172 CALL	4b6140 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>

0x44f177 MOVSXD	%R12D,%RAX

0x44f17a LEA	(%RAX,%RAX,2),%RCX

0x44f17e SAL	$0x3,%RCX

0x44f182 ADD	0x40(%R13),%RCX

0x44f186 CMP	%EAX,0x124(%R13)

0x44f18d LEA	0x128(%R13),%RAX

0x44f194 CMOVNE	%RCX,%RAX

0x44f198 MOV	%RBX,-0xa8(%RBP)

0x44f19f MOVSXD	0x30(%RBX),%R14

0x44f1a3 TEST	%R14,%R14

0x44f1a6 JLE	44ffa5

0x44f1ac VMOVSD	(%RAX),%XMM0

0x44f1b0 VMOVSD	0x8(%RAX),%XMM1

0x44f1b5 MOV	-0xa8(%RBP),%RCX

0x44f1bc VMULSD	0xd8(%RCX),%XMM0,%XMM2

0x44f1c4 VFMADD231SD	0xf0(%RCX),%XMM1,%XMM2

0x44f1cd VMOVSD	0x10(%RAX),%XMM3

0x44f1d2 VFMADD231SD	0x108(%RCX),%XMM3,%XMM2

0x44f1db VMULSD	0xe0(%RCX),%XMM0,%XMM4

0x44f1e3 VFMADD231SD	0xf8(%RCX),%XMM1,%XMM4

0x44f1ec VFMADD231SD	0x110(%RCX),%XMM3,%XMM4

0x44f1f5 VMULSD	0xe8(%RCX),%XMM0,%XMM0

0x44f1fd VFMADD231SD	0x100(%RCX),%XMM1,%XMM0

0x44f206 VFMADD231SD	0x118(%RCX),%XMM3,%XMM0

0x44f20f VROUNDSD	$0x9,%XMM2,%XMM2,%XMM1

0x44f215 VSUBSD	%XMM1,%XMM2,%XMM16

0x44f21b VXORPD	%XMM1,%XMM1,%XMM1

0x44f21f VCMPSD	$0x1,%XMM1,%XMM2,%K1

0x44f226 VMOVAPD	%XMM16,%XMM3

0x44f22c VMOVSD	%XMM1,%XMM3,%XMM3{%K1}

0x44f232 VMOVSD	0xeabee(%RIP),%XMM5

0x44f23a VCMPSD	$0x1,%XMM2,%XMM5,%K1

0x44f241 VROUNDSD	$0x9,%XMM4,%XMM4,%XMM2

0x44f247 VMOVSD	%XMM3,%XMM16,%XMM16{%K1}

0x44f24d VSUBSD	%XMM2,%XMM4,%XMM17

0x44f253 VCMPSD	$0x1,%XMM1,%XMM4,%K1

0x44f25a VMOVAPD	%XMM17,%XMM2

0x44f260 VMOVSD	%XMM1,%XMM2,%XMM2{%K1}

0x44f266 VCMPSD	$0x1,%XMM4,%XMM5,%K1

0x44f26d VMOVSD	%XMM2,%XMM17,%XMM17{%K1}

0x44f273 VROUNDSD	$0x9,%XMM0,%XMM0,%XMM2

0x44f279 VSUBSD	%XMM2,%XMM0,%XMM18

0x44f27f VCMPSD	$0x1,%XMM1,%XMM0,%K1

0x44f286 VMOVAPD	%XMM18,%XMM2

0x44f28c VMOVSD	%XMM1,%XMM2,%XMM2{%K1}

0x44f292 VCMPSD	$0x1,%XMM0,%XMM5,%K1

0x44f299 VMOVSD	%XMM2,%XMM18,%XMM18{%K1}

0x44f29f MOV	0x2f8(%RCX),%RAX

0x44f2a6 MOV	%RAX,-0xb8(%RBP)

0x44f2ad MOV	0x310(%RCX),%RAX

0x44f2b4 MOV	%RAX,-0xb0(%RBP)

0x44f2bb MOVSXD	0x40(%RCX),%RBX

0x44f2bf LEA	(,%RBX,8),%RAX

0x44f2c7 MOV	%RAX,-0x90(%RBP)

0x44f2ce TEST	%RAX,%RAX

0x44f2d1 MOV	%RBX,-0x60(%RBP)

0x44f2d5 JE	44f800

0x44f2db TEST	%EBX,%EBX

0x44f2dd JE	44fe40

0x44f2e3 DEC	%R14

0x44f2e6 MOV	%RBX,%RAX

0x44f2e9 SHR	$0x1,%RAX

0x44f2ec MOV	%RAX,-0x78(%RBP)

0x44f2f0 AND	$-0x2,%RBX

0x44f2f4 XOR	%ECX,%ECX

0x44f2f6 VMOVSD	0xeab30(%RIP),%XMM19

0x44f300 VMOVSD	0xe7d16(%RIP),%XMM20

0x44f30a VMOVDDUP	0xe7d0c(%RIP),%XMM31

0x44f314 VMOVUPD	0xeab52(%RIP),%XMM21

0x44f31e VMOVUPD	0xeab58(%RIP),%XMM22

0x44f328 VMOVSD	0xe7d06(%RIP),%XMM23

0x44f332 VMOVSD	0xeaafc(%RIP),%XMM24

0x44f33c VMOVSD	0xe8e72(%RIP),%XMM25

0x44f346 MOV	%R14,-0x98(%RBP)

0x44f34d JMP	44f39b

0x44f34f NOPW	%CS:(%RAX,%RAX,1)

0x44f35e NOPW	%CS:(%RAX,%RAX,1)

0x44f36d NOPW	%CS:(%RAX,%RAX,1)

0x44f37c NOPL	(%RAX)

(921) 0x44f380 MOV	-0x98(%RBP),%R14

(921) 0x44f387 MOV	-0xa0(%RBP),%RCX

(921) 0x44f38e CMP	%R14,%RCX

(921) 0x44f391 LEA	0x1(%RCX),%RCX

(921) 0x44f395 JE	44ffa5

(921) 0x44f39b MOV	-0xb8(%RBP),%RAX

(921) 0x44f3a2 MOV	(%RAX,%RCX,8),%R14

(921) 0x44f3a6 MOV	%RCX,-0xa0(%RBP)

(921) 0x44f3ad LEA	(%RCX,%RCX,2),%RAX

(921) 0x44f3b1 VSUBSD	0x28(%R14),%XMM16,%XMM0

(921) 0x44f3b8 VSUBSD	0x50(%R14),%XMM17,%XMM1

(921) 0x44f3bf VSUBSD	0x78(%R14),%XMM18,%XMM2

(921) 0x44f3c6 VMULSD	0x48(%R14),%XMM0,%XMM0

(921) 0x44f3cc MOV	-0xb0(%RBP),%RCX

(921) 0x44f3d3 MOV	(%RCX,%RAX,8),%R13

(921) 0x44f3d7 MOVSXD	0x38(%R14),%RAX

(921) 0x44f3db MOV	%RAX,-0x58(%RBP)

(921) 0x44f3df VROUNDSD	$0x9,%XMM0,%XMM0,%XMM3

(921) 0x44f3e5 VCVTTSD2SI	%XMM3,%EAX

(921) 0x44f3e9 MOV	%EAX,-0x50(%RBP)

(921) 0x44f3ec VSUBSD	%XMM3,%XMM0,%XMM0

(921) 0x44f3f0 VMULSD	0x70(%R14),%XMM1,%XMM1

(921) 0x44f3f6 VMULSD	%XMM19,%XMM0,%XMM3

(921) 0x44f3fc VSUBSD	%XMM3,%XMM20,%XMM4

(921) 0x44f402 VMULSD	%XMM0,%XMM0,%XMM5

(921) 0x44f406 VMOVDDUP	%XMM0,%XMM6

(921) 0x44f40a VMOVAPD	%XMM31,%XMM8

(921) 0x44f410 VBLENDPD	$0x1,%XMM4,%XMM8,%XMM4

(921) 0x44f416 VMULPD	%XMM4,%XMM6,%XMM4

(921) 0x44f41a VADDPD	%XMM21,%XMM4,%XMM7

(921) 0x44f420 VPUNPCKLQDQ	%XMM5,%XMM6,%XMM6

(921) 0x44f424 VFMADD213PD	%XMM22,%XMM7,%XMM6

(921) 0x44f42a VROUNDSD	$0x9,%XMM1,%XMM1,%XMM7

(921) 0x44f430 VCVTTSD2SI	%XMM7,%EAX

(921) 0x44f434 MOV	%EAX,-0x48(%RBP)

(921) 0x44f437 VMULSD	0x98(%R14),%XMM2,%XMM2

(921) 0x44f440 MOVSXD	0x60(%R14),%RAX

(921) 0x44f444 MOV	%RAX,-0x38(%RBP)

(921) 0x44f448 MOVSXD	0x88(%R14),%RAX

(921) 0x44f44f MOV	%RAX,-0x30(%RBP)

(921) 0x44f453 VMOVUPD	%XMM6,-0x100(%RBP)

(921) 0x44f45b VROUNDSD	$0x9,%XMM2,%XMM2,%XMM6

(921) 0x44f461 VCVTTSD2SI	%XMM6,%EAX

(921) 0x44f465 MOV	%EAX,-0x40(%RBP)

(921) 0x44f468 VSHUFPD	$0x1,%XMM4,%XMM4,%XMM4

(921) 0x44f46d VSUBSD	%XMM4,%XMM20,%XMM4

(921) 0x44f473 VFMADD213SD	%XMM20,%XMM0,%XMM4

(921) 0x44f479 VFMADD213SD	%XMM19,%XMM0,%XMM4

(921) 0x44f47f VMOVSD	%XMM4,-0xf0(%RBP)

(921) 0x44f487 VMULSD	%XMM5,%XMM3,%XMM0

(921) 0x44f48b VMOVSD	%XMM0,-0xe8(%RBP)

(921) 0x44f493 VSUBSD	%XMM7,%XMM1,%XMM0

(921) 0x44f497 VMULSD	%XMM19,%XMM0,%XMM1

(921) 0x44f49d VSUBSD	%XMM1,%XMM20,%XMM3

(921) 0x44f4a3 VMULSD	%XMM0,%XMM0,%XMM4

(921) 0x44f4a7 VMOVDDUP	%XMM0,%XMM5

(921) 0x44f4ab VBLENDPD	$0x1,%XMM3,%XMM8,%XMM3

(921) 0x44f4b1 VMULPD	%XMM3,%XMM5,%XMM3

(921) 0x44f4b5 VADDPD	%XMM21,%XMM3,%XMM7

(921) 0x44f4bb VPUNPCKLQDQ	%XMM4,%XMM5,%XMM5

(921) 0x44f4bf VFMADD213PD	%XMM22,%XMM7,%XMM5

(921) 0x44f4c5 VMOVUPD	%XMM5,-0xe0(%RBP)

(921) 0x44f4cd VSHUFPD	$0x1,%XMM3,%XMM3,%XMM3

(921) 0x44f4d2 VSUBSD	%XMM3,%XMM20,%XMM3

(921) 0x44f4d8 VFMADD213SD	%XMM20,%XMM0,%XMM3

(921) 0x44f4de VFMADD213SD	%XMM19,%XMM0,%XMM3

(921) 0x44f4e4 VMOVSD	%XMM3,-0xd0(%RBP)

(921) 0x44f4ec VSUBSD	%XMM6,%XMM2,%XMM0

(921) 0x44f4f0 VMULSD	%XMM4,%XMM1,%XMM1

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(921) 0x44f508 VFMADD213SD	%XMM23,%XMM0,%XMM26

(921) 0x44f50e VFMADD213SD	%XMM19,%XMM0,%XMM26

(921) 0x44f514 VMULSD	%XMM20,%XMM0,%XMM1

(921) 0x44f51a VADDSD	%XMM24,%XMM1,%XMM27

(921) 0x44f520 VMULSD	%XMM0,%XMM0,%XMM30

(921) 0x44f526 VFMADD213SD	%XMM25,%XMM30,%XMM27

(921) 0x44f52c VSUBSD	%XMM1,%XMM20,%XMM28

(921) 0x44f532 VFMADD213SD	%XMM20,%XMM0,%XMM28

(921) 0x44f538 VFMADD213SD	%XMM19,%XMM0,%XMM28

(921) 0x44f53e MOV	0x10(%R14),%RAX

(921) 0x44f542 MOV	%RAX,-0x68(%RBP)

(921) 0x44f546 MOV	0x18(%R14),%R15

(921) 0x44f54a MOV	0x20(%R14),%R12

(921) 0x44f54e MOV	%R13,%RDI

(921) 0x44f551 XOR	%ESI,%ESI

(921) 0x44f553 MOV	-0x90(%RBP),%RDX

(921) 0x44f55a CALL	534740 <__intel_avx_rep_memset>

(921) 0x44f55f MOV	0x8(%R14),%RAX

(921) 0x44f563 VMULSD	%XMM30,%XMM29,%XMM0

(921) 0x44f569 MOV	-0x30(%RBP),%R10

(921) 0x44f56d DEC	%R10

(921) 0x44f570 MOV	-0x40(%RBP),%EDX

(921) 0x44f573 MOV	%EDX,%ECX

(921) 0x44f575 SAR	$0x1f,%ECX

(921) 0x44f578 ANDN	%EDX,%ECX,%ECX

(921) 0x44f57d CMP	%RCX,%R10

(921) 0x44f580 CMOVGE	%RCX,%R10

(921) 0x44f584 MOV	%R12,%RDI

(921) 0x44f587 IMUL	%R10,%RDI

(921) 0x44f58b MOV	-0x38(%RBP),%RDX

(921) 0x44f58f DEC	%RDX

(921) 0x44f592 MOV	-0x48(%RBP),%ESI

(921) 0x44f595 MOV	%ESI,%ECX

(921) 0x44f597 SAR	$0x1f,%ECX

(921) 0x44f59a ANDN	%ESI,%ECX,%ECX

(921) 0x44f59f CMP	%RCX,%RDX

(921) 0x44f5a2 CMOVGE	%RCX,%RDX

(921) 0x44f5a6 IMUL	%R15,%RDX

(921) 0x44f5aa MOV	%RDX,%R8

(921) 0x44f5ad MOV	-0x58(%RBP),%RDX

(921) 0x44f5b1 DEC	%RDX

(921) 0x44f5b4 MOV	-0x50(%RBP),%ESI

(921) 0x44f5b7 MOV	%ESI,%ECX

(921) 0x44f5b9 SAR	$0x1f,%ECX

(921) 0x44f5bc ANDN	%ESI,%ECX,%ECX

(921) 0x44f5c1 CMP	%RCX,%RDX

(921) 0x44f5c4 CMOVGE	%RCX,%RDX

(921) 0x44f5c8 MOV	-0x68(%RBP),%R9

(921) 0x44f5cc IMUL	%R9,%RDX

(921) 0x44f5d0 ADD	%R8,%RDX

(921) 0x44f5d3 LEA	(%R12,%R12,2),%RCX

(921) 0x44f5d7 VMOVDDUP	%XMM27,%XMM1

(921) 0x44f5dd VMOVDDUP	%XMM26,%XMM2

(921) 0x44f5e3 VMOVDDUP	%XMM28,%XMM3

(921) 0x44f5e9 VMOVDDUP	%XMM0,%XMM4

(921) 0x44f5ed LEA	(%RDX,%RDI,1),%R8

(921) 0x44f5f1 LEA	(%R12,%RDI,1),%RSI

(921) 0x44f5f5 ADD	%RDX,%RSI

(921) 0x44f5f8 ADD	%RBX,%RSI

(921) 0x44f5fb MOV	%RSI,-0x50(%RBP)

(921) 0x44f5ff LEA	(%RDI,%R12,2),%RSI

(921) 0x44f603 ADD	%RDX,%RSI

(921) 0x44f606 ADD	%RBX,%RSI

(921) 0x44f609 MOV	%RSI,-0x48(%RBP)

(921) 0x44f60d ADD	%RDI,%RCX

(921) 0x44f610 ADD	%RDX,%RCX

(921) 0x44f613 ADD	%RBX,%RCX

(921) 0x44f616 MOV	%RCX,-0x58(%RBP)

(921) 0x44f61a LEA	0x3(%R10),%RCX

(921) 0x44f61e IMUL	%R12,%RCX

(921) 0x44f622 ADD	%RDX,%RCX

(921) 0x44f625 LEA	(%RAX,%RCX,8),%R14

(921) 0x44f629 LEA	(,%R9,8),%RSI

(921) 0x44f631 MOV	%RSI,-0x80(%RBP)

(921) 0x44f635 MOV	%R15,%RSI

(921) 0x44f638 LEA	(,%R15,8),%R9

(921) 0x44f640 LEA	0x2(%R10),%RCX

(921) 0x44f644 IMUL	%R12,%RCX

(921) 0x44f648 ADD	%RDX,%RCX

(921) 0x44f64b LEA	(%RAX,%RCX,8),%R15

(921) 0x44f64f INC	%R10

(921) 0x44f652 IMUL	%R12,%R10

(921) 0x44f656 ADD	%RDX,%R10

(921) 0x44f659 LEA	(%RAX,%R10,8),%R11

(921) 0x44f65d LEA	(%RAX,%R8,8),%RDX

(921) 0x44f661 LEA	(%R8,%RBX,1),%RDI

(921) 0x44f665 XOR	%R8D,%R8D

(921) 0x44f668 MOV	-0x60(%RBP),%RCX

(921) 0x44f66c JMP	44f6b8

0x44f66e NOPW	%CS:(%RAX,%RAX,1)

0x44f67d NOPL	(%RAX)

  (922) 0x44f680 MOV	-0x38(%RBP),%R14

  (922) 0x44f684 MOV	-0x80(%RBP),%RDX

  (922) 0x44f688 ADD	%RDX,%R14

  (922) 0x44f68b MOV	-0x30(%RBP),%R15

  (922) 0x44f68f ADD	%RDX,%R15

  (922) 0x44f692 MOV	-0x40(%RBP),%R11

  (922) 0x44f696 ADD	%RDX,%R11

  (922) 0x44f699 MOV	-0x88(%RBP),%R8

  (922) 0x44f6a0 ADD	%RDX,%R8

  (922) 0x44f6a3 MOV	%R8,%RDX

  (922) 0x44f6a6 MOV	-0x70(%RBP),%R8

  (922) 0x44f6aa CMP	$0x3,%R8

  (922) 0x44f6ae LEA	0x1(%R8),%R8

  (922) 0x44f6b2 JE	44f380

  (922) 0x44f6b8 VMOVSD	-0x100(%RBP,%R8,8),%XMM5

  (922) 0x44f6c2 MOV	-0x68(%RBP),%R12

  (922) 0x44f6c6 MOV	%R8,-0x70(%RBP)

  (922) 0x44f6ca IMUL	%R8,%R12

  (922) 0x44f6ce MOV	%RDX,-0x88(%RBP)

  (922) 0x44f6d5 MOV	%RDX,%R8

  (922) 0x44f6d8 MOV	%R11,-0x40(%RBP)

  (922) 0x44f6dc MOV	%R15,-0x30(%RBP)

  (922) 0x44f6e0 MOV	%R15,%R10

  (922) 0x44f6e3 MOV	%R14,-0x38(%RBP)

  (922) 0x44f6e7 XOR	%R15D,%R15D

  (922) 0x44f6ea JMP	44f71a

0x44f6ec NOPW	%CS:(%RAX,%RAX,1)

0x44f6fb NOPL	(%RAX,%RAX,1)

    (923) 0x44f700 ADD	%R9,%R14

    (923) 0x44f703 ADD	%R9,%R10

    (923) 0x44f706 ADD	%R9,%R11

    (923) 0x44f709 ADD	%R9,%R8

    (923) 0x44f70c CMP	$0x3,%R15

    (923) 0x44f710 LEA	0x1(%R15),%R15

    (923) 0x44f714 JE	44f680

    (923) 0x44f71a VMULSD	-0xe0(%RBP,%R15,8),%XMM5,%XMM6

    (923) 0x44f724 CMP	$0x1,%ECX

    (923) 0x44f727 JE	44f76f

    (923) 0x44f729 VMOVDDUP	%XMM6,%XMM7

    (923) 0x44f72d MOV	-0x78(%RBP),%RCX

    (923) 0x44f731 XOR	%EDX,%EDX

    (923) 0x44f733 NOPW	%CS:(%RAX,%RAX,1)

      (924) 0x44f740 VMULPD	(%R8,%RDX,1),%XMM2,%XMM8

      (924) 0x44f746 VFMADD231PD	(%R11,%RDX,1),%XMM1,%XMM8

      (924) 0x44f74c VFMADD231PD	(%R10,%RDX,1),%XMM3,%XMM8

      (924) 0x44f752 VFMADD231PD	(%R14,%RDX,1),%XMM4,%XMM8

      (924) 0x44f758 VFMADD213PD	(%R13,%RDX,1),%XMM7,%XMM8

      (924) 0x44f75f VMOVUPD	%XMM8,(%R13,%RDX,1)

      (924) 0x44f766 ADD	$0x10,%RDX

      (924) 0x44f76a DEC	%RCX

      (924) 0x44f76d JNE	44f740

    (923) 0x44f76f MOV	-0x60(%RBP),%RCX

    (923) 0x44f773 CMP	%RCX,%RBX

    (923) 0x44f776 JE	44f700

    (923) 0x44f778 MOV	%RSI,%RCX

    (923) 0x44f77b IMUL	%R15,%RCX

    (923) 0x44f77f ADD	%R12,%RCX

    (923) 0x44f782 LEA	(%RDI,%RCX,1),%RDX

    (923) 0x44f786 VMULSD	(%RAX,%RDX,8),%XMM26,%XMM7

    (923) 0x44f78d MOV	-0x50(%RBP),%RDX

    (923) 0x44f791 ADD	%RCX,%RDX

    (923) 0x44f794 VFMADD231SD	(%RAX,%RDX,8),%XMM27,%XMM7

    (923) 0x44f79b MOV	-0x48(%RBP),%RDX

    (923) 0x44f79f ADD	%RCX,%RDX

    (923) 0x44f7a2 VFMADD231SD	(%RAX,%RDX,8),%XMM28,%XMM7

    (923) 0x44f7a9 ADD	-0x58(%RBP),%RCX

    (923) 0x44f7ad VFMADD231SD	(%RAX,%RCX,8),%XMM0,%XMM7

    (923) 0x44f7b3 MOV	-0x60(%RBP),%RCX

    (923) 0x44f7b7 VFMADD213SD	(%R13,%RBX,8),%XMM6,%XMM7

    (923) 0x44f7be VMOVSD	%XMM7,(%R13,%RBX,8)

    (923) 0x44f7c5 JMP	44f700

0x44f7ca NOPW	%CS:(%RAX,%RAX,1)

0x44f7d9 NOPW	%CS:(%RAX,%RAX,1)

0x44f7e8 NOPW	%CS:(%RAX,%RAX,1)

0x44f7f7 NOPW	(%RAX,%RAX,1)

0x44f800 TEST	%EBX,%EBX

0x44f802 JE	44ffa5

0x44f808 DEC	%R14

0x44f80b MOV	-0x60(%RBP),%RAX

0x44f80f SHR	$0x1,%RAX

0x44f812 MOV	%RAX,-0x70(%RBP)

0x44f816 XOR	%ECX,%ECX

0x44f818 VMOVSD	0xea610(%RIP),%XMM0

0x44f820 VMOVSD	0xe77f8(%RIP),%XMM1

0x44f828 VMOVDDUP	0xe77f0(%RIP),%XMM2

0x44f830 VMOVUPD	0xea638(%RIP),%XMM3

0x44f838 VMOVUPD	0xea640(%RIP),%XMM4

0x44f840 VMOVSD	0xe77f0(%RIP),%XMM5

0x44f848 VMOVSD	0xea5e8(%RIP),%XMM6

0x44f850 VMOVSD	0xe8960(%RIP),%XMM7

0x44f858 MOV	%R14,-0x98(%RBP)

0x44f85f JMP	44f89b

0x44f861 NOPW	%CS:(%RAX,%RAX,1)

0x44f870 NOPW	%CS:(%RAX,%RAX,1)

0x44f87f NOP

(908) 0x44f880 MOV	-0x98(%RBP),%R14

(908) 0x44f887 MOV	-0xa0(%RBP),%RCX

(908) 0x44f88e CMP	%R14,%RCX

(908) 0x44f891 LEA	0x1(%RCX),%RCX

(908) 0x44f895 JE	44ffa5

(908) 0x44f89b MOV	-0xb8(%RBP),%RAX

(908) 0x44f8a2 MOV	(%RAX,%RCX,8),%RBX

(908) 0x44f8a6 MOV	%RCX,-0xa0(%RBP)

(908) 0x44f8ad LEA	(%RCX,%RCX,2),%RAX

(908) 0x44f8b1 VSUBSD	0x28(%RBX),%XMM16,%XMM8

(908) 0x44f8b8 VSUBSD	0x50(%RBX),%XMM17,%XMM9

(908) 0x44f8bf MOV	-0xb0(%RBP),%RCX

(908) 0x44f8c6 MOV	(%RCX,%RAX,8),%RDX

(908) 0x44f8ca VSUBSD	0x78(%RBX),%XMM18,%XMM10

(908) 0x44f8d1 VMULSD	0x48(%RBX),%XMM8,%XMM8

(908) 0x44f8d6 MOVSXD	0x38(%RBX),%RSI

(908) 0x44f8da VROUNDSD	$0x9,%XMM8,%XMM8,%XMM11

(908) 0x44f8e0 VCVTTSD2SI	%XMM11,%R8D

(908) 0x44f8e5 VMULSD	0x70(%RBX),%XMM9,%XMM9

(908) 0x44f8ea VSUBSD	%XMM11,%XMM8,%XMM8

(908) 0x44f8ef VMULSD	%XMM0,%XMM8,%XMM12

(908) 0x44f8f3 VSUBSD	%XMM12,%XMM1,%XMM11

(908) 0x44f8f8 VMULSD	%XMM8,%XMM8,%XMM13

(908) 0x44f8fd VMOVDDUP	%XMM8,%XMM14

(908) 0x44f902 VBLENDPD	$0x1,%XMM11,%XMM2,%XMM11

(908) 0x44f908 VMULPD	%XMM11,%XMM14,%XMM15

(908) 0x44f90d VADDPD	%XMM3,%XMM15,%XMM11

(908) 0x44f911 VPUNPCKLQDQ	%XMM13,%XMM14,%XMM14

(908) 0x44f916 VFMADD213PD	%XMM4,%XMM11,%XMM14

(908) 0x44f91b VRNDSCALESD	$0x9,%XMM9,%XMM9,%XMM19

(908) 0x44f922 MOVSXD	0x60(%RBX),%R14

(908) 0x44f926 VCVTTSD2SI	%XMM19,%R10D

(908) 0x44f92c VMULSD	0x98(%RBX),%XMM10,%XMM10

(908) 0x44f934 MOVSXD	0x88(%RBX),%RDI

(908) 0x44f93b VMOVUPD	%XMM14,-0x100(%RBP)

(908) 0x44f943 VROUNDSD	$0x9,%XMM10,%XMM10,%XMM11

(908) 0x44f949 VCVTTSD2SI	%XMM11,%R11D

(908) 0x44f94e VSHUFPD	$0x1,%XMM15,%XMM15,%XMM14

(908) 0x44f954 VSUBSD	%XMM14,%XMM1,%XMM14

(908) 0x44f959 VFMADD213SD	%XMM1,%XMM8,%XMM14

(908) 0x44f95e VFMADD213SD	%XMM0,%XMM8,%XMM14

(908) 0x44f963 VMOVSD	%XMM14,-0xf0(%RBP)

(908) 0x44f96b VSUBSD	%XMM19,%XMM9,%XMM9

(908) 0x44f971 VMULSD	%XMM13,%XMM12,%XMM8

(908) 0x44f976 VMOVSD	%XMM8,-0xe8(%RBP)

(908) 0x44f97e VMULSD	%XMM0,%XMM9,%XMM12

(908) 0x44f982 VSUBSD	%XMM12,%XMM1,%XMM8

(908) 0x44f987 VMULSD	%XMM9,%XMM9,%XMM13

(908) 0x44f98c VMOVDDUP	%XMM9,%XMM14

(908) 0x44f991 VBLENDPD	$0x1,%XMM8,%XMM2,%XMM8

(908) 0x44f997 VMULPD	%XMM8,%XMM14,%XMM8

(908) 0x44f99c VADDPD	%XMM3,%XMM8,%XMM15

(908) 0x44f9a0 VPUNPCKLQDQ	%XMM13,%XMM14,%XMM14

(908) 0x44f9a5 VFMADD213PD	%XMM4,%XMM15,%XMM14

(908) 0x44f9aa VMOVUPD	%XMM14,-0xe0(%RBP)

(908) 0x44f9b2 VSHUFPD	$0x1,%XMM8,%XMM8,%XMM8

(908) 0x44f9b8 VSUBSD	%XMM8,%XMM1,%XMM8

(908) 0x44f9bd VFMADD213SD	%XMM1,%XMM9,%XMM8

(908) 0x44f9c2 VFMADD213SD	%XMM0,%XMM9,%XMM8

(908) 0x44f9c7 VMOVSD	%XMM8,-0xd0(%RBP)

(908) 0x44f9cf VMULSD	%XMM13,%XMM12,%XMM9

(908) 0x44f9d4 VMOVSD	%XMM9,-0xc8(%RBP)

(908) 0x44f9dc MOV	0x10(%RBX),%R15

(908) 0x44f9e0 MOV	%R15,-0x80(%RBP)

(908) 0x44f9e4 MOV	0x18(%RBX),%R9

(908) 0x44f9e8 MOV	0x20(%RBX),%RCX

(908) 0x44f9ec DEC	%RDI

(908) 0x44f9ef MOV	%R11D,%EAX

(908) 0x44f9f2 SAR	$0x1f,%EAX

(908) 0x44f9f5 ANDN	%R11D,%EAX,%EAX

(908) 0x44f9fa CMP	%RAX,%RDI

(908) 0x44f9fd CMOVGE	%RAX,%RDI

(908) 0x44fa01 MOV	%RCX,%R11

(908) 0x44fa04 IMUL	%RDI,%R11

(908) 0x44fa08 DEC	%R14

(908) 0x44fa0b MOV	%R10D,%EAX

(908) 0x44fa0e SAR	$0x1f,%EAX

(908) 0x44fa11 ANDN	%R10D,%EAX,%EAX

(908) 0x44fa16 CMP	%RAX,%R14

(908) 0x44fa19 CMOVGE	%RAX,%R14

(908) 0x44fa1d MOV	%R9,%RAX

(908) 0x44fa20 IMUL	%R14,%RAX

(908) 0x44fa24 MOV	%RAX,%R10

(908) 0x44fa27 MOV	%RAX,-0x30(%RBP)

(908) 0x44fa2b DEC	%RSI

(908) 0x44fa2e MOV	%R8D,%EAX

(908) 0x44fa31 SAR	$0x1f,%EAX

(908) 0x44fa34 ANDN	%R8D,%EAX,%EAX

(908) 0x44fa39 CMP	%RAX,%RSI

(908) 0x44fa3c CMOVGE	%RAX,%RSI

(908) 0x44fa40 IMUL	%R15,%RSI

(908) 0x44fa44 LEA	0x2(%RDI),%RAX

(908) 0x44fa48 IMUL	%RCX,%RAX

(908) 0x44fa4c LEA	0x3(%RDI),%R15

(908) 0x44fa50 IMUL	%RCX,%R15

(908) 0x44fa54 INC	%RDI

(908) 0x44fa57 IMUL	%RCX,%RDI

(908) 0x44fa5b MOV	%R14,%R8

(908) 0x44fa5e LEA	0x1(%R14),%R12

(908) 0x44fa62 IMUL	%R9,%R12

(908) 0x44fa66 LEA	0x2(%R14),%R13

(908) 0x44fa6a IMUL	%R9,%R13

(908) 0x44fa6e ADD	$0x3,%R8

(908) 0x44fa72 IMUL	%R9,%R8

(908) 0x44fa76 LEA	(%R10,%RSI,1),%R9

(908) 0x44fa7a MOV	%R15,%RCX

(908) 0x44fa7d LEA	(%R9,%R15,1),%R10

(908) 0x44fa81 MOV	%R10,-0x48(%RBP)

(908) 0x44fa85 LEA	(%R9,%RAX,1),%R10

(908) 0x44fa89 MOV	%R10,-0x78(%RBP)

(908) 0x44fa8d ADD	%RDI,%R9

(908) 0x44fa90 ADD	%RSI,%R11

(908) 0x44fa93 LEA	(%RSI,%R12,1),%R14

(908) 0x44fa97 LEA	(%R14,%RAX,1),%R10

(908) 0x44fa9b MOV	%R10,-0x38(%RBP)

(908) 0x44fa9f ADD	%RDI,%R14

(908) 0x44faa2 LEA	(%RSI,%R13,1),%R15

(908) 0x44faa6 LEA	(%R15,%RAX,1),%R10

(908) 0x44faaa MOV	%R10,-0x58(%RBP)

(908) 0x44faae ADD	%RDI,%R15

(908) 0x44fab1 MOV	%R15,-0x50(%RBP)

(908) 0x44fab5 LEA	(%RSI,%RCX,1),%R15

(908) 0x44fab9 ADD	%R8,%RSI

(908) 0x44fabc ADD	%RSI,%RCX

(908) 0x44fabf MOV	%RCX,-0x40(%RBP)

(908) 0x44fac3 ADD	%RSI,%RAX

(908) 0x44fac6 MOV	%RAX,-0x68(%RBP)

(908) 0x44faca ADD	%RDI,%RSI

(908) 0x44facd MOV	%RSI,-0x90(%RBP)

(908) 0x44fad4 MOV	-0x30(%RBP),%RAX

(908) 0x44fad8 ADD	%R11,%RAX

(908) 0x44fadb LEA	(%R15,%R12,1),%RCX

(908) 0x44fadf MOV	%RCX,-0x30(%RBP)

(908) 0x44fae3 ADD	%R11,%R12

(908) 0x44fae6 ADD	%R13,%R15

(908) 0x44fae9 ADD	%R11,%R13

(908) 0x44faec ADD	%R11,%R8

(908) 0x44faef MOV	%R8,-0x118(%RBP)

(908) 0x44faf6 MOV	0x8(%RBX),%RCX

(908) 0x44fafa MOV	-0x48(%RBP),%RSI

(908) 0x44fafe LEA	(%RCX,%RSI,8),%RDI

(908) 0x44fb02 MOV	-0x78(%RBP),%RSI

(908) 0x44fb06 LEA	(%RCX,%RSI,8),%R8

(908) 0x44fb0a LEA	(%RCX,%R9,8),%R9

(908) 0x44fb0e LEA	(%RCX,%RAX,8),%R10

(908) 0x44fb12 MOV	-0x30(%RBP),%RAX

(908) 0x44fb16 LEA	(%RCX,%RAX,8),%R11

(908) 0x44fb1a MOV	-0x38(%RBP),%RAX

(908) 0x44fb1e LEA	(%RCX,%RAX,8),%RBX

(908) 0x44fb22 LEA	(%RCX,%R14,8),%R14

(908) 0x44fb26 LEA	(%RCX,%R12,8),%R12

(908) 0x44fb2a LEA	(%RCX,%R15,8),%RAX

(908) 0x44fb2e MOV	%RAX,-0x88(%RBP)

(908) 0x44fb35 MOV	-0x58(%RBP),%RAX

(908) 0x44fb39 LEA	(%RCX,%RAX,8),%RAX

(908) 0x44fb3d MOV	%RAX,-0x30(%RBP)

(908) 0x44fb41 MOV	-0x50(%RBP),%RAX

(908) 0x44fb45 LEA	(%RCX,%RAX,8),%RSI

(908) 0x44fb49 LEA	(%RCX,%R13,8),%R15

(908) 0x44fb4d MOV	%RSI,%R13

(908) 0x44fb50 MOV	-0x80(%RBP),%RSI

(908) 0x44fb54 MOV	-0x40(%RBP),%RAX

(908) 0x44fb58 LEA	(%RCX,%RAX,8),%RAX

(908) 0x44fb5c MOV	%RAX,-0x58(%RBP)

(908) 0x44fb60 MOV	-0x68(%RBP),%RAX

(908) 0x44fb64 LEA	(%RCX,%RAX,8),%RAX

(908) 0x44fb68 MOV	%RAX,-0x50(%RBP)

(908) 0x44fb6c MOV	-0x90(%RBP),%RAX

(908) 0x44fb73 LEA	(%RCX,%RAX,8),%RAX

(908) 0x44fb77 MOV	%RAX,-0x48(%RBP)

(908) 0x44fb7b MOV	-0x118(%RBP),%RAX

(908) 0x44fb82 LEA	(%RCX,%RAX,8),%RAX

(908) 0x44fb86 MOV	%RAX,-0x78(%RBP)

(908) 0x44fb8a VSUBSD	%XMM11,%XMM10,%XMM10

(908) 0x44fb8f VMULSD	%XMM0,%XMM10,%XMM11

(908) 0x44fb93 VSUBSD	%XMM11,%XMM1,%XMM13

(908) 0x44fb98 VFMADD213SD	%XMM5,%XMM10,%XMM13

(908) 0x44fb9d VFMADD213SD	%XMM0,%XMM10,%XMM13

(908) 0x44fba2 VMULSD	%XMM1,%XMM10,%XMM12

(908) 0x44fba6 VADDSD	%XMM6,%XMM12,%XMM14

(908) 0x44fbaa VMULSD	%XMM10,%XMM10,%XMM15

(908) 0x44fbaf VFMADD213SD	%XMM7,%XMM15,%XMM14

(908) 0x44fbb4 VSUBSD	%XMM12,%XMM1,%XMM19

(908) 0x44fbba VFMADD213SD	%XMM1,%XMM10,%XMM19

(908) 0x44fbc0 VFMADD213SD	%XMM0,%XMM10,%XMM19

(908) 0x44fbc6 VMULSD	%XMM15,%XMM11,%XMM15

(908) 0x44fbcb VMOVSD	-0xe0(%RBP),%XMM10

(908) 0x44fbd3 VMOVSD	-0xd8(%RBP),%XMM11

(908) 0x44fbdb VMOVDDUP	%XMM14,%XMM12

(908) 0x44fbe0 VMOVDDUP	%XMM13,%XMM13

(908) 0x44fbe5 VMOVDDUP	%XMM19,%XMM14

(908) 0x44fbeb VMOVDDUP	%XMM15,%XMM15

(908) 0x44fbf0 SAL	$0x3,%RSI

(908) 0x44fbf4 MOVQ	$0,-0x38(%RBP)

(908) 0x44fbfc MOV	%RSI,-0x80(%RBP)

(908) 0x44fc00 JMP	44fc9a

0x44fc05 NOPW	%CS:(%RAX,%RAX,1)

0x44fc14 NOPW	%CS:(%RAX,%RAX,1)

0x44fc23 NOPW	%CS:(%RAX,%RAX,1)

0x44fc32 NOPW	%CS:(%RAX,%RAX,1)

  (909) 0x44fc40 ADD	%RSI,%RDI

  (909) 0x44fc43 ADD	%RSI,%R8

  (909) 0x44fc46 ADD	%RSI,%R9

  (909) 0x44fc49 ADD	%RSI,%R10

  (909) 0x44fc4c ADD	%RSI,%R11

  (909) 0x44fc4f ADD	%RSI,%RBX

  (909) 0x44fc52 ADD	%RSI,%R14

  (909) 0x44fc55 ADD	%RSI,%R12

  (909) 0x44fc58 ADD	%RSI,-0x88(%RBP)

  (909) 0x44fc5f MOV	-0x30(%RBP),%RAX

  (909) 0x44fc63 ADD	%RSI,%RAX

  (909) 0x44fc66 MOV	%RAX,-0x30(%RBP)

  (909) 0x44fc6a ADD	%RSI,%R13

  (909) 0x44fc6d MOV	-0x40(%RBP),%R15

  (909) 0x44fc71 ADD	%RSI,%R15

  (909) 0x44fc74 ADD	%RSI,-0x58(%RBP)

  (909) 0x44fc78 ADD	%RSI,-0x50(%RBP)

  (909) 0x44fc7c ADD	%RSI,-0x48(%RBP)

  (909) 0x44fc80 ADD	%RSI,-0x78(%RBP)

  (909) 0x44fc84 MOV	-0x38(%RBP),%RAX

  (909) 0x44fc88 CMP	$0x3,%RAX

  (909) 0x44fc8c LEA	0x1(%RAX),%RAX

  (909) 0x44fc90 MOV	%RAX,-0x38(%RBP)

  (909) 0x44fc94 JE	44f880

  (909) 0x44fc9a MOV	%R15,-0x40(%RBP)

  (909) 0x44fc9e CMPL	$0x1,-0x60(%RBP)

  (909) 0x44fca2 JE	44fc40

  (909) 0x44fca4 MOV	-0x38(%RBP),%RAX

  (909) 0x44fca8 VMOVSD	-0x100(%RBP,%RAX,8),%XMM19

  (909) 0x44fcb0 VMULSD	%XMM19,%XMM10,%XMM20

  (909) 0x44fcb6 VMOVDDUP	%XMM20,%XMM20

  (909) 0x44fcbc MOV	-0x70(%RBP),%R15

  (909) 0x44fcc0 XOR	%ECX,%ECX

  (909) 0x44fcc2 NOPW	%CS:(%RAX,%RAX,1)

    (910) 0x44fcd0 VMULPD	(%R10,%RCX,1),%XMM13,%XMM21

    (910) 0x44fcd7 VFMADD231PD	(%R9,%RCX,1),%XMM12,%XMM21

    (910) 0x44fcde VFMADD231PD	(%R8,%RCX,1),%XMM14,%XMM21

    (910) 0x44fce5 VFMADD231PD	(%RDI,%RCX,1),%XMM15,%XMM21

    (910) 0x44fcec VFMADD213PD	(%RDX,%RCX,1),%XMM20,%XMM21

    (910) 0x44fcf3 VMOVUPD	%XMM21,(%RDX,%RCX,1)

    (910) 0x44fcfa ADD	$0x10,%RCX

    (910) 0x44fcfe DEC	%R15

    (910) 0x44fd01 JNE	44fcd0

  (909) 0x44fd03 CMPL	$0x1,-0x60(%RBP)

  (909) 0x44fd07 JE	44fc40

  (909) 0x44fd0d VMULSD	%XMM19,%XMM11,%XMM20

  (909) 0x44fd13 VMOVDDUP	%XMM20,%XMM20

  (909) 0x44fd19 XOR	%R15D,%R15D

  (909) 0x44fd1c MOV	-0x70(%RBP),%RCX

    (911) 0x44fd20 VMULPD	(%R12,%R15,1),%XMM13,%XMM21

    (911) 0x44fd27 VFMADD231PD	(%R14,%R15,1),%XMM12,%XMM21

    (911) 0x44fd2e VFMADD231PD	(%RBX,%R15,1),%XMM14,%XMM21

    (911) 0x44fd35 VFMADD231PD	(%R11,%R15,1),%XMM15,%XMM21

    (911) 0x44fd3c VFMADD213PD	(%RDX,%R15,1),%XMM20,%XMM21

    (911) 0x44fd43 VMOVUPD	%XMM21,(%RDX,%R15,1)

    (911) 0x44fd4a ADD	$0x10,%R15

    (911) 0x44fd4e DEC	%RCX

    (911) 0x44fd51 JNE	44fd20

  (909) 0x44fd53 CMPL	$0x1,-0x60(%RBP)

  (909) 0x44fd57 JE	44fc40

  (909) 0x44fd5d MOV	%R11,-0x68(%RBP)

  (909) 0x44fd61 VMULSD	%XMM19,%XMM8,%XMM20

  (909) 0x44fd67 VMOVDDUP	%XMM20,%XMM20

  (909) 0x44fd6d XOR	%R15D,%R15D

  (909) 0x44fd70 MOV	-0x70(%RBP),%RCX

  (909) 0x44fd74 MOV	%R13,%RSI

  (909) 0x44fd77 MOV	-0x30(%RBP),%R13

  (909) 0x44fd7b MOV	-0x88(%RBP),%RAX

  (909) 0x44fd82 MOV	-0x40(%RBP),%R11

  (909) 0x44fd86 NOPW	%CS:(%RAX,%RAX,1)

    (912) 0x44fd90 VMULPD	(%R11,%R15,1),%XMM13,%XMM21

    (912) 0x44fd97 VFMADD231PD	(%RSI,%R15,1),%XMM12,%XMM21

    (912) 0x44fd9e VFMADD231PD	(%R13,%R15,1),%XMM14,%XMM21

    (912) 0x44fda6 VFMADD231PD	(%RAX,%R15,1),%XMM15,%XMM21

    (912) 0x44fdad VFMADD213PD	(%RDX,%R15,1),%XMM20,%XMM21

    (912) 0x44fdb4 VMOVUPD	%XMM21,(%RDX,%R15,1)

    (912) 0x44fdbb ADD	$0x10,%R15

    (912) 0x44fdbf DEC	%RCX

    (912) 0x44fdc2 JNE	44fd90

  (909) 0x44fdc4 CMPL	$0x1,-0x60(%RBP)

  (909) 0x44fdc8 MOV	%RSI,%R13

  (909) 0x44fdcb MOV	-0x80(%RBP),%RSI

  (909) 0x44fdcf MOV	-0x68(%RBP),%R11

  (909) 0x44fdd3 JE	44fc40

  (909) 0x44fdd9 VMULSD	%XMM19,%XMM9,%XMM19

  (909) 0x44fddf VMOVDDUP	%XMM19,%XMM19

  (909) 0x44fde5 XOR	%R15D,%R15D

  (909) 0x44fde8 MOV	-0x70(%RBP),%RCX

  (909) 0x44fdec NOPL	(%RAX)

    (913) 0x44fdf0 MOV	-0x78(%RBP),%RAX

    (913) 0x44fdf4 VMULPD	(%RAX,%R15,1),%XMM13,%XMM20

    (913) 0x44fdfb MOV	-0x48(%RBP),%RAX

    (913) 0x44fdff VFMADD231PD	(%RAX,%R15,1),%XMM12,%XMM20

    (913) 0x44fe06 MOV	-0x50(%RBP),%RAX

    (913) 0x44fe0a VFMADD231PD	(%RAX,%R15,1),%XMM14,%XMM20

    (913) 0x44fe11 MOV	-0x58(%RBP),%RAX

    (913) 0x44fe15 VFMADD231PD	(%RAX,%R15,1),%XMM15,%XMM20

    (913) 0x44fe1c VFMADD213PD	(%RDX,%R15,1),%XMM19,%XMM20

    (913) 0x44fe23 VMOVUPD	%XMM20,(%RDX,%R15,1)

    (913) 0x44fe2a ADD	$0x10,%R15

    (913) 0x44fe2e DEC	%RCX

    (913) 0x44fe31 JNE	44fdf0

  (909) 0x44fe33 JMP	44fc40

0x44fe38 NOPL	(%RAX,%RAX,1)

0x44fe40 CMP	$0x40,%R14D

0x44fe44 JBE	44ff80

0x44fe4a DEC	%R14

0x44fe4d MOV	%R14,%RAX

0x44fe50 SHR	$0x6,%RAX

0x44fe54 XOR	%ECX,%ECX

0x44fe56 MOV	$0x3f,%EDX

0x44fe5b MOV	%R14,%RSI

0x44fe5e JMP	44fe91

0x44fe60 NOPW	%CS:(%RAX,%RAX,1)

0x44fe6f NOPW	%CS:(%RAX,%RAX,1)

0x44fe7e XCHG	%AX,%AX

(917) 0x44fe80 ADD	$-0x40,%RSI

(917) 0x44fe84 CMP	%RAX,%RCX

(917) 0x44fe87 LEA	0x1(%RCX),%RCX

(917) 0x44fe8b JE	44ffa5

(917) 0x44fe91 CMP	$0x3f,%RSI

(917) 0x44fe95 MOV	$0x3f,%EDI

(917) 0x44fe9a CMOVL	%RSI,%RDI

(917) 0x44fe9e MOV	%RCX,%R9

(917) 0x44fea1 SAL	$0x6,%R9

(917) 0x44fea5 MOV	%R14,%R8

(917) 0x44fea8 SUB	%R9,%R8

(917) 0x44feab CMP	$0x3f,%R8

(917) 0x44feaf CMOVGE	%RDX,%R8

(917) 0x44feb3 CMP	$0x7,%R8

(917) 0x44feb7 JB	44fed6

(917) 0x44feb9 LEA	0x1(%RDI),%R9

(917) 0x44febd AND	$-0x8,%R9

(917) 0x44fec1 NOPW	%CS:(%RAX,%RAX,1)

  (920) 0x44fed0 ADD	$-0x8,%R9

  (920) 0x44fed4 JNE	44fed0

(917) 0x44fed6 INC	%R8

(917) 0x44fed9 TEST	$0x7,%R8B

(917) 0x44fedd JE	44fef5

(917) 0x44fedf LEA	0x1(%RDI),%R9D

(917) 0x44fee3 MOVZX	%R9B,%R9D

(917) 0x44fee7 AND	$0x7,%R9D

(917) 0x44feeb NOPL	(%RAX,%RAX,1)

  (919) 0x44fef0 DEC	%R9

  (919) 0x44fef3 JNE	44fef0

(917) 0x44fef5 MOV	%R8,%R9

(917) 0x44fef8 AND	$-0x4,%R9

(917) 0x44fefc JE	44ff40

(917) 0x44fefe LEA	-0x1(%R9),%R10

(917) 0x44ff02 XOR	%R11D,%R11D

(917) 0x44ff05 NOPW	%CS:(%RAX,%RAX,1)

  (918) 0x44ff10 ADD	$0x4,%R11

  (918) 0x44ff14 CMP	%R10,%R11

  (918) 0x44ff17 JLE	44ff10

(917) 0x44ff19 CMP	%R9,%R8

(917) 0x44ff1c JE	44fe80

(917) 0x44ff22 JMP	44ff43

0x44ff24 NOPW	%CS:(%RAX,%RAX,1)

0x44ff33 NOPW	%CS:(%RAX,%RAX,1)

(917) 0x44ff40 XOR	%R9D,%R9D

(917) 0x44ff43 SUB	%R9,%RDI

(917) 0x44ff46 INC	%RDI

(917) 0x44ff49 NOPL	(%RAX)

  (916) 0x44ff50 DEC	%RDI

  (916) 0x44ff53 JNE	44ff50

(917) 0x44ff55 JMP	44fe80

0x44ff5a NOPW	%CS:(%RAX,%RAX,1)

0x44ff69 NOPW	%CS:(%RAX,%RAX,1)

0x44ff78 NOPL	(%RAX,%RAX,1)

0x44ff80 MOV	%R14D,%EAX

0x44ff83 AND	$0x7,%EAX

0x44ff86 CMP	$0x8,%R14D

0x44ff8a JB	44ff96

0x44ff8c AND	$0x78,%R14D

(915) 0x44ff90 ADD	$-0x8,%R14

(915) 0x44ff94 JNE	44ff90

0x44ff96 TEST	%RAX,%RAX

0x44ff99 JE	44ffa5

0x44ff9b NOPL	(%RAX,%RAX,1)

(914) 0x44ffa0 DEC	%RAX

(914) 0x44ffa3 JNE	44ffa0

0x44ffa5 MOV	-0x110(%RBP),%RDI

0x44ffac CALL	4b63c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>

0x44ffb1 MOV	-0xa8(%RBP),%R12

0x44ffb8 MOV	0x30(%R12),%EAX

0x44ffbd TEST	%EAX,%EAX

0x44ffbf MOV	-0x108(%RBP),%R15

0x44ffc6 JLE	450080

0x44ffcc XOR	%EBX,%EBX

0x44ffce XOR	%R14D,%R14D

0x44ffd1 JMP	45000c

0x44ffd3 NOPW	%CS:(%RAX,%RAX,1)

0x44ffe2 NOPW	%CS:(%RAX,%RAX,1)

0x44fff1 NOPW	%CS:(%RAX,%RAX,1)

(907) 0x450000 MOVSXD	%EAX,%RCX

(907) 0x450003 ADD	$0x18,%RBX

(907) 0x450007 CMP	%RCX,%R14

(907) 0x45000a JGE	450080

(907) 0x45000c MOV	%R14D,%ECX

(907) 0x45000f IMUL	%EAX,%ECX

(907) 0x450012 INC	%R14

(907) 0x450015 MOV	0x40(%R12),%EDX

(907) 0x45001a IMUL	%R14D,%EDX

(907) 0x45001e MOV	0x8(%R12),%ESI

(907) 0x450023 CMP	%EDX,%ESI

(907) 0x450025 CMOVL	%ESI,%EDX

(907) 0x450028 SUB	%ECX,%EDX

(907) 0x45002a JLE	450000

(907) 0x45002c MOV	0x310(%R12),%RAX

(907) 0x450034 MOV	(%RAX,%RBX,1),%RSI

(907) 0x450038 MOVSXD	%ECX,%RDI

(907) 0x45003b SAL	$0x3,%RDI

(907) 0x45003f ADD	0x18(%R15),%RDI

(907) 0x450043 MOV	%EDX,%EDX

(907) 0x450045 SAL	$0x3,%RDX

(907) 0x450049 CALL	4040b0 <memmove@plt>

(907) 0x45004e MOV	0x30(%R12),%EAX

(907) 0x450053 JMP	450000

0x450055 NOPW	%CS:(%RAX,%RAX,1)

0x450064 NOPW	%CS:(%RAX,%RAX,1)

0x450073 NOPW	%CS:(%RAX,%RAX,1)

0x450080 ADD	$0xf8,%RSP

0x450087 POP	%RBX

0x450088 POP	%R12

0x45008a POP	%R13

0x45008c POP	%R14

0x45008e POP	%R15

0x450090 POP	%RBP

0x450091 RET

0x450092 NOPW	%CS:(%RAX,%RAX,1)

0x4500a1 NOPW	%CS:(%RAX,%RAX,1)

0x4500b0 NOPW	%CS:(%RAX,%RAX,1)

0x4500bf NOP

0x4500c0 MOV	%RAX,%RDI

0x4500c3 CALL	410460 <__clang_call_terminate>

0x4500c8 NOPW	%CS:(%RAX,%RAX,1)

0x4500d2 NOPW	%CS:(%RAX,%RAX,1)

0x4500dc NOPW	%CS:(%RAX,%RAX,1)

0x4500e6 NOPW	%CS:(%RAX,%RAX,1)

0x4500f0 NOPW	%CS:(%RAX,%RAX,1)

0x4500fa NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	qmcplusplus::SPOSet::evaluateD[...]	OhmmsVector.h:178	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:217	exec
○	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:919	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:135	exec
○	main.extracted.107	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run icx_4

Source file and lines	einspline_spo_ref.hpp:172-189
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h:150-152
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:172-189
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046,1169
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:235,429-431,923-924
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:61
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algo.h:725,751
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:45-47
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:143
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:54-57
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:42-49,56-71

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 32.33 to 11.17 cycles (2.90x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 32.33 to 2.74 cycles (11.80x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__clang_call_terminate: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249
qmcplusplus::TimerType
::start(): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242
qmcplusplus::TimerType
::stop(): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VROUNDSD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170

Type of elements and instruction set

21 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 18 FP arithmetical operations:

9: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 352 bytes (44 double precision FP elements). The binary function is storing 88 bytes (11 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	188
nb uops	194
loop length	1281
used x86 registers	12
used mmx registers	0
used xmm registers	19
used ymm registers	0
used zmm registers	0
nb stack references	10
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	32.33 cycles
front end	32.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	12.17	12.17	16.33	16.33	10.00	12.17	12.30	10.00	10.00	10.00	12.20	16.33
cycles	12.17	12.17	16.33	16.33	10.00	12.17	12.30	10.00	10.00	10.00	12.20	16.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	32.33
Dispatch	16.33
Overall L1	32.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	15%
load	13%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

INT+FP

all	10%
load	12%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Vector efficiency ratios

INT

all	10%
load	8%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	14%
load	14%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	12%
load	13%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 32.33 cycles. At this rate:

5% of peak load performance is reached (10.89 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.72 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 32.33 to 16.33 cycles (1.98x speedup).

ASM code

In the binary file, the address of the function is: 44f140

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xf8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,-0x108(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %EDX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x358(%RDI),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4b6140 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOVSXD %R12D,%RAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (%RAX,%RAX,2),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD 0x40(%R13),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
CMP %EAX,0x124(%R13)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
LEA 0x128(%R13),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMOVNE %RCX,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %RBX,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD 0x30(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
TEST %R14,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 44ffa5 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xe65>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RAX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x8(%RAX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xa8(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD 0xd8(%RCX),%XMM0,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0xf0(%RCX),%XMM1,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x10(%RAX),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD231SD 0x108(%RCX),%XMM3,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMULSD 0xe0(%RCX),%XMM0,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0xf8(%RCX),%XMM1,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0x110(%RCX),%XMM3,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMULSD 0xe8(%RCX),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0x100(%RCX),%XMM1,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0x118(%RCX),%XMM3,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VROUNDSD $0x9,%XMM2,%XMM2,%XMM1	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VSUBSD %XMM1,%XMM2,%XMM16	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCMPSD $0x1,%XMM1,%XMM2,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM16,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD %XMM1,%XMM3,%XMM3{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VMOVSD 0xeabee(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCMPSD $0x1,%XMM2,%XMM5,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VROUNDSD $0x9,%XMM4,%XMM4,%XMM2	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VMOVSD %XMM3,%XMM16,%XMM16{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VSUBSD %XMM2,%XMM4,%XMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VCMPSD $0x1,%XMM1,%XMM4,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM17,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD %XMM1,%XMM2,%XMM2{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VCMPSD $0x1,%XMM4,%XMM5,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM2,%XMM17,%XMM17{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VROUNDSD $0x9,%XMM0,%XMM0,%XMM2	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VSUBSD %XMM2,%XMM0,%XMM18	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VCMPSD $0x1,%XMM1,%XMM0,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM18,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD %XMM1,%XMM2,%XMM2{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VCMPSD $0x1,%XMM0,%XMM5,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM2,%XMM18,%XMM18{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV 0x2f8(%RCX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x310(%RCX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD 0x40(%RCX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RBX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %RBX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 44f800 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x6c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %EBX,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JE 44fe40 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xd00>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
DEC %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND $-0x2,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0xeab30(%RIP),%XMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe7d16(%RIP),%XMM20	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVDDUP 0xe7d0c(%RIP),%XMM31	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD 0xeab52(%RIP),%XMM21	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPD 0xeab58(%RIP),%XMM22	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0xe7d06(%RIP),%XMM23	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xeaafc(%RIP),%XMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe8e72(%RIP),%XMM25	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R14,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 44f39b <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x25b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %EBX,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JE 44ffa5 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xe65>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
DEC %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SHR $0x1,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0xea610(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe77f8(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVDDUP 0xe77f0(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD 0xea638(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPD 0xea640(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0xe77f0(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xea5e8(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe8960(%RIP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R14,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 44f89b <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x75b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x40,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JBE 44ff80 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xe40>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
DEC %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x6,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x3f,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R14,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 44fe91 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xd51>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP $0x8,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 44ff96 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xe56>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
AND $0x78,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 44ffa5 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xe65>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x110(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 4b63c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0xa8(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%R12),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
MOV -0x108(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JLE 450080 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xf40>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 45000c <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xecc>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0xf8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 410460 <__clang_call_terminate>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run icx_4

Source file and lines	einspline_spo_ref.hpp:172-189
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h:150-152
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:172-189
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046,1169
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:235,429-431,923-924
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:61
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algo.h:725,751
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:45-47
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:143
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:54-57
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:42-49,56-71

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

CALL instructions

Detected function call instructions.

Details

__clang_call_terminate: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249
qmcplusplus::TimerType
::start(): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242
qmcplusplus::TimerType
::stop(): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VROUNDSD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170

Type of elements and instruction set

21 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 18 FP arithmetical operations:

9: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 352 bytes (44 double precision FP elements). The binary function is storing 88 bytes (11 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	188
nb uops	194
loop length	1281
used x86 registers	12
used mmx registers	0
used xmm registers	19
used ymm registers	0
used zmm registers	0
nb stack references	10
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	32.33 cycles
front end	32.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	12.17	12.17	16.33	16.33	10.00	12.17	12.30	10.00	10.00	10.00	12.20	16.33
cycles	12.17	12.17	16.33	16.33	10.00	12.17	12.30	10.00	10.00	10.00	12.20	16.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	32.33
Dispatch	16.33
Overall L1	32.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	15%
load	13%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

INT+FP

all	10%
load	12%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Vector efficiency ratios

INT

all	10%
load	8%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	14%
load	14%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	12%
load	13%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 32.33 cycles. At this rate:

5% of peak load performance is reached (10.89 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.72 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 44f140

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xf8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,-0x108(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %EDX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x358(%RDI),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4b6140 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOVSXD %R12D,%RAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (%RAX,%RAX,2),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD 0x40(%R13),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
CMP %EAX,0x124(%R13)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
LEA 0x128(%R13),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMOVNE %RCX,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %RBX,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD 0x30(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
TEST %R14,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 44ffa5 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xe65>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RAX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x8(%RAX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xa8(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD 0xd8(%RCX),%XMM0,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0xf0(%RCX),%XMM1,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x10(%RAX),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD231SD 0x108(%RCX),%XMM3,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMULSD 0xe0(%RCX),%XMM0,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0xf8(%RCX),%XMM1,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0x110(%RCX),%XMM3,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMULSD 0xe8(%RCX),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0x100(%RCX),%XMM1,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD 0x118(%RCX),%XMM3,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VROUNDSD $0x9,%XMM2,%XMM2,%XMM1	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VSUBSD %XMM1,%XMM2,%XMM16	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCMPSD $0x1,%XMM1,%XMM2,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM16,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD %XMM1,%XMM3,%XMM3{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VMOVSD 0xeabee(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCMPSD $0x1,%XMM2,%XMM5,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VROUNDSD $0x9,%XMM4,%XMM4,%XMM2	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VMOVSD %XMM3,%XMM16,%XMM16{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VSUBSD %XMM2,%XMM4,%XMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VCMPSD $0x1,%XMM1,%XMM4,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM17,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD %XMM1,%XMM2,%XMM2{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VCMPSD $0x1,%XMM4,%XMM5,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM2,%XMM17,%XMM17{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VROUNDSD $0x9,%XMM0,%XMM0,%XMM2	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VSUBSD %XMM2,%XMM0,%XMM18	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VCMPSD $0x1,%XMM1,%XMM0,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM18,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD %XMM1,%XMM2,%XMM2{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VCMPSD $0x1,%XMM0,%XMM5,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM2,%XMM18,%XMM18{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV 0x2f8(%RCX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x310(%RCX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD 0x40(%RCX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RBX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %RBX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 44f800 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x6c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %EBX,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JE 44fe40 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xd00>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
DEC %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND $-0x2,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0xeab30(%RIP),%XMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe7d16(%RIP),%XMM20	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVDDUP 0xe7d0c(%RIP),%XMM31	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD 0xeab52(%RIP),%XMM21	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPD 0xeab58(%RIP),%XMM22	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0xe7d06(%RIP),%XMM23	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xeaafc(%RIP),%XMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe8e72(%RIP),%XMM25	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R14,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 44f39b <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x25b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %EBX,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JE 44ffa5 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xe65>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
DEC %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SHR $0x1,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0xea610(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe77f8(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVDDUP 0xe77f0(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD 0xea638(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPD 0xea640(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0xe77f0(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xea5e8(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xe8960(%RIP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R14,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 44f89b <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x75b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x40,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JBE 44ff80 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xe40>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
DEC %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x6,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x3f,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R14,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 44fe91 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xd51>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP $0x8,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 44ff96 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xe56>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
AND $0x78,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 44ffa5 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xe65>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x110(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 4b63c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0xa8(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%R12),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
MOV -0x108(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JLE 450080 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xf40>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 45000c <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xecc>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0xf8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 410460 <__clang_call_terminate>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)–	19.93	17.06
▼Loop 921 - MultiBsplineRef.hpp:42-71 - exec–	0.00	0.01
▼Loop 922 - MultiBsplineRef.hpp:63-71 - exec–	0.00	0.01
▼Loop 923 - MultiBsplineRef.hpp:64-71 - exec–	0.00	0.01
○Loop 924 - MultiBsplineRef.hpp:68-70 - exec	19.92	16.83
○Loop 907 - einspline_spo_ref.hpp:183-187 - exec	0.00	0.01
▼Loop 917 - MultiBsplineRef.hpp:68-68 - exec–	0.00	0.00
○Loop 920 - einspline_spo_ref.hpp:175-175 - exec	0.00	0.00
○Loop 919 - einspline_spo_ref.hpp:175-175 - exec	0.00	0.00
○Loop 918 - einspline_spo_ref.hpp:175-175 - exec	0.00	0.00
○Loop 916 - einspline_spo_ref.hpp:175-175 - exec	0.00	0.00
▼Loop 908 - MultiBsplineRef.hpp:42-71 - exec–	0.00	0.00
▼Loop 909 - MultiBsplineRef.hpp:63-70 - exec–	0.00	0.00
○Loop 912 - MultiBsplineRef.hpp:68-70 - exec	0.00	0.00
○Loop 913 - MultiBsplineRef.hpp:68-70 - exec	0.00	0.00
○Loop 911 - MultiBsplineRef.hpp:68-70 - exec	0.00	0.00
○Loop 910 - MultiBsplineRef.hpp:68-70 - exec	0.00	0.00
○Loop 915 - einspline_spo_ref.hpp:175-175 - exec	0.00	0.00
○Loop 914 - einspline_spo_ref.hpp:175-175 - exec	0.00	0.00

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ASM code

Code clean check

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Vectorization

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Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code