OV - exec - Loop 620

	Loop Id: 620	Module: exec	Source: TwoBodyJastrowRef.h:324-331	Coverage: 0.32%

0x4577d4 VMOVSD	(%R9,%RSI,1),%XMM12    [4]

0x4577da VMOVSD	(%RCX,%RSI,1),%XMM13    [7]

0x4577df VADDSD	(%RDX,%RSI,1),%XMM12,%XMM2    [8]

0x4577e4 VFMADD213SD	(%RDI,%RSI,1),%XMM4,%XMM13    [2]

0x4577ea VMOVSD	(%RBX,%RSI,1),%XMM15    [6]

0x4577ef VSUBSD	(%RAX,%RSI,1),%XMM2,%XMM5    [5]

0x4577f4 VMOVSD	(%R10,%RSI,1),%XMM14    [3]

0x4577fa VFMSUB132SD	%XMM4,%XMM13,%XMM15

0x4577ff VMOVSD	%XMM5,(%RDX,%RSI,1)    [8]

0x457804 VADDSD	(%R8,%RSI,1),%XMM14,%XMM6    [1]

0x45780a VSUBSD	%XMM13,%XMM1,%XMM8

0x45780f VADDSD	%XMM15,%XMM6,%XMM7

0x457814 VMOVSD	%XMM7,(%R8,%RSI,1)    [1]

0x45781a VMOVSD	0x8(%R9,%RSI,1),%XMM9    [4]

0x457821 VMOVSD	0x8(%RCX,%RSI,1),%XMM10    [7]

0x457827 VADDSD	0x8(%RDX,%RSI,1),%XMM9,%XMM11    [8]

0x45782d VFMADD213SD	0x8(%RDI,%RSI,1),%XMM4,%XMM10    [2]

0x457834 VMOVSD	0x8(%RBX,%RSI,1),%XMM3    [6]

0x45783a VSUBSD	0x8(%RAX,%RSI,1),%XMM11,%XMM1    [5]

0x457840 VMOVSD	0x8(%R10,%RSI,1),%XMM0    [3]

0x457847 VFMSUB132SD	%XMM4,%XMM10,%XMM3

0x45784c VMOVSD	%XMM1,0x8(%RDX,%RSI,1)    [8]

0x457852 VADDSD	0x8(%R8,%RSI,1),%XMM0,%XMM12    [1]

0x457859 VSUBSD	%XMM10,%XMM8,%XMM14

0x45785e VADDSD	%XMM3,%XMM12,%XMM13

0x457862 VMOVSD	%XMM13,0x8(%R8,%RSI,1)    [1]

0x457869 VMOVSD	0x10(%R9,%RSI,1),%XMM15    [4]

0x457870 VMOVSD	0x10(%RCX,%RSI,1),%XMM5    [7]

0x457876 VADDSD	0x10(%RDX,%RSI,1),%XMM15,%XMM2    [8]

0x45787c VFMADD213SD	0x10(%RDI,%RSI,1),%XMM4,%XMM5    [2]

0x457883 VMOVSD	0x10(%RBX,%RSI,1),%XMM7    [6]

0x457889 VSUBSD	0x10(%RAX,%RSI,1),%XMM2,%XMM8    [5]

0x45788f VMOVSD	0x10(%R10,%RSI,1),%XMM6    [3]

0x457896 VFMSUB132SD	%XMM4,%XMM5,%XMM7

0x45789b VMOVSD	%XMM8,0x10(%RDX,%RSI,1)    [8]

0x4578a1 VADDSD	0x10(%R8,%RSI,1),%XMM6,%XMM9    [1]

0x4578a8 VSUBSD	%XMM5,%XMM14,%XMM11

0x4578ac VADDSD	%XMM7,%XMM9,%XMM10

0x4578b0 VMOVSD	%XMM10,0x10(%R8,%RSI,1)    [1]

0x4578b7 VMOVSD	0x18(%R9,%RSI,1),%XMM1    [4]

0x4578be VMOVSD	0x18(%RCX,%RSI,1),%XMM12    [7]

0x4578c4 VFMADD213SD	0x18(%RDI,%RSI,1),%XMM4,%XMM12    [2]

0x4578cb VADDSD	0x18(%RDX,%RSI,1),%XMM1,%XMM13    [8]

0x4578d1 VMOVSD	0x18(%RBX,%RSI,1),%XMM3    [6]

0x4578d7 VMOVSD	0x18(%R10,%RSI,1),%XMM0    [3]

0x4578de VSUBSD	0x18(%RAX,%RSI,1),%XMM13,%XMM14    [5]

0x4578e4 VFMSUB132SD	%XMM4,%XMM12,%XMM3

0x4578e9 VSUBSD	%XMM12,%XMM11,%XMM1

0x4578ee VMOVSD	%XMM14,0x18(%RDX,%RSI,1)    [8]

0x4578f4 VADDSD	0x18(%R8,%RSI,1),%XMM0,%XMM15    [1]

0x4578fb VADDSD	%XMM3,%XMM15,%XMM5

0x4578ff VMOVSD	%XMM5,0x18(%R8,%RSI,1)    [1]

0x457906 ADD	$0x20,%RSI

0x45790a CMP	%R15,%RSI

0x45790d JNE	4577d4

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h: 324 - 331

--------------------------------------------------------------------------------

324:   for (int jat = 0; jat < N; jat++)

325:   {

326:     const valT du   = cur_u[jat] - old_u[jat];

327:     const valT newl = cur_d2u[jat] + lapfac * cur_du[jat];

328:     const valT dl   = old_d2u[jat] + lapfac * old_du[jat] - newl;

329:     Uat[jat] += du;

330:     d2Uat[jat] += dl;

331:     cur_d2Uat -= newl;

Coverage (%)	Name	Source Location	Module
►97.34+	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main._omp_fn.1	refwrap.h:350	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►2.66+	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main._omp_fn.1	refwrap.h:350	exec
○	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.31
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	P1,
Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source	TwoBodyJastrowRef.h:324-331
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.00
CQA cycles if no scalar integer	14.00
CQA cycles if FP arith vectorized	10.67
CQA cycles if fully vectorized	1.75
Front-end cycles	11.67
P0 cycles	7.50
P1 cycles	14.00
P2 cycles	10.67
P3 cycles	10.67
P4 cycles	4.00
P5 cycles	10.00
P6 cycles	1.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.00
P11 cycles	10.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	12
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	55.00
Nb uops	54.00
Nb loads	32.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	2.57
Nb FLOP add-sub	20.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.86
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	8.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.31
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	P1,
Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source	TwoBodyJastrowRef.h:324-331
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.00
CQA cycles if no scalar integer	14.00
CQA cycles if FP arith vectorized	10.67
CQA cycles if fully vectorized	1.75
Front-end cycles	11.67
P0 cycles	7.50
P1 cycles	14.00
P2 cycles	10.67
P3 cycles	10.67
P4 cycles	4.00
P5 cycles	10.00
P6 cycles	1.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.00
P11 cycles	10.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	12
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	55.00
Nb uops	54.00
Nb loads	32.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	2.57
Nb FLOP add-sub	20.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.86
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	8.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source file and lines	TwoBodyJastrowRef.h:324-331
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:324-331.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 14.00 to 1.75 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 14.00 to 11.67 cycles (1.20x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 8 FMA (fused multiply-add) operations.

Type of elements and instruction set

28 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 36 FP arithmetical operations:

28: addition or subtraction (8 inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 256 bytes (32 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	55
nb uops	54
loop length	319
used x86 registers	10
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	11.67 cycles
front end	11.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.50	10.50	10.67	10.67	4.00	10.00	1.00	4.00	4.00	4.00	0.00	10.67
cycles	7.50	14.00	10.67	10.67	4.00	10.00	1.00	4.00	4.00	4.00	0.00	10.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	12.00

Cycles summary

Front-end	11.67
Dispatch	14.00
Data deps.	12.00
Overall L1	14.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.00 cycles. At this rate:

9% of peak load performance is reached (18.29 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.57 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4577d4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVSD (%R9,%RSI,1),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RCX,%RSI,1),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%RDX,%RSI,1),%XMM12,%XMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VFMADD213SD (%RDI,%RSI,1),%XMM4,%XMM13	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RBX,%RSI,1),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VSUBSD (%RAX,%RSI,1),%XMM2,%XMM5	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD (%R10,%RSI,1),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMSUB132SD %XMM4,%XMM13,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM5,(%RDX,%RSI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD (%R8,%RSI,1),%XMM14,%XMM6	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VSUBSD %XMM13,%XMM1,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM15,%XMM6,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM7,(%R8,%RSI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%R9,%RSI,1),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x8(%RCX,%RSI,1),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD 0x8(%RDX,%RSI,1),%XMM9,%XMM11	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VFMADD213SD 0x8(%RDI,%RSI,1),%XMM4,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x8(%RBX,%RSI,1),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VSUBSD 0x8(%RAX,%RSI,1),%XMM11,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD 0x8(%R10,%RSI,1),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMSUB132SD %XMM4,%XMM10,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,0x8(%RDX,%RSI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD 0x8(%R8,%RSI,1),%XMM0,%XMM12	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VSUBSD %XMM10,%XMM8,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM3,%XMM12,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM13,0x8(%R8,%RSI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x10(%R9,%RSI,1),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x10(%RCX,%RSI,1),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD 0x10(%RDX,%RSI,1),%XMM15,%XMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VFMADD213SD 0x10(%RDI,%RSI,1),%XMM4,%XMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x10(%RBX,%RSI,1),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VSUBSD 0x10(%RAX,%RSI,1),%XMM2,%XMM8	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD 0x10(%R10,%RSI,1),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMSUB132SD %XMM4,%XMM5,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM8,0x10(%RDX,%RSI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD 0x10(%R8,%RSI,1),%XMM6,%XMM9	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VSUBSD %XMM5,%XMM14,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM7,%XMM9,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM10,0x10(%R8,%RSI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x18(%R9,%RSI,1),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x18(%RCX,%RSI,1),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x18(%RDI,%RSI,1),%XMM4,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VADDSD 0x18(%RDX,%RSI,1),%XMM1,%XMM13	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD 0x18(%RBX,%RSI,1),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x18(%R10,%RSI,1),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VSUBSD 0x18(%RAX,%RSI,1),%XMM13,%XMM14	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VFMSUB132SD %XMM4,%XMM12,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM12,%XMM11,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM14,0x18(%RDX,%RSI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD 0x18(%R8,%RSI,1),%XMM0,%XMM15	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VADDSD %XMM3,%XMM15,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM5,0x18(%R8,%RSI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $0x20,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 4577d4 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi+0x204>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source file and lines	TwoBodyJastrowRef.h:324-331
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 14.00 to 1.75 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 8 FMA (fused multiply-add) operations.

Type of elements and instruction set

28 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 36 FP arithmetical operations:

28: addition or subtraction (8 inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 256 bytes (32 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	55
nb uops	54
loop length	319
used x86 registers	10
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	11.67 cycles
front end	11.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.50	10.50	10.67	10.67	4.00	10.00	1.00	4.00	4.00	4.00	0.00	10.67
cycles	7.50	14.00	10.67	10.67	4.00	10.00	1.00	4.00	4.00	4.00	0.00	10.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	12.00

Cycles summary

Front-end	11.67
Dispatch	14.00
Data deps.	12.00
Overall L1	14.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.00 cycles. At this rate:

9% of peak load performance is reached (18.29 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.57 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4577d4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVSD (%R9,%RSI,1),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RCX,%RSI,1),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%RDX,%RSI,1),%XMM12,%XMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VFMADD213SD (%RDI,%RSI,1),%XMM4,%XMM13	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RBX,%RSI,1),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VSUBSD (%RAX,%RSI,1),%XMM2,%XMM5	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD (%R10,%RSI,1),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMSUB132SD %XMM4,%XMM13,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM5,(%RDX,%RSI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD (%R8,%RSI,1),%XMM14,%XMM6	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VSUBSD %XMM13,%XMM1,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM15,%XMM6,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM7,(%R8,%RSI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%R9,%RSI,1),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x8(%RCX,%RSI,1),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD 0x8(%RDX,%RSI,1),%XMM9,%XMM11	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VFMADD213SD 0x8(%RDI,%RSI,1),%XMM4,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x8(%RBX,%RSI,1),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VSUBSD 0x8(%RAX,%RSI,1),%XMM11,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD 0x8(%R10,%RSI,1),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMSUB132SD %XMM4,%XMM10,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,0x8(%RDX,%RSI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD 0x8(%R8,%RSI,1),%XMM0,%XMM12	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VSUBSD %XMM10,%XMM8,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM3,%XMM12,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM13,0x8(%R8,%RSI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x10(%R9,%RSI,1),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x10(%RCX,%RSI,1),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD 0x10(%RDX,%RSI,1),%XMM15,%XMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VFMADD213SD 0x10(%RDI,%RSI,1),%XMM4,%XMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x10(%RBX,%RSI,1),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VSUBSD 0x10(%RAX,%RSI,1),%XMM2,%XMM8	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD 0x10(%R10,%RSI,1),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMSUB132SD %XMM4,%XMM5,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM8,0x10(%RDX,%RSI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD 0x10(%R8,%RSI,1),%XMM6,%XMM9	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VSUBSD %XMM5,%XMM14,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM7,%XMM9,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM10,0x10(%R8,%RSI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x18(%R9,%RSI,1),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x18(%RCX,%RSI,1),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x18(%RDI,%RSI,1),%XMM4,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VADDSD 0x18(%RDX,%RSI,1),%XMM1,%XMM13	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD 0x18(%RBX,%RSI,1),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x18(%R10,%RSI,1),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VSUBSD 0x18(%RAX,%RSI,1),%XMM13,%XMM14	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VFMSUB132SD %XMM4,%XMM12,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM12,%XMM11,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM14,0x18(%RDX,%RSI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD 0x18(%R8,%RSI,1),%XMM0,%XMM15	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VADDSD %XMM3,%XMM15,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM5,0x18(%R8,%RSI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $0x20,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 4577d4 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi+0x204>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code