OV - exec - Loop 616

	Loop Id: 616	Module: exec	Source: BsplineFunctor.h:305-336 [...]	Coverage: 0.02%

0x456910 VMOVAPD	(%R15,%RDX,2),%YMM10    [6]

0x456916 VMOVAPD	0x20(%R15,%RDX,2),%YMM9    [6]

0x45691d VMULPD	%YMM18,%YMM10,%YMM0

0x456923 VMULPD	%YMM18,%YMM9,%YMM1

0x456929 KMOVB	%K2,%K1

0x45692d KMOVB	%K2,%K5

0x456931 KMOVB	%K2,%K3

0x456935 VRNDSCALEPD	$0xb,%YMM0,%YMM7

0x45693c VRNDSCALEPD	$0xb,%YMM1,%YMM11

0x456943 VCVTTPD2DQ	%YMM0,%XMM5

0x456947 VCVTTPD2DQ	%YMM1,%XMM2

0x45694b VINSERTI32X4	$0x1,%XMM2,%YMM5,%YMM6

0x456952 VPADDD	0x160326(%RIP),%YMM6,%YMM12    [5]

0x45695a VPADDD	0x16033e(%RIP),%YMM6,%YMM15    [5]

0x456962 VPERM2I128	$0x11,%YMM6,%YMM6,%YMM13

0x456968 VPADDD	0x160350(%RIP),%YMM6,%YMM6    [5]

0x456970 VSUBPD	%YMM7,%YMM0,%YMM0

0x456974 VPERM2I128	$0x11,%YMM12,%YMM12,%YMM7

0x45697a VSUBPD	%YMM11,%YMM1,%YMM1

0x45697f VGATHERDPD	(%RAX,%XMM5,8),%YMM22{%K1}    [8]

0x456986 VGATHERDPD	(%RAX,%XMM7,8),%YMM5{%K5}    [8]

0x45698d KMOVB	%K2,%K1

0x456991 VPERM2I128	$0x11,%YMM6,%YMM6,%YMM7

0x456997 VGATHERDPD	(%RAX,%XMM6,8),%YMM20{%K1}    [8]

0x45699e VMOVAPD	0x4c0(%RSP),%YMM6    [7]

0x4569a7 VGATHERDPD	(%RAX,%XMM13,8),%YMM21{%K3}    [8]

0x4569ae KMOVB	%K2,%K4

0x4569b2 VPERM2I128	$0x11,%YMM15,%YMM15,%YMM13

0x4569b8 VGATHERDPD	(%RAX,%XMM12,8),%YMM23{%K4}    [8]

0x4569bf KMOVB	%K2,%K6

0x4569c3 VGATHERDPD	(%RAX,%XMM15,8),%YMM12{%K6}    [8]

0x4569ca VMOVAPD	0x4a0(%RSP),%YMM15    [7]

0x4569d3 VMOVAPD	0x480(%RSP),%YMM8    [7]

0x4569dc KMOVB	%K2,%K7

0x4569e0 KMOVB	%K2,%K3

0x4569e4 VGATHERDPD	(%RAX,%XMM13,8),%YMM11{%K7}    [8]

0x4569eb VGATHERDPD	(%RAX,%XMM7,8),%YMM13{%K3}    [8]

0x4569f2 VMOVAPD	%YMM6,%YMM7

0x4569f6 VFMADD132PD	%YMM0,%YMM15,%YMM7

0x4569fb VFMADD132PD	%YMM1,%YMM15,%YMM6

0x456a00 VMOVAPD	0x460(%RSP),%YMM15    [7]

0x456a09 VMOVAPD	%YMM8,%YMM14

0x456a0e VFMADD132PD	%YMM0,%YMM15,%YMM14

0x456a13 VFMADD132PD	%YMM1,%YMM15,%YMM8

0x456a18 VMOVAPD	0x440(%RSP),%YMM15    [7]

0x456a21 VMOVAPD	0x3e0(%RSP),%YMM24    [7]

0x456a29 VMOVAPD	%YMM15,%YMM19

0x456a2f VMULPD	%YMM14,%YMM23,%YMM14

0x456a35 VMULPD	%YMM8,%YMM5,%YMM8

0x456a3a VMOVDQA	(%R12,%RDX,1),%YMM4    [3]

0x456a40 KMOVB	%K2,%K4

0x456a44 KMOVB	%K2,%K5

0x456a48 VFMADD132PD	%YMM22,%YMM14,%YMM7

0x456a4e VFMADD132PD	%YMM21,%YMM8,%YMM6

0x456a54 VMOVAPD	0x420(%RSP),%YMM14    [7]

0x456a5d VMOVAPD	0x400(%RSP),%YMM8    [7]

0x456a66 VFMADD132PD	%YMM0,%YMM14,%YMM19

0x456a6c VFMADD132PD	%YMM1,%YMM14,%YMM15

0x456a71 VMOVAPD	%YMM8,%YMM14

0x456a76 VFMADD132PD	%YMM0,%YMM24,%YMM14

0x456a7c VFMADD132PD	%YMM1,%YMM24,%YMM8

0x456a82 VMULPD	%YMM0,%YMM0,%YMM3

0x456a86 VMULPD	%YMM1,%YMM1,%YMM2

0x456a8a KMOVB	%K2,%K6

0x456a8e VMULPD	%YMM14,%YMM20,%YMM14

0x456a94 VMULPD	%YMM8,%YMM13,%YMM8

0x456a99 KMOVB	%K2,%K7

0x456a9d VMULPD	%YMM3,%YMM0,%YMM17

0x456aa3 VMULPD	%YMM2,%YMM1,%YMM16

0x456aa9 VFMADD231PD	%YMM19,%YMM12,%YMM14

0x456aaf VFMADD231PD	%YMM15,%YMM11,%YMM8

0x456ab4 VMOVAPD	0x3c0(%RSP),%YMM15    [7]

0x456abd VMOVDQA32	%XMM4,%XMM19

0x456ac3 ADD	$0x20,%RDX

0x456ac7 VADDPD	%YMM14,%YMM7,%YMM7

0x456acc VADDPD	%YMM8,%YMM6,%YMM6

0x456ad1 KMOVB	%K2,%K1

0x456ad5 VMULPD	%YMM15,%YMM7,%YMM14

0x456ada VMULPD	%YMM15,%YMM6,%YMM8

0x456adf VBROADCASTSD	0x160288(%RIP),%YMM7    [5]

0x456ae8 KMOVB	%K2,%K3

0x456aec VDIVPD	%YMM10,%YMM7,%YMM10

0x456af1 VSCATTERDPD	%YMM14,(%R8,%XMM4,8){%K4}    [1]

0x456af8 VPERM2I128	$0x11,%YMM4,%YMM4,%YMM4

0x456afe VSCATTERDPD	%YMM8,(%R8,%XMM4,8){%K5}    [1]

0x456b05 VMOVAPD	0x380(%RSP),%YMM6    [7]

0x456b0e VMOVAPD	0x360(%RSP),%YMM15    [7]

0x456b17 VMOVAPD	0x3a0(%RSP),%YMM14    [7]

0x456b20 VMOVAPD	0x320(%RSP),%YMM8    [7]

0x456b29 VDIVPD	%YMM9,%YMM7,%YMM9

0x456b2e VMOVAPD	%YMM6,%YMM7

0x456b32 VFMADD132PD	%YMM0,%YMM15,%YMM7

0x456b37 VFMADD132PD	%YMM1,%YMM15,%YMM6

0x456b3c VMOVAPD	0x300(%RSP),%YMM15    [7]

0x456b45 VFMADD231PD	%YMM14,%YMM3,%YMM7

0x456b4a VFMADD231PD	%YMM14,%YMM2,%YMM6

0x456b4f VMOVAPD	%YMM8,%YMM14

0x456b54 VFMADD132PD	%YMM0,%YMM15,%YMM14

0x456b59 VFMADD132PD	%YMM1,%YMM15,%YMM8

0x456b5e VMOVAPD	0x340(%RSP),%YMM15    [7]

0x456b67 VMULPD	%YMM18,%YMM10,%YMM10

0x456b6d VFMADD231PD	%YMM15,%YMM3,%YMM14

0x456b72 VFMADD231PD	%YMM15,%YMM2,%YMM8

0x456b77 VMULPD	%YMM14,%YMM23,%YMM14

0x456b7d VMULPD	%YMM8,%YMM5,%YMM8

0x456b82 VFMADD132PD	%YMM22,%YMM14,%YMM7

0x456b88 VMOVAPD	0x2c0(%RSP),%YMM14    [7]

0x456b91 VMOVAPD	0x2a0(%RSP),%YMM15    [7]

0x456b9a VMOVAPD	%YMM14,%YMM24

0x456ba0 VFMADD132PD	%YMM0,%YMM15,%YMM24

0x456ba6 VFMADD132PD	%YMM1,%YMM15,%YMM14

0x456bab VFMADD132PD	%YMM21,%YMM8,%YMM6

0x456bb1 VMOVAPD	0x280(%RSP),%YMM15    [7]

0x456bba VMOVAPD	0x2e0(%RSP),%YMM8    [7]

0x456bc3 VMULPD	%YMM18,%YMM9,%YMM9

0x456bc9 VFMADD231PD	%YMM8,%YMM3,%YMM24

0x456bcf VFMADD231PD	%YMM8,%YMM2,%YMM14

0x456bd4 VMOVAPD	%YMM15,%YMM8

0x456bd9 VFMADD213PD	0x4e0(%RSP),%YMM0,%YMM8    [7]

0x456be3 VFMADD213PD	0x4e0(%RSP),%YMM1,%YMM15    [7]

0x456bed VFMADD231PD	0x500(%RSP),%YMM3,%YMM8    [7]

0x456bf7 VFMADD231PD	0x500(%RSP),%YMM2,%YMM15    [7]

0x456c01 VMULPD	%YMM8,%YMM20,%YMM8

0x456c07 VMULPD	%YMM15,%YMM13,%YMM15

0x456c0c VFMADD231PD	%YMM24,%YMM12,%YMM8

0x456c12 VFMADD132PD	%YMM11,%YMM15,%YMM14

0x456c17 VADDPD	%YMM8,%YMM7,%YMM7

0x456c1c VADDPD	%YMM14,%YMM6,%YMM6

0x456c21 VMULPD	%YMM10,%YMM7,%YMM10

0x456c26 VMULPD	%YMM9,%YMM6,%YMM9

0x456c2b VSCATTERDPD	%YMM10,(%RDI,%XMM19,8){%K6}    [4]

0x456c32 VSCATTERDPD	%YMM9,(%RDI,%XMM4,8){%K7}    [4]

0x456c39 VMOVAPD	0x240(%RSP),%YMM14    [7]

0x456c42 VMOVAPD	0x220(%RSP),%YMM7    [7]

0x456c4b VMULPD	%YMM14,%YMM3,%YMM8

0x456c50 VMOVAPD	0x260(%RSP),%YMM15    [7]

0x456c59 VMOVAPD	0x200(%RSP),%YMM10    [7]

0x456c62 VMULPD	%YMM14,%YMM2,%YMM6

0x456c67 VMOVAPD	%YMM7,%YMM9

0x456c6b VMOVAPD	0x1c0(%RSP),%YMM14    [7]

0x456c74 VFMADD231PD	%YMM15,%YMM17,%YMM8

0x456c7a VFMADD132PD	%YMM0,%YMM10,%YMM9

0x456c7f VFMADD132PD	%YMM1,%YMM10,%YMM7

0x456c84 VMULPD	%YMM14,%YMM3,%YMM10

0x456c89 VMULPD	%YMM14,%YMM2,%YMM14

0x456c8e VFMADD231PD	%YMM15,%YMM16,%YMM6

0x456c94 VADDPD	%YMM8,%YMM9,%YMM9

0x456c99 VMOVAPD	0x1e0(%RSP),%YMM8    [7]

0x456ca2 VMOVAPD	0x180(%RSP),%YMM15    [7]

0x456cab VFMADD231PD	%YMM8,%YMM17,%YMM10

0x456cb1 VFMADD231PD	%YMM8,%YMM16,%YMM14

0x456cb7 VMOVAPD	0x1a0(%RSP),%YMM8    [7]

0x456cc0 VADDPD	%YMM6,%YMM7,%YMM7

0x456cc4 VMOVAPD	%YMM8,%YMM6

0x456cc8 VFMADD132PD	%YMM0,%YMM15,%YMM6

0x456ccd VFMADD132PD	%YMM1,%YMM15,%YMM8

0x456cd2 VMOVAPD	0x160(%RSP),%YMM15    [7]

0x456cdb VADDPD	%YMM10,%YMM6,%YMM10

0x456ce0 VADDPD	%YMM14,%YMM8,%YMM14

0x456ce5 VMOVAPD	%YMM15,%YMM8

0x456cea VMULPD	%YMM23,%YMM10,%YMM6

0x456cf0 VMULPD	%YMM14,%YMM5,%YMM5

0x456cf5 VFMADD231PD	%YMM29,%YMM0,%YMM8

0x456cfb VFMADD231PD	%YMM29,%YMM1,%YMM15

0x456d01 VFMADD132PD	%YMM26,%YMM25,%YMM0

0x456d07 VFMADD231PD	%YMM9,%YMM22,%YMM6

0x456d0d VFMADD231PD	%YMM7,%YMM21,%YMM5

0x456d13 VMULPD	%YMM30,%YMM3,%YMM9

0x456d19 VMULPD	%YMM30,%YMM2,%YMM7

0x456d1f VMULPD	%YMM27,%YMM3,%YMM3

0x456d25 VMULPD	%YMM27,%YMM2,%YMM2

0x456d2b VFMADD132PD	%YMM26,%YMM25,%YMM1

0x456d31 VFMADD231PD	%YMM31,%YMM17,%YMM9

0x456d37 VFMADD231PD	%YMM31,%YMM16,%YMM7

0x456d3d VFMADD231PD	%YMM28,%YMM17,%YMM3

0x456d43 VFMADD231PD	%YMM28,%YMM16,%YMM2

0x456d49 VADDPD	%YMM9,%YMM8,%YMM14

0x456d4e VADDPD	%YMM7,%YMM15,%YMM10

0x456d52 VADDPD	%YMM3,%YMM0,%YMM0

0x456d56 VADDPD	%YMM1,%YMM2,%YMM1

0x456d5a VMULPD	%YMM20,%YMM0,%YMM9

0x456d60 VMULPD	%YMM1,%YMM13,%YMM13

0x456d64 VFMADD132PD	%YMM14,%YMM9,%YMM12

0x456d69 VFMADD132PD	%YMM10,%YMM13,%YMM11

0x456d6e VADDPD	%YMM12,%YMM6,%YMM12

0x456d73 VADDPD	%YMM11,%YMM5,%YMM11

0x456d78 VSCATTERDPD	%YMM12,(%RSI,%XMM19,8){%K1}    [2]

0x456d7f VSCATTERDPD	%YMM11,(%RSI,%XMM4,8){%K3}    [2]

0x456d86 CMP	%RDX,%R9

0x456d89 JNE	456910

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h: 1147 - 1147

--------------------------------------------------------------------------------

1147:       operator[](size_type __n) const _GLIBCXX_NOEXCEPT

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 305 - 336

--------------------------------------------------------------------------------

305:     real_type r    = distArrayCompressed[j];

306:     int iScatter   = distIndices[j];

307:     real_type rinv = cOne / r;

308:     r *= DeltaRInv;

309:     int iGather   = (int)r;

310:     real_type t   = r - real_type(iGather);

311:     real_type tp0 = t * t * t;

312:     real_type tp1 = t * t;

313:     real_type tp2 = t;

314:

315:     real_type sCoef0 = SplineCoefs[iGather + 0];

316:     real_type sCoef1 = SplineCoefs[iGather + 1];

317:     real_type sCoef2 = SplineCoefs[iGather + 2];

318:     real_type sCoef3 = SplineCoefs[iGather + 3];

319:

320:     // clang-format off

321:     laplArray[iScatter] = dSquareDeltaRinv *

322:       (sCoef0*( d2A[ 2]*tp2 + d2A[ 3])+

323:        sCoef1*( d2A[ 6]*tp2 + d2A[ 7])+

324:        sCoef2*( d2A[10]*tp2 + d2A[11])+

325:        sCoef3*( d2A[14]*tp2 + d2A[15]));

326:

327:     gradArray[iScatter] = DeltaRInv * rinv *

328:       (sCoef0*( dA[ 1]*tp1 + dA[ 2]*tp2 + dA[ 3])+

329:        sCoef1*( dA[ 5]*tp1 + dA[ 6]*tp2 + dA[ 7])+

330:        sCoef2*( dA[ 9]*tp1 + dA[10]*tp2 + dA[11])+

331:        sCoef3*( dA[13]*tp1 + dA[14]*tp2 + dA[15]));

332:

333:     valArray[iScatter] = (sCoef0*(A[ 0]*tp0 + A[ 1]*tp1 + A[ 2]*tp2 + A[ 3])+

334:         sCoef1*(A[ 4]*tp0 + A[ 5]*tp1 + A[ 6]*tp2 + A[ 7])+

335:         sCoef2*(A[ 8]*tp0 + A[ 9]*tp1 + A[10]*tp2 + A[11])+

336:         sCoef3*(A[12]*tp0 + A[13]*tp1 + A[14]*tp2 + A[15]));

Coverage (%)	Name	Source Location	Module
►98.02+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:315	exec
○	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main._omp_fn.1	refwrap.h:350	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►1.98+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:315	exec
○	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main._omp_fn.1	refwrap.h:350	exec
○	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.12
CQA speedup if FP arith vectorized	1.59
CQA speedup if fully vectorized	2.20
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.39
Bottlenecks	P0, P1,
Function	miniqmcreference::TwoBodyJastrowRef >::computeU3(qmcplusplus::ParticleSet const&, int, double const, double, double, double, bool)
Source	stl_vector.h:1147-1147,BsplineFunctor.h:305-336
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	67.50
CQA cycles if no scalar integer	60.50
CQA cycles if FP arith vectorized	42.50
CQA cycles if fully vectorized	30.75
Front-end cycles	48.50
P0 cycles	67.50
P1 cycles	67.50
P2 cycles	23.67
P3 cycles	23.67
P4 cycles	12.00
P5 cycles	34.00
P6 cycles	3.60
P7 cycles	12.00
P8 cycles	12.00
P9 cycles	12.00
P10 cycles	3.40
P11 cycles	23.67
DIV/SQRT cycles	16.00
Inter-iter dependencies cycles	28
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	190.00
Nb uops	291.00
Nb loads	47.00
Nb stores	6.00
Nb stack references	30.00
FLOP/cycle	9.13
Nb FLOP add-sub	64.00
Nb FLOP mul	128.00
Nb FLOP fma	208.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.77
Bytes prefetched	0.00
Bytes loaded	1480.00
Bytes stored	192.00
Stride 0	2.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	4.00
Vectorization ratio all	99.42
Vectorization ratio load	97.87
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	96.77
Vector-efficiency ratio all	48.77
Vector-efficiency ratio load	49.20
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	43.15

Metric	Value
CQA speedup if no scalar integer	1.12
CQA speedup if FP arith vectorized	1.59
CQA speedup if fully vectorized	2.20
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.39
Bottlenecks	P0, P1,
Function	miniqmcreference::TwoBodyJastrowRef >::computeU3(qmcplusplus::ParticleSet const&, int, double const, double, double, double, bool)
Source	stl_vector.h:1147-1147,BsplineFunctor.h:305-336
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	67.50
CQA cycles if no scalar integer	60.50
CQA cycles if FP arith vectorized	42.50
CQA cycles if fully vectorized	30.75
Front-end cycles	48.50
P0 cycles	67.50
P1 cycles	67.50
P2 cycles	23.67
P3 cycles	23.67
P4 cycles	12.00
P5 cycles	34.00
P6 cycles	3.60
P7 cycles	12.00
P8 cycles	12.00
P9 cycles	12.00
P10 cycles	3.40
P11 cycles	23.67
DIV/SQRT cycles	16.00
Inter-iter dependencies cycles	28
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	190.00
Nb uops	291.00
Nb loads	47.00
Nb stores	6.00
Nb stack references	30.00
FLOP/cycle	9.13
Nb FLOP add-sub	64.00
Nb FLOP mul	128.00
Nb FLOP fma	208.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.77
Bytes prefetched	0.00
Bytes loaded	1480.00
Bytes stored	192.00
Stride 0	2.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	4.00
Vectorization ratio all	99.42
Vectorization ratio load	97.87
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	96.77
Vector-efficiency ratio all	48.77
Vector-efficiency ratio load	49.20
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	43.15

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::computeU3(qmcplusplus::ParticleSet const&, int, double const, double, double, double, bool)
Source file and lines	BsplineFunctor.h:305-336
Module	exec

The loop is defined in:

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:1147
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:305-336

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 67.50 to 60.50 cycles (1.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is highly vectorized. Only 48% of vector register length is used (average across all SSE/AVX instructions).

Details

99% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

97% of SSE/AVX loads are used in vector version.
96% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 67.50 to 48.50 cycles (1.39x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 208 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTPD2DQ: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309
VGATHERDPD: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:315
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:316
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:318
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:315
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:316
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:317
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:317
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:318
VRNDSCALEPD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:310
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:310
VSCATTERDPD: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:327
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:327
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPD: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:315
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:316
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:318
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:315
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:316
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:317
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:317
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:318
VSCATTERDPD: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:327
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:327
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

104 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 616 FP arithmetical operations:

272: addition or subtraction (208 inside FMA instructions)
336: multiply (208 inside FMA instructions)
8: divide

The binary loop is loading 1480 bytes (185 double precision FP elements). The binary loop is storing 192 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.37 FP operations per loaded or stored byte.

General properties

nb instructions	190
nb uops	291
loop length	1151
used x86 registers	9
used mmx registers	0
used xmm registers	9
used ymm registers	32
used zmm registers	0
nb stack references	30
ADD-SUB / MUL ratio	0.50

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	48.50 cycles
front end	48.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	67.50	67.50	23.67	23.67	12.00	34.00	3.60	12.00	12.00	12.00	3.40	23.67
cycles	67.50	67.50	23.67	23.67	12.00	34.00	3.60	12.00	12.00	12.00	3.40	23.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	16.00
Longest recurrence chain latency (RecMII)	28.00

Cycles summary

Front-end	48.50
Dispatch	67.50
DIV/SQRT	16.00
Data deps.	28.00
Overall L1	67.50

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	99%
load	97%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	95%

INT+FP

all	99%
load	97%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	96%

Vector efficiency ratios

INT

all	34%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	49%
load	49%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	48%

INT+FP

all	48%
load	49%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	43%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 67.50 cycles. At this rate:

11% of peak load performance is reached (21.93 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.84 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 456910

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVAPD (%R15,%RDX,2),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x20(%R15,%RDX,2),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM18,%YMM10,%YMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM18,%YMM9,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
KMOVB %K2,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K2,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K2,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VRNDSCALEPD $0xb,%YMM0,%YMM7	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VRNDSCALEPD $0xb,%YMM1,%YMM11	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VCVTTPD2DQ %YMM0,%XMM5	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	vect (50.0%)
VCVTTPD2DQ %YMM1,%XMM2	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	vect (50.0%)
VINSERTI32X4 $0x1,%XMM2,%YMM5,%YMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPADDD 0x160326(%RIP),%YMM6,%YMM12	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPADDD 0x16033e(%RIP),%YMM6,%YMM15	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPERM2I128 $0x11,%YMM6,%YMM6,%YMM13	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPADDD 0x160350(%RIP),%YMM6,%YMM6	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VSUBPD %YMM7,%YMM0,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPERM2I128 $0x11,%YMM12,%YMM12,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSUBPD %YMM11,%YMM1,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VGATHERDPD (%RAX,%XMM5,8),%YMM22{%K1}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VGATHERDPD (%RAX,%XMM7,8),%YMM5{%K5}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
KMOVB %K2,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VPERM2I128 $0x11,%YMM6,%YMM6,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VGATHERDPD (%RAX,%XMM6,8),%YMM20{%K1}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VMOVAPD 0x4c0(%RSP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VGATHERDPD (%RAX,%XMM13,8),%YMM21{%K3}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
KMOVB %K2,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VPERM2I128 $0x11,%YMM15,%YMM15,%YMM13	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VGATHERDPD (%RAX,%XMM12,8),%YMM23{%K4}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
KMOVB %K2,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERDPD (%RAX,%XMM15,8),%YMM12{%K6}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VMOVAPD 0x4a0(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x480(%RSP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
KMOVB %K2,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K2,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERDPD (%RAX,%XMM13,8),%YMM11{%K7}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VGATHERDPD (%RAX,%XMM7,8),%YMM13{%K3}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VMOVAPD %YMM6,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD132PD %YMM0,%YMM15,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM15,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x460(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD %YMM8,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD132PD %YMM0,%YMM15,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM15,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x440(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x3e0(%RSP),%YMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD %YMM15,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMULPD %YMM14,%YMM23,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM8,%YMM5,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVDQA (%R12,%RDX,1),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
KMOVB %K2,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K2,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VFMADD132PD %YMM22,%YMM14,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM21,%YMM8,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x420(%RSP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x400(%RSP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD132PD %YMM0,%YMM14,%YMM19	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM14,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM8,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD132PD %YMM0,%YMM24,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM24,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM0,%YMM0,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM1,%YMM1,%YMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
KMOVB %K2,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMULPD %YMM14,%YMM20,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM8,%YMM13,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
KMOVB %K2,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMULPD %YMM3,%YMM0,%YMM17	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM2,%YMM1,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM19,%YMM12,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM11,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x3c0(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVDQA32 %XMM4,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ADD $0x20,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %YMM14,%YMM7,%YMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM8,%YMM6,%YMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K2,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMULPD %YMM15,%YMM7,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM15,%YMM6,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x160288(%RIP),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
KMOVB %K2,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VDIVPD %YMM10,%YMM7,%YMM10	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VSCATTERDPD %YMM14,(%R8,%XMM4,8){%K4}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (50.0%)
VPERM2I128 $0x11,%YMM4,%YMM4,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSCATTERDPD %YMM8,(%R8,%XMM4,8){%K5}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (50.0%)
VMOVAPD 0x380(%RSP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x360(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x3a0(%RSP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x320(%RSP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VDIVPD %YMM9,%YMM7,%YMM9	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMOVAPD %YMM6,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD132PD %YMM0,%YMM15,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM15,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x300(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD231PD %YMM14,%YMM3,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM14,%YMM2,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM8,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD132PD %YMM0,%YMM15,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM15,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x340(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM18,%YMM10,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM3,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM2,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM14,%YMM23,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM8,%YMM5,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM22,%YMM14,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x2c0(%RSP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x2a0(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD %YMM14,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD132PD %YMM0,%YMM15,%YMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM15,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM21,%YMM8,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x280(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x2e0(%RSP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM18,%YMM9,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM8,%YMM3,%YMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM8,%YMM2,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM15,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD213PD 0x4e0(%RSP),%YMM0,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PD 0x4e0(%RSP),%YMM1,%YMM15	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x500(%RSP),%YMM3,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x500(%RSP),%YMM2,%YMM15	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VMULPD %YMM8,%YMM20,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM15,%YMM13,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM12,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM11,%YMM15,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM8,%YMM7,%YMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM14,%YMM6,%YMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM10,%YMM7,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM9,%YMM6,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VSCATTERDPD %YMM10,(%RDI,%XMM19,8){%K6}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (50.0%)
VSCATTERDPD %YMM9,(%RDI,%XMM4,8){%K7}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (50.0%)
VMOVAPD 0x240(%RSP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x220(%RSP),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM14,%YMM3,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x260(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x200(%RSP),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM14,%YMM2,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM7,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD 0x1c0(%RSP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD231PD %YMM15,%YMM17,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM0,%YMM10,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM10,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM14,%YMM3,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM14,%YMM2,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM16,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM8,%YMM9,%YMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD 0x1e0(%RSP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x180(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD231PD %YMM8,%YMM17,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM8,%YMM16,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x1a0(%RSP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD %YMM6,%YMM7,%YMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM8,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD132PD %YMM0,%YMM15,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM15,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x160(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD %YMM10,%YMM6,%YMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM14,%YMM8,%YMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM15,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMULPD %YMM23,%YMM10,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM14,%YMM5,%YMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM29,%YMM0,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM29,%YMM1,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM26,%YMM25,%YMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM9,%YMM22,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM7,%YMM21,%YMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM30,%YMM3,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM30,%YMM2,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM27,%YMM3,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM27,%YMM2,%YMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM26,%YMM25,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM31,%YMM17,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM31,%YMM16,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM28,%YMM17,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM28,%YMM16,%YMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM9,%YMM8,%YMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM7,%YMM15,%YMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM3,%YMM0,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM1,%YMM2,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM20,%YMM0,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM1,%YMM13,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM14,%YMM9,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM10,%YMM13,%YMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM12,%YMM6,%YMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM11,%YMM5,%YMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSCATTERDPD %YMM12,(%RSI,%XMM19,8){%K1}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (50.0%)
VSCATTERDPD %YMM11,(%RSI,%XMM4,8){%K3}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (50.0%)
CMP %RDX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 456910 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0x860>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	miniqmcreference::TwoBodyJastrowRef >::computeU3(qmcplusplus::ParticleSet const&, int, double const, double, double, double, bool)
Source file and lines	BsplineFunctor.h:305-336
Module	exec

The loop is defined in:

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:1147
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:305-336

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is highly vectorized. Only 48% of vector register length is used (average across all SSE/AVX instructions).

Details

99% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

97% of SSE/AVX loads are used in vector version.
96% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 208 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTPD2DQ: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309
VGATHERDPD: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:315
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:316
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:318
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:315
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:316
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:317
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:317
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:318
VRNDSCALEPD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:310
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:310
VSCATTERDPD: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:327
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:327
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPD: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:315
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:316
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:318
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:315
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:316
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:317
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:317
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:318
VSCATTERDPD: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:327
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:327
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

104 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 616 FP arithmetical operations:

272: addition or subtraction (208 inside FMA instructions)
336: multiply (208 inside FMA instructions)
8: divide

The binary loop is loading 1480 bytes (185 double precision FP elements). The binary loop is storing 192 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.37 FP operations per loaded or stored byte.

General properties

nb instructions	190
nb uops	291
loop length	1151
used x86 registers	9
used mmx registers	0
used xmm registers	9
used ymm registers	32
used zmm registers	0
nb stack references	30
ADD-SUB / MUL ratio	0.50

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	48.50 cycles
front end	48.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	67.50	67.50	23.67	23.67	12.00	34.00	3.60	12.00	12.00	12.00	3.40	23.67
cycles	67.50	67.50	23.67	23.67	12.00	34.00	3.60	12.00	12.00	12.00	3.40	23.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	16.00
Longest recurrence chain latency (RecMII)	28.00

Cycles summary

Front-end	48.50
Dispatch	67.50
DIV/SQRT	16.00
Data deps.	28.00
Overall L1	67.50

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	99%
load	97%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	95%

INT+FP

all	99%
load	97%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	96%

Vector efficiency ratios

INT

all	34%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	49%
load	49%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	48%

INT+FP

all	48%
load	49%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	43%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 67.50 cycles. At this rate:

11% of peak load performance is reached (21.93 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.84 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 456910

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVAPD (%R15,%RDX,2),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x20(%R15,%RDX,2),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM18,%YMM10,%YMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM18,%YMM9,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
KMOVB %K2,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K2,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K2,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VRNDSCALEPD $0xb,%YMM0,%YMM7	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VRNDSCALEPD $0xb,%YMM1,%YMM11	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VCVTTPD2DQ %YMM0,%XMM5	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	vect (50.0%)
VCVTTPD2DQ %YMM1,%XMM2	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	vect (50.0%)
VINSERTI32X4 $0x1,%XMM2,%YMM5,%YMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPADDD 0x160326(%RIP),%YMM6,%YMM12	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPADDD 0x16033e(%RIP),%YMM6,%YMM15	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPERM2I128 $0x11,%YMM6,%YMM6,%YMM13	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPADDD 0x160350(%RIP),%YMM6,%YMM6	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VSUBPD %YMM7,%YMM0,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPERM2I128 $0x11,%YMM12,%YMM12,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSUBPD %YMM11,%YMM1,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VGATHERDPD (%RAX,%XMM5,8),%YMM22{%K1}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VGATHERDPD (%RAX,%XMM7,8),%YMM5{%K5}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
KMOVB %K2,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VPERM2I128 $0x11,%YMM6,%YMM6,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VGATHERDPD (%RAX,%XMM6,8),%YMM20{%K1}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VMOVAPD 0x4c0(%RSP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VGATHERDPD (%RAX,%XMM13,8),%YMM21{%K3}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
KMOVB %K2,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VPERM2I128 $0x11,%YMM15,%YMM15,%YMM13	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VGATHERDPD (%RAX,%XMM12,8),%YMM23{%K4}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
KMOVB %K2,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERDPD (%RAX,%XMM15,8),%YMM12{%K6}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VMOVAPD 0x4a0(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x480(%RSP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
KMOVB %K2,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K2,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERDPD (%RAX,%XMM13,8),%YMM11{%K7}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VGATHERDPD (%RAX,%XMM7,8),%YMM13{%K3}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VMOVAPD %YMM6,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD132PD %YMM0,%YMM15,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM15,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x460(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD %YMM8,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD132PD %YMM0,%YMM15,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM15,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x440(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x3e0(%RSP),%YMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD %YMM15,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMULPD %YMM14,%YMM23,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM8,%YMM5,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVDQA (%R12,%RDX,1),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
KMOVB %K2,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K2,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VFMADD132PD %YMM22,%YMM14,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM21,%YMM8,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x420(%RSP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x400(%RSP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD132PD %YMM0,%YMM14,%YMM19	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM14,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM8,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD132PD %YMM0,%YMM24,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM24,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM0,%YMM0,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM1,%YMM1,%YMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
KMOVB %K2,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMULPD %YMM14,%YMM20,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM8,%YMM13,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
KMOVB %K2,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMULPD %YMM3,%YMM0,%YMM17	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM2,%YMM1,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM19,%YMM12,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM11,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x3c0(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVDQA32 %XMM4,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ADD $0x20,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %YMM14,%YMM7,%YMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM8,%YMM6,%YMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K2,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMULPD %YMM15,%YMM7,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM15,%YMM6,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x160288(%RIP),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
KMOVB %K2,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VDIVPD %YMM10,%YMM7,%YMM10	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VSCATTERDPD %YMM14,(%R8,%XMM4,8){%K4}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (50.0%)
VPERM2I128 $0x11,%YMM4,%YMM4,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSCATTERDPD %YMM8,(%R8,%XMM4,8){%K5}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (50.0%)
VMOVAPD 0x380(%RSP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x360(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x3a0(%RSP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x320(%RSP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VDIVPD %YMM9,%YMM7,%YMM9	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMOVAPD %YMM6,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD132PD %YMM0,%YMM15,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM15,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x300(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD231PD %YMM14,%YMM3,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM14,%YMM2,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM8,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD132PD %YMM0,%YMM15,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM15,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x340(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM18,%YMM10,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM3,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM2,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM14,%YMM23,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM8,%YMM5,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM22,%YMM14,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x2c0(%RSP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x2a0(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD %YMM14,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD132PD %YMM0,%YMM15,%YMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM15,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM21,%YMM8,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x280(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x2e0(%RSP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM18,%YMM9,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM8,%YMM3,%YMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM8,%YMM2,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM15,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD213PD 0x4e0(%RSP),%YMM0,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PD 0x4e0(%RSP),%YMM1,%YMM15	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x500(%RSP),%YMM3,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x500(%RSP),%YMM2,%YMM15	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VMULPD %YMM8,%YMM20,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM15,%YMM13,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM12,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM11,%YMM15,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM8,%YMM7,%YMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM14,%YMM6,%YMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM10,%YMM7,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM9,%YMM6,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VSCATTERDPD %YMM10,(%RDI,%XMM19,8){%K6}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (50.0%)
VSCATTERDPD %YMM9,(%RDI,%XMM4,8){%K7}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (50.0%)
VMOVAPD 0x240(%RSP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x220(%RSP),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM14,%YMM3,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x260(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x200(%RSP),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM14,%YMM2,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM7,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD 0x1c0(%RSP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD231PD %YMM15,%YMM17,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM0,%YMM10,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM10,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM14,%YMM3,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM14,%YMM2,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM16,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM8,%YMM9,%YMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD 0x1e0(%RSP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x180(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD231PD %YMM8,%YMM17,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM8,%YMM16,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x1a0(%RSP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD %YMM6,%YMM7,%YMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM8,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD132PD %YMM0,%YMM15,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM15,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x160(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD %YMM10,%YMM6,%YMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM14,%YMM8,%YMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM15,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMULPD %YMM23,%YMM10,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM14,%YMM5,%YMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM29,%YMM0,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM29,%YMM1,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM26,%YMM25,%YMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM9,%YMM22,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM7,%YMM21,%YMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM30,%YMM3,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM30,%YMM2,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM27,%YMM3,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM27,%YMM2,%YMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM26,%YMM25,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM31,%YMM17,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM31,%YMM16,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM28,%YMM17,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM28,%YMM16,%YMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM9,%YMM8,%YMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM7,%YMM15,%YMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM3,%YMM0,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM1,%YMM2,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM20,%YMM0,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM1,%YMM13,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM14,%YMM9,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM10,%YMM13,%YMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM12,%YMM6,%YMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM11,%YMM5,%YMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSCATTERDPD %YMM12,(%RSI,%XMM19,8){%K1}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (50.0%)
VSCATTERDPD %YMM11,(%RSI,%XMM4,8){%K3}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (50.0%)
CMP %RDX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 456910 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0x860>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code