OV - exec - Loop 293

	Loop Id: 293	Module: exec	Source: BsplineFunctor.h:305-336 [...]	Coverage: 0.03%

0x426250 VMOVAPD	(%RBX,%RDX,2),%YMM11    [8]

0x426255 VMOVAPD	0x20(%RBX,%RDX,2),%YMM10    [8]

0x42625b VMULPD	%YMM18,%YMM11,%YMM0

0x426261 VMULPD	%YMM18,%YMM10,%YMM1

0x426267 KMOVB	%K2,%K1

0x42626b KMOVB	%K2,%K5

0x42626f KMOVB	%K2,%K3

0x426273 VRNDSCALEPD	$0xb,%YMM0,%YMM7

0x42627a VRNDSCALEPD	$0xb,%YMM1,%YMM13

0x426281 VCVTTPD2DQ	%YMM0,%XMM5

0x426285 VCVTTPD2DQ	%YMM1,%XMM2

0x426289 VINSERTI32X4	$0x1,%XMM2,%YMM5,%YMM6

0x426290 VPADDD	0x1909e8(%RIP),%YMM6,%YMM12    [6]

0x426298 VPADDD	0x190a00(%RIP),%YMM6,%YMM15    [6]

0x4262a0 VPERM2I128	$0x11,%YMM6,%YMM6,%YMM8

0x4262a6 VPADDD	0x190a12(%RIP),%YMM6,%YMM6    [6]

0x4262ae VSUBPD	%YMM7,%YMM0,%YMM0

0x4262b2 VPERM2I128	$0x11,%YMM12,%YMM12,%YMM7

0x4262b8 VSUBPD	%YMM13,%YMM1,%YMM1

0x4262bd VGATHERDPD	(%RAX,%XMM5,8),%YMM22{%K1}    [7]

0x4262c4 VGATHERDPD	(%RAX,%XMM7,8),%YMM5{%K5}    [7]

0x4262cb KMOVB	%K2,%K1

0x4262cf VPERM2I128	$0x11,%YMM6,%YMM6,%YMM7

0x4262d5 VGATHERDPD	(%RAX,%XMM6,8),%YMM20{%K1}    [7]

0x4262dc VMOVAPD	-0xb0(%RBP),%YMM6    [3]

0x4262e4 VGATHERDPD	(%RAX,%XMM8,8),%YMM21{%K3}    [7]

0x4262eb VPERM2I128	$0x11,%YMM15,%YMM15,%YMM13

0x4262f1 KMOVB	%K2,%K6

0x4262f5 VGATHERDPD	(%RAX,%XMM15,8),%YMM8{%K6}    [7]

0x4262fc VMOVAPD	-0xd0(%RBP),%YMM15    [3]

0x426304 VMOVAPD	-0xf0(%RBP),%YMM9    [3]

0x42630c KMOVB	%K2,%K4

0x426310 KMOVB	%K2,%K7

0x426314 VGATHERDPD	(%RAX,%XMM12,8),%YMM23{%K4}    [7]

0x42631b KMOVB	%K2,%K3

0x42631f VGATHERDPD	(%RAX,%XMM13,8),%YMM12{%K7}    [7]

0x426326 VGATHERDPD	(%RAX,%XMM7,8),%YMM13{%K3}    [7]

0x42632d VMOVAPD	%YMM6,%YMM7

0x426331 VFMADD132PD	%YMM0,%YMM15,%YMM7

0x426336 VFMADD132PD	%YMM1,%YMM15,%YMM6

0x42633b VMOVAPD	-0x110(%RBP),%YMM15    [3]

0x426343 VMOVAPD	%YMM9,%YMM14

0x426348 VFMADD132PD	%YMM0,%YMM15,%YMM14

0x42634d VFMADD132PD	%YMM1,%YMM15,%YMM9

0x426352 VMOVAPD	-0x130(%RBP),%YMM15    [3]

0x42635a VMOVAPD	-0x190(%RBP),%YMM24    [3]

0x426364 VMOVAPD	%YMM15,%YMM19

0x42636a VMULPD	%YMM14,%YMM23,%YMM14

0x426370 VMULPD	%YMM9,%YMM5,%YMM9

0x426375 VMOVDQA	(%R12,%RDX,1),%YMM4    [4]

0x42637b KMOVB	%K2,%K4

0x42637f KMOVB	%K2,%K5

0x426383 VFMADD132PD	%YMM22,%YMM14,%YMM7

0x426389 VFMADD132PD	%YMM21,%YMM9,%YMM6

0x42638f VMOVAPD	-0x150(%RBP),%YMM14    [3]

0x426397 VMOVAPD	-0x170(%RBP),%YMM9    [3]

0x42639f VFMADD132PD	%YMM0,%YMM14,%YMM19

0x4263a5 VFMADD132PD	%YMM1,%YMM14,%YMM15

0x4263aa VMOVAPD	%YMM9,%YMM14

0x4263af VFMADD132PD	%YMM0,%YMM24,%YMM14

0x4263b5 VFMADD132PD	%YMM1,%YMM24,%YMM9

0x4263bb VMULPD	%YMM0,%YMM0,%YMM2

0x4263bf VMULPD	%YMM1,%YMM1,%YMM3

0x4263c3 KMOVB	%K2,%K6

0x4263c7 VMULPD	%YMM14,%YMM20,%YMM14

0x4263cd VMULPD	%YMM9,%YMM13,%YMM9

0x4263d2 KMOVB	%K2,%K7

0x4263d6 VMULPD	%YMM2,%YMM0,%YMM17

0x4263dc VMULPD	%YMM3,%YMM1,%YMM16

0x4263e2 VFMADD231PD	%YMM19,%YMM8,%YMM14

0x4263e8 VFMADD231PD	%YMM15,%YMM12,%YMM9

0x4263ed VMOVAPD	-0x1b0(%RBP),%YMM15    [3]

0x4263f5 VMOVDQA32	%XMM4,%XMM19

0x4263fb ADD	$0x20,%RDX

0x4263ff VADDPD	%YMM14,%YMM7,%YMM7

0x426404 VADDPD	%YMM9,%YMM6,%YMM6

0x426409 KMOVB	%K2,%K1

0x42640d VMULPD	%YMM15,%YMM7,%YMM14

0x426412 VMULPD	%YMM15,%YMM6,%YMM9

0x426417 VBROADCASTSD	0x190950(%RIP),%YMM7    [6]

0x426420 KMOVB	%K2,%K3

0x426424 VDIVPD	%YMM11,%YMM7,%YMM11

0x426429 VSCATTERDPD	%YMM14,(%R8,%XMM4,8){%K4}    [1]

0x426430 VPERM2I128	$0x11,%YMM4,%YMM4,%YMM4

0x426436 VSCATTERDPD	%YMM9,(%R8,%XMM4,8){%K5}    [1]

0x42643d VMOVAPD	-0x1f0(%RBP),%YMM6    [3]

0x426445 VMOVAPD	-0x210(%RBP),%YMM15    [3]

0x42644d VMOVAPD	-0x1d0(%RBP),%YMM14    [3]

0x426455 VMOVAPD	-0x250(%RBP),%YMM9    [3]

0x42645d VDIVPD	%YMM10,%YMM7,%YMM10

0x426462 VMOVAPD	%YMM6,%YMM7

0x426466 VFMADD132PD	%YMM0,%YMM15,%YMM7

0x42646b VFMADD132PD	%YMM1,%YMM15,%YMM6

0x426470 VMOVAPD	-0x270(%RBP),%YMM15    [3]

0x426478 VFMADD231PD	%YMM14,%YMM2,%YMM7

0x42647d VFMADD231PD	%YMM14,%YMM3,%YMM6

0x426482 VMOVAPD	%YMM9,%YMM14

0x426487 VFMADD132PD	%YMM0,%YMM15,%YMM14

0x42648c VFMADD132PD	%YMM1,%YMM15,%YMM9

0x426491 VMOVAPD	-0x230(%RBP),%YMM15    [3]

0x426499 VMULPD	%YMM18,%YMM11,%YMM11

0x42649f VFMADD231PD	%YMM15,%YMM2,%YMM14

0x4264a4 VFMADD231PD	%YMM15,%YMM3,%YMM9

0x4264a9 VMULPD	%YMM14,%YMM23,%YMM14

0x4264af VMULPD	%YMM9,%YMM5,%YMM9

0x4264b4 VFMADD132PD	%YMM22,%YMM14,%YMM7

0x4264ba VMOVAPD	-0x2b0(%RBP),%YMM14    [3]

0x4264c2 VMOVAPD	-0x2d0(%RBP),%YMM15    [3]

0x4264ca VMOVAPD	%YMM14,%YMM24

0x4264d0 VFMADD132PD	%YMM0,%YMM15,%YMM24

0x4264d6 VFMADD132PD	%YMM1,%YMM15,%YMM14

0x4264db VFMADD132PD	%YMM21,%YMM9,%YMM6

0x4264e1 VMOVAPD	-0x2f0(%RBP),%YMM15    [3]

0x4264e9 VMOVAPD	-0x290(%RBP),%YMM9    [3]

0x4264f1 VMULPD	%YMM18,%YMM10,%YMM10

0x4264f7 VFMADD231PD	%YMM9,%YMM2,%YMM24

0x4264fd VFMADD231PD	%YMM9,%YMM3,%YMM14

0x426502 VMOVAPD	%YMM15,%YMM9

0x426507 VFMADD213PD	-0x90(%RBP),%YMM0,%YMM9    [3]

0x426510 VFMADD213PD	-0x90(%RBP),%YMM1,%YMM15    [3]

0x426519 VFMADD231PD	-0x70(%RBP),%YMM2,%YMM9    [3]

0x42651f VFMADD231PD	-0x70(%RBP),%YMM3,%YMM15    [3]

0x426525 VMULPD	%YMM9,%YMM20,%YMM9

0x42652b VMULPD	%YMM15,%YMM13,%YMM15

0x426530 VFMADD231PD	%YMM24,%YMM8,%YMM9

0x426536 VFMADD132PD	%YMM12,%YMM15,%YMM14

0x42653b VADDPD	%YMM9,%YMM7,%YMM7

0x426540 VADDPD	%YMM14,%YMM6,%YMM6

0x426545 VMULPD	%YMM11,%YMM7,%YMM11

0x42654a VMULPD	%YMM10,%YMM6,%YMM10

0x42654f VSCATTERDPD	%YMM11,(%RDI,%XMM19,8){%K6}    [5]

0x426556 VSCATTERDPD	%YMM10,(%RDI,%XMM4,8){%K7}    [5]

0x42655d VMOVAPD	-0x330(%RBP),%YMM14    [3]

0x426565 VMOVAPD	-0x310(%RBP),%YMM9    [3]

0x42656d VMULPD	%YMM14,%YMM2,%YMM15

0x426572 VMULPD	%YMM14,%YMM3,%YMM6

0x426577 VMOVAPD	-0x350(%RBP),%YMM14    [3]

0x42657f VMOVAPD	-0x370(%RBP),%YMM11    [3]

0x426587 VMOVAPD	%YMM14,%YMM7

0x42658b VFMADD231PD	%YMM9,%YMM17,%YMM15

0x426591 VFMADD132PD	%YMM0,%YMM11,%YMM7

0x426596 VFMADD132PD	%YMM1,%YMM11,%YMM14

0x42659b VFMADD231PD	%YMM9,%YMM16,%YMM6

0x4265a1 VMOVAPD	-0x390(%RBP),%YMM10    [3]

0x4265a9 VADDPD	%YMM7,%YMM15,%YMM7

0x4265ad VMOVAPD	-0x3b0(%RBP),%YMM15    [3]

0x4265b5 VADDPD	%YMM6,%YMM14,%YMM9

0x4265b9 VMULPD	%YMM15,%YMM2,%YMM11

0x4265be VMULPD	%YMM15,%YMM3,%YMM14

0x4265c3 VMOVAPD	-0x3f0(%RBP),%YMM15    [3]

0x4265cb VFMADD231PD	%YMM10,%YMM17,%YMM11

0x4265d1 VFMADD231PD	%YMM10,%YMM16,%YMM14

0x4265d7 VMOVAPD	-0x3d0(%RBP),%YMM10    [3]

0x4265df VMOVAPD	%YMM10,%YMM6

0x4265e3 VFMADD132PD	%YMM0,%YMM15,%YMM6

0x4265e8 VFMADD132PD	%YMM1,%YMM15,%YMM10

0x4265ed VMOVAPD	-0x410(%RBP),%YMM15    [3]

0x4265f5 VADDPD	%YMM11,%YMM6,%YMM11

0x4265fa VADDPD	%YMM14,%YMM10,%YMM14

0x4265ff VMULPD	%YMM30,%YMM2,%YMM10

0x426605 VMULPD	%YMM23,%YMM11,%YMM6

0x42660b VMULPD	%YMM14,%YMM5,%YMM5

0x426610 VMULPD	%YMM27,%YMM2,%YMM2

0x426616 VFMADD231PD	%YMM31,%YMM17,%YMM10

0x42661c VFMADD231PD	%YMM7,%YMM22,%YMM6

0x426622 VMULPD	%YMM30,%YMM3,%YMM7

0x426628 VMULPD	%YMM27,%YMM3,%YMM3

0x42662e VFMADD231PD	%YMM9,%YMM21,%YMM5

0x426634 VMOVAPD	%YMM15,%YMM9

0x426639 VFMADD231PD	%YMM29,%YMM0,%YMM9

0x42663f VFMADD231PD	%YMM29,%YMM1,%YMM15

0x426645 VFMADD231PD	%YMM28,%YMM17,%YMM2

0x42664b VFMADD231PD	%YMM28,%YMM16,%YMM3

0x426651 VFMADD132PD	%YMM26,%YMM25,%YMM0

0x426657 VFMADD132PD	%YMM26,%YMM25,%YMM1

0x42665d VFMADD231PD	%YMM31,%YMM16,%YMM7

0x426663 VADDPD	%YMM10,%YMM9,%YMM14

0x426668 VADDPD	%YMM0,%YMM2,%YMM0

0x42666c VADDPD	%YMM1,%YMM3,%YMM1

0x426670 VADDPD	%YMM7,%YMM15,%YMM11

0x426674 VMULPD	%YMM20,%YMM0,%YMM10

0x42667a VMULPD	%YMM1,%YMM13,%YMM13

0x42667e VFMADD132PD	%YMM14,%YMM10,%YMM8

0x426683 VFMADD132PD	%YMM11,%YMM13,%YMM12

0x426688 VADDPD	%YMM6,%YMM8,%YMM8

0x42668c VADDPD	%YMM12,%YMM5,%YMM12

0x426691 VSCATTERDPD	%YMM8,(%RSI,%XMM19,8){%K1}    [2]

0x426698 VSCATTERDPD	%YMM12,(%RSI,%XMM4,8){%K3}    [2]

0x42669f CMP	%RDX,%R9

0x4266a2 JNE	426250

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h: 1147 - 1147

--------------------------------------------------------------------------------

1147:       operator[](size_type __n) const _GLIBCXX_NOEXCEPT

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 305 - 336

--------------------------------------------------------------------------------

305:     real_type r    = distArrayCompressed[j];

306:     int iScatter   = distIndices[j];

307:     real_type rinv = cOne / r;

308:     r *= DeltaRInv;

309:     int iGather   = (int)r;

310:     real_type t   = r - real_type(iGather);

311:     real_type tp0 = t * t * t;

312:     real_type tp1 = t * t;

313:     real_type tp2 = t;

314:

315:     real_type sCoef0 = SplineCoefs[iGather + 0];

316:     real_type sCoef1 = SplineCoefs[iGather + 1];

317:     real_type sCoef2 = SplineCoefs[iGather + 2];

318:     real_type sCoef3 = SplineCoefs[iGather + 3];

319:

320:     // clang-format off

321:     laplArray[iScatter] = dSquareDeltaRinv *

322:       (sCoef0*( d2A[ 2]*tp2 + d2A[ 3])+

323:        sCoef1*( d2A[ 6]*tp2 + d2A[ 7])+

324:        sCoef2*( d2A[10]*tp2 + d2A[11])+

325:        sCoef3*( d2A[14]*tp2 + d2A[15]));

326:

327:     gradArray[iScatter] = DeltaRInv * rinv *

328:       (sCoef0*( dA[ 1]*tp1 + dA[ 2]*tp2 + dA[ 3])+

329:        sCoef1*( dA[ 5]*tp1 + dA[ 6]*tp2 + dA[ 7])+

330:        sCoef2*( dA[ 9]*tp1 + dA[10]*tp2 + dA[11])+

331:        sCoef3*( dA[13]*tp1 + dA[14]*tp2 + dA[15]));

332:

333:     valArray[iScatter] = (sCoef0*(A[ 0]*tp0 + A[ 1]*tp1 + A[ 2]*tp2 + A[ 3])+

334:         sCoef1*(A[ 4]*tp0 + A[ 5]*tp1 + A[ 6]*tp2 + A[ 7])+

335:         sCoef2*(A[ 8]*tp0 + A[ 9]*tp1 + A[10]*tp2 + A[11])+

336:         sCoef3*(A[12]*tp0 + A[13]*tp1 + A[14]*tp2 + A[15]));

Coverage (%)	Name	Source Location	Module
►97.42+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main._omp_fn.1	refwrap.h:350	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►2.58+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main._omp_fn.1	refwrap.h:350	exec
○	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.12
CQA speedup if FP arith vectorized	1.59
CQA speedup if fully vectorized	2.20
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.39
Bottlenecks	P0, P1,
Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source	stl_vector.h:1147-1147,BsplineFunctor.h:305-336
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	67.50
CQA cycles if no scalar integer	60.50
CQA cycles if FP arith vectorized	42.50
CQA cycles if fully vectorized	30.75
Front-end cycles	48.50
P0 cycles	67.50
P1 cycles	67.50
P2 cycles	23.67
P3 cycles	23.67
P4 cycles	12.00
P5 cycles	34.00
P6 cycles	3.60
P7 cycles	12.00
P8 cycles	12.00
P9 cycles	12.00
P10 cycles	3.40
P11 cycles	23.67
DIV/SQRT cycles	16.00
Inter-iter dependencies cycles	28
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	190.00
Nb uops	291.00
Nb loads	47.00
Nb stores	6.00
Nb stack references	30.00
FLOP/cycle	9.13
Nb FLOP add-sub	64.00
Nb FLOP mul	128.00
Nb FLOP fma	208.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.77
Bytes prefetched	0.00
Bytes loaded	1480.00
Bytes stored	192.00
Stride 0	2.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	4.00
Vectorization ratio all	99.42
Vectorization ratio load	97.87
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	96.77
Vector-efficiency ratio all	48.77
Vector-efficiency ratio load	49.20
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	43.15

Metric	Value
CQA speedup if no scalar integer	1.12
CQA speedup if FP arith vectorized	1.59
CQA speedup if fully vectorized	2.20
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.39
Bottlenecks	P0, P1,
Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source	stl_vector.h:1147-1147,BsplineFunctor.h:305-336
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	67.50
CQA cycles if no scalar integer	60.50
CQA cycles if FP arith vectorized	42.50
CQA cycles if fully vectorized	30.75
Front-end cycles	48.50
P0 cycles	67.50
P1 cycles	67.50
P2 cycles	23.67
P3 cycles	23.67
P4 cycles	12.00
P5 cycles	34.00
P6 cycles	3.60
P7 cycles	12.00
P8 cycles	12.00
P9 cycles	12.00
P10 cycles	3.40
P11 cycles	23.67
DIV/SQRT cycles	16.00
Inter-iter dependencies cycles	28
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	190.00
Nb uops	291.00
Nb loads	47.00
Nb stores	6.00
Nb stack references	30.00
FLOP/cycle	9.13
Nb FLOP add-sub	64.00
Nb FLOP mul	128.00
Nb FLOP fma	208.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.77
Bytes prefetched	0.00
Bytes loaded	1480.00
Bytes stored	192.00
Stride 0	2.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	4.00
Vectorization ratio all	99.42
Vectorization ratio load	97.87
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	96.77
Vector-efficiency ratio all	48.77
Vector-efficiency ratio load	49.20
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	43.15

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source file and lines	BsplineFunctor.h:305-336
Module	exec

The loop is defined in:

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:1147
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:305-336

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 67.50 to 60.50 cycles (1.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is highly vectorized. Only 48% of vector register length is used (average across all SSE/AVX instructions).

Details

99% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

97% of SSE/AVX loads are used in vector version.
96% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 67.50 to 48.50 cycles (1.39x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 208 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTPD2DQ: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309
VGATHERDPD: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:315
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:316
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:318
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:315
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:317
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:316
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:317
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:318
VRNDSCALEPD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:310
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:310
VSCATTERDPD: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:327
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:327
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPD: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:315
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:316
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:318
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:315
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:317
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:316
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:317
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:318
VSCATTERDPD: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:327
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:327
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

104 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 616 FP arithmetical operations:

272: addition or subtraction (208 inside FMA instructions)
336: multiply (208 inside FMA instructions)
8: divide

The binary loop is loading 1480 bytes (185 double precision FP elements). The binary loop is storing 192 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.37 FP operations per loaded or stored byte.

General properties

nb instructions	190
nb uops	291
loop length	1112
used x86 registers	9
used mmx registers	0
used xmm registers	10
used ymm registers	32
used zmm registers	0
nb stack references	30
ADD-SUB / MUL ratio	0.50

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	48.50 cycles
front end	48.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	67.50	67.50	23.67	23.67	12.00	34.00	3.60	12.00	12.00	12.00	3.40	23.67
cycles	67.50	67.50	23.67	23.67	12.00	34.00	3.60	12.00	12.00	12.00	3.40	23.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	16.00
Longest recurrence chain latency (RecMII)	28.00

Cycles summary

Front-end	48.50
Dispatch	67.50
DIV/SQRT	16.00
Data deps.	28.00
Overall L1	67.50

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	99%
load	97%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	95%

INT+FP

all	99%
load	97%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	96%

Vector efficiency ratios

INT

all	34%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	49%
load	49%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	48%

INT+FP

all	48%
load	49%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	43%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 67.50 cycles. At this rate:

11% of peak load performance is reached (21.93 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.84 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 426250

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVAPD (%RBX,%RDX,2),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x20(%RBX,%RDX,2),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM18,%YMM11,%YMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM18,%YMM10,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
KMOVB %K2,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K2,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K2,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VRNDSCALEPD $0xb,%YMM0,%YMM7	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VRNDSCALEPD $0xb,%YMM1,%YMM13	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VCVTTPD2DQ %YMM0,%XMM5	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	vect (50.0%)
VCVTTPD2DQ %YMM1,%XMM2	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	vect (50.0%)
VINSERTI32X4 $0x1,%XMM2,%YMM5,%YMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPADDD 0x1909e8(%RIP),%YMM6,%YMM12	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPADDD 0x190a00(%RIP),%YMM6,%YMM15	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPERM2I128 $0x11,%YMM6,%YMM6,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPADDD 0x190a12(%RIP),%YMM6,%YMM6	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VSUBPD %YMM7,%YMM0,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPERM2I128 $0x11,%YMM12,%YMM12,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSUBPD %YMM13,%YMM1,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VGATHERDPD (%RAX,%XMM5,8),%YMM22{%K1}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VGATHERDPD (%RAX,%XMM7,8),%YMM5{%K5}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
KMOVB %K2,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VPERM2I128 $0x11,%YMM6,%YMM6,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VGATHERDPD (%RAX,%XMM6,8),%YMM20{%K1}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VMOVAPD -0xb0(%RBP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VGATHERDPD (%RAX,%XMM8,8),%YMM21{%K3}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VPERM2I128 $0x11,%YMM15,%YMM15,%YMM13	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
KMOVB %K2,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERDPD (%RAX,%XMM15,8),%YMM8{%K6}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VMOVAPD -0xd0(%RBP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD -0xf0(%RBP),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
KMOVB %K2,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K2,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERDPD (%RAX,%XMM12,8),%YMM23{%K4}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
KMOVB %K2,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERDPD (%RAX,%XMM13,8),%YMM12{%K7}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VGATHERDPD (%RAX,%XMM7,8),%YMM13{%K3}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VMOVAPD %YMM6,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD132PD %YMM0,%YMM15,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM15,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD -0x110(%RBP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD %YMM9,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD132PD %YMM0,%YMM15,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM15,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD -0x130(%RBP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD -0x190(%RBP),%YMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD %YMM15,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMULPD %YMM14,%YMM23,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM9,%YMM5,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVDQA (%R12,%RDX,1),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
KMOVB %K2,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K2,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VFMADD132PD %YMM22,%YMM14,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM21,%YMM9,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD -0x150(%RBP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD -0x170(%RBP),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD132PD %YMM0,%YMM14,%YMM19	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM14,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM9,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD132PD %YMM0,%YMM24,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM24,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM0,%YMM0,%YMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM1,%YMM1,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
KMOVB %K2,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMULPD %YMM14,%YMM20,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM9,%YMM13,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
KMOVB %K2,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMULPD %YMM2,%YMM0,%YMM17	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM3,%YMM1,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM19,%YMM8,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM12,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD -0x1b0(%RBP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVDQA32 %XMM4,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ADD $0x20,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %YMM14,%YMM7,%YMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
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VSCATTERDPD %YMM12,(%RSI,%XMM4,8){%K3}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (50.0%)
CMP %RDX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 426250 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x8e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source file and lines	BsplineFunctor.h:305-336
Module	exec

The loop is defined in:

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:1147
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:305-336

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is highly vectorized. Only 48% of vector register length is used (average across all SSE/AVX instructions).

Details

99% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

97% of SSE/AVX loads are used in vector version.
96% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 208 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTPD2DQ: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309
VGATHERDPD: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:315
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:316
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:318
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:315
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:317
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:316
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:317
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:318
VRNDSCALEPD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:310
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:310
VSCATTERDPD: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:327
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:327
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPD: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:315
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:316
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:318
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:315
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:317
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:316
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:317
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:318
VSCATTERDPD: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:327
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:327
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

104 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 616 FP arithmetical operations:

272: addition or subtraction (208 inside FMA instructions)
336: multiply (208 inside FMA instructions)
8: divide

The binary loop is loading 1480 bytes (185 double precision FP elements). The binary loop is storing 192 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.37 FP operations per loaded or stored byte.

General properties

nb instructions	190
nb uops	291
loop length	1112
used x86 registers	9
used mmx registers	0
used xmm registers	10
used ymm registers	32
used zmm registers	0
nb stack references	30
ADD-SUB / MUL ratio	0.50

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	48.50 cycles
front end	48.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	67.50	67.50	23.67	23.67	12.00	34.00	3.60	12.00	12.00	12.00	3.40	23.67
cycles	67.50	67.50	23.67	23.67	12.00	34.00	3.60	12.00	12.00	12.00	3.40	23.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	16.00
Longest recurrence chain latency (RecMII)	28.00

Cycles summary

Front-end	48.50
Dispatch	67.50
DIV/SQRT	16.00
Data deps.	28.00
Overall L1	67.50

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	99%
load	97%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	95%

INT+FP

all	99%
load	97%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	96%

Vector efficiency ratios

INT

all	34%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	49%
load	49%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	48%

INT+FP

all	48%
load	49%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	43%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 67.50 cycles. At this rate:

11% of peak load performance is reached (21.93 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.84 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 426250

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVAPD (%RBX,%RDX,2),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD 0x20(%RBX,%RDX,2),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM18,%YMM11,%YMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM18,%YMM10,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
KMOVB %K2,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K2,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K2,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VRNDSCALEPD $0xb,%YMM0,%YMM7	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VRNDSCALEPD $0xb,%YMM1,%YMM13	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VCVTTPD2DQ %YMM0,%XMM5	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	vect (50.0%)
VCVTTPD2DQ %YMM1,%XMM2	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	vect (50.0%)
VINSERTI32X4 $0x1,%XMM2,%YMM5,%YMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPADDD 0x1909e8(%RIP),%YMM6,%YMM12	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPADDD 0x190a00(%RIP),%YMM6,%YMM15	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPERM2I128 $0x11,%YMM6,%YMM6,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPADDD 0x190a12(%RIP),%YMM6,%YMM6	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VSUBPD %YMM7,%YMM0,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPERM2I128 $0x11,%YMM12,%YMM12,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSUBPD %YMM13,%YMM1,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VGATHERDPD (%RAX,%XMM5,8),%YMM22{%K1}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VGATHERDPD (%RAX,%XMM7,8),%YMM5{%K5}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
KMOVB %K2,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VPERM2I128 $0x11,%YMM6,%YMM6,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VGATHERDPD (%RAX,%XMM6,8),%YMM20{%K1}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VMOVAPD -0xb0(%RBP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VGATHERDPD (%RAX,%XMM8,8),%YMM21{%K3}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VPERM2I128 $0x11,%YMM15,%YMM15,%YMM13	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
KMOVB %K2,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERDPD (%RAX,%XMM15,8),%YMM8{%K6}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VMOVAPD -0xd0(%RBP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD -0xf0(%RBP),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
KMOVB %K2,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K2,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERDPD (%RAX,%XMM12,8),%YMM23{%K4}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
KMOVB %K2,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERDPD (%RAX,%XMM13,8),%YMM12{%K7}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VGATHERDPD (%RAX,%XMM7,8),%YMM13{%K3}	5	1	1	1.33	1.33	0	1	0	0	0	0	0	1.33	28	2	vect (50.0%)
VMOVAPD %YMM6,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD132PD %YMM0,%YMM15,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM15,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD -0x110(%RBP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD %YMM9,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD132PD %YMM0,%YMM15,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM15,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD -0x130(%RBP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD -0x190(%RBP),%YMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD %YMM15,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMULPD %YMM14,%YMM23,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM9,%YMM5,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVDQA (%R12,%RDX,1),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
KMOVB %K2,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K2,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VFMADD132PD %YMM22,%YMM14,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM21,%YMM9,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD -0x150(%RBP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD -0x170(%RBP),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD132PD %YMM0,%YMM14,%YMM19	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM14,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM9,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD132PD %YMM0,%YMM24,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM24,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM0,%YMM0,%YMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM1,%YMM1,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
KMOVB %K2,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMULPD %YMM14,%YMM20,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM9,%YMM13,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
KMOVB %K2,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMULPD %YMM2,%YMM0,%YMM17	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM3,%YMM1,%YMM16	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM19,%YMM8,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM12,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD -0x1b0(%RBP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVDQA32 %XMM4,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ADD $0x20,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %YMM14,%YMM7,%YMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM9,%YMM6,%YMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K2,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMULPD %YMM15,%YMM7,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM15,%YMM6,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x190950(%RIP),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
KMOVB %K2,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VDIVPD %YMM11,%YMM7,%YMM11	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VSCATTERDPD %YMM14,(%R8,%XMM4,8){%K4}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (50.0%)
VPERM2I128 $0x11,%YMM4,%YMM4,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSCATTERDPD %YMM9,(%R8,%XMM4,8){%K5}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (50.0%)
VMOVAPD -0x1f0(%RBP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD -0x210(%RBP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD -0x1d0(%RBP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD -0x250(%RBP),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VDIVPD %YMM10,%YMM7,%YMM10	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VMOVAPD %YMM6,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD132PD %YMM0,%YMM15,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM15,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD -0x270(%RBP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD231PD %YMM14,%YMM2,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM14,%YMM3,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM9,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD132PD %YMM0,%YMM15,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM15,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD -0x230(%RBP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM18,%YMM11,%YMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM2,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM3,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM14,%YMM23,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM9,%YMM5,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM22,%YMM14,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD -0x2b0(%RBP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD -0x2d0(%RBP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD %YMM14,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD132PD %YMM0,%YMM15,%YMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM15,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM21,%YMM9,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD -0x2f0(%RBP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD -0x290(%RBP),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM18,%YMM10,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM9,%YMM2,%YMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM9,%YMM3,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM15,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD213PD -0x90(%RBP),%YMM0,%YMM9	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PD -0x90(%RBP),%YMM1,%YMM15	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD -0x70(%RBP),%YMM2,%YMM9	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD -0x70(%RBP),%YMM3,%YMM15	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VMULPD %YMM9,%YMM20,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM15,%YMM13,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM8,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM12,%YMM15,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM9,%YMM7,%YMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM14,%YMM6,%YMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM11,%YMM7,%YMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM10,%YMM6,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VSCATTERDPD %YMM11,(%RDI,%XMM19,8){%K6}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (50.0%)
VSCATTERDPD %YMM10,(%RDI,%XMM4,8){%K7}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (50.0%)
VMOVAPD -0x330(%RBP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD -0x310(%RBP),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM14,%YMM2,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM14,%YMM3,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD -0x350(%RBP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD -0x370(%RBP),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD %YMM14,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD231PD %YMM9,%YMM17,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM0,%YMM11,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM11,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM9,%YMM16,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD -0x390(%RBP),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD %YMM7,%YMM15,%YMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD -0x3b0(%RBP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD %YMM6,%YMM14,%YMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM15,%YMM2,%YMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM15,%YMM3,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD -0x3f0(%RBP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD231PD %YMM10,%YMM17,%YMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM10,%YMM16,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD -0x3d0(%RBP),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD %YMM10,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD132PD %YMM0,%YMM15,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM15,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD -0x410(%RBP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD %YMM11,%YMM6,%YMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM14,%YMM10,%YMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM30,%YMM2,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM23,%YMM11,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM14,%YMM5,%YMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM27,%YMM2,%YMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM31,%YMM17,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM7,%YMM22,%YMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM30,%YMM3,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM27,%YMM3,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM9,%YMM21,%YMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM15,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD231PD %YMM29,%YMM0,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM29,%YMM1,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM28,%YMM17,%YMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM28,%YMM16,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM26,%YMM25,%YMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM26,%YMM25,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM31,%YMM16,%YMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM10,%YMM9,%YMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM0,%YMM2,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM1,%YMM3,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM7,%YMM15,%YMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM20,%YMM0,%YMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM1,%YMM13,%YMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM14,%YMM10,%YMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM11,%YMM13,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM6,%YMM8,%YMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM12,%YMM5,%YMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSCATTERDPD %YMM8,(%RSI,%XMM19,8){%K1}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (50.0%)
VSCATTERDPD %YMM12,(%RSI,%XMM4,8){%K3}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (50.0%)
CMP %RDX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 426250 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x8e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code