OV - exec - Loop 289

0x426f9c VADDPD	(%RAX),%YMM0,%YMM1    [2]

0x426fa0 ADD	$0x100,%RAX

0x426fa6 VADDPD	-0xe0(%RAX),%YMM1,%YMM3    [1]

0x426fae VADDPD	-0xc0(%RAX),%YMM3,%YMM4    [1]

0x426fb6 VADDPD	-0xa0(%RAX),%YMM4,%YMM5    [1]

0x426fbe VADDPD	-0x80(%RAX),%YMM5,%YMM6    [1]

0x426fc3 VADDPD	-0x60(%RAX),%YMM6,%YMM7    [1]

0x426fc8 VADDPD	-0x40(%RAX),%YMM7,%YMM9    [1]

0x426fcd VADDPD	-0x20(%RAX),%YMM9,%YMM0    [1]

0x426fd2 CMP	%RAX,%R9

0x426fd5 JNE	426f9c

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_numeric.h: 140 - 141

--------------------------------------------------------------------------------

140:       for (; __first != __last; ++__first)

141: 	__init = _GLIBCXX_MOVE_IF_20(__init) + *__first;

Coverage (%)	Name	Source Location	Module
►97.14+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main._omp_fn.1	refwrap.h:350	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►2.86+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main._omp_fn.1	refwrap.h:350	exec
○	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.47
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	6.00
Bottlenecks
Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source	stl_numeric.h:140-141
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.00
CQA cycles if no scalar integer	24.00
CQA cycles if FP arith vectorized	16.36
CQA cycles if fully vectorized	12.00
Front-end cycles	1.67
P0 cycles	0.70
P1 cycles	4.00
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	0.00
P5 cycles	4.00
P6 cycles	0.70
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.60
P11 cycles	2.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	24
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	10.00
Nb loads	8.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.33
Nb FLOP add-sub	32.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.67
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.47
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	6.00
Bottlenecks
Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source	stl_numeric.h:140-141
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.00
CQA cycles if no scalar integer	24.00
CQA cycles if FP arith vectorized	16.36
CQA cycles if fully vectorized	12.00
Front-end cycles	1.67
P0 cycles	0.70
P1 cycles	4.00
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	0.00
P5 cycles	4.00
P6 cycles	0.70
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.60
P11 cycles	2.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	24
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	10.00
Nb loads	8.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.33
Nb FLOP add-sub	32.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.67
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source file and lines	stl_numeric.h:140-141
Module	exec

The loop is defined in /cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_numeric.h:140-141.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

8 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

32: addition or subtraction

The binary loop is loading 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	11
nb uops	10
loop length	59
used x86 registers	2
used mmx registers	0
used xmm registers	0
used ymm registers	8
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.67 cycles
front end	1.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	0.70	4.00	2.67	2.67	0.00	4.00	0.70	0.00	0.00	0.00	0.60	2.67
cycles	0.70	4.00	2.67	2.67	0.00	4.00	0.70	0.00	0.00	0.00	0.60	2.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	24.00

Cycles summary

Front-end	1.67
Dispatch	4.00
Data deps.	24.00
Overall L1	24.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles. At this rate:

5% of peak load performance is reached (10.67 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 426f9c

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
VADDPD (%RAX),%YMM0,%YMM1	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
ADD $0x100,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VADDPD -0xe0(%RAX),%YMM1,%YMM3	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD -0xc0(%RAX),%YMM3,%YMM4	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD -0xa0(%RAX),%YMM4,%YMM5	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD -0x80(%RAX),%YMM5,%YMM6	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD -0x60(%RAX),%YMM6,%YMM7	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD -0x40(%RAX),%YMM7,%YMM9	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD -0x20(%RAX),%YMM9,%YMM0	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
CMP %RAX,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 426f9c <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x162c>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source file and lines	stl_numeric.h:140-141
Module	exec

The loop is defined in /cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_numeric.h:140-141.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

8 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

32: addition or subtraction

The binary loop is loading 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	11
nb uops	10
loop length	59
used x86 registers	2
used mmx registers	0
used xmm registers	0
used ymm registers	8
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.67 cycles
front end	1.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	0.70	4.00	2.67	2.67	0.00	4.00	0.70	0.00	0.00	0.00	0.60	2.67
cycles	0.70	4.00	2.67	2.67	0.00	4.00	0.70	0.00	0.00	0.00	0.60	2.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	24.00

Cycles summary

Front-end	1.67
Dispatch	4.00
Data deps.	24.00
Overall L1	24.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles. At this rate:

5% of peak load performance is reached (10.67 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 426f9c

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
VADDPD (%RAX),%YMM0,%YMM1	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
ADD $0x100,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VADDPD -0xe0(%RAX),%YMM1,%YMM3	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD -0xc0(%RAX),%YMM3,%YMM4	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD -0xa0(%RAX),%YMM4,%YMM5	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD -0x80(%RAX),%YMM5,%YMM6	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD -0x60(%RAX),%YMM6,%YMM7	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD -0x40(%RAX),%YMM7,%YMM9	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
VADDPD -0x20(%RAX),%YMM9,%YMM0	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	vect (50.0%)
CMP %RAX,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 426f9c <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x162c>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code