OV - exec - Loop 2652

	Loop Id: 2652	Module: exec	Source: ParticleBConds3DSoa.h:237-255	Coverage: 0.57%

0x56f8e0 VMOVAPD	(%RSI,%R8,1),%YMM0    [2]

0x56f8e6 VMOVAPD	(%RDI,%R8,1),%YMM3    [1]

0x56f8ec VSUBPD	%YMM8,%YMM0,%YMM15

0x56f8f1 VSUBPD	%YMM12,%YMM3,%YMM10

0x56f8f6 VMOVAPD	(%RCX,%R8,1),%YMM9    [7]

0x56f8fc VMULPD	0x168(%RBX){1to4},%YMM15,%YMM1    [6]

0x56f903 VMULPD	0x198(%RBX){1to4},%YMM15,%YMM4    [6]

0x56f90a VMULPD	0x180(%RBX){1to4},%YMM15,%YMM2    [6]

0x56f911 VSUBPD	%YMM7,%YMM9,%YMM0

0x56f915 VMOVAPD	%YMM14,%YMM3

0x56f919 VFMADD231PD	0x160(%RBX){1to4},%YMM10,%YMM1    [6]

0x56f920 VFMADD231PD	0x178(%RBX){1to4},%YMM10,%YMM2    [6]

0x56f927 VFMADD132PD	0x190(%RBX){1to4},%YMM4,%YMM10    [6]

0x56f92e VFMADD231PD	0x170(%RBX){1to4},%YMM0,%YMM1    [6]

0x56f935 VFMADD231PD	0x188(%RBX){1to4},%YMM0,%YMM2    [6]

0x56f93c VFMADD132PD	0x1a0(%RBX){1to4},%YMM10,%YMM0    [6]

0x56f943 VPTERNLOGQ	$-0x8,%YMM5,%YMM1,%YMM3

0x56f94a VADDPD	%YMM3,%YMM1,%YMM10

0x56f94e VRNDSCALEPD	$0x3,%YMM10,%YMM15

0x56f955 VMOVAPD	%YMM14,%YMM10

0x56f95a VPTERNLOGQ	$-0x8,%YMM5,%YMM0,%YMM10

0x56f961 VSUBPD	%YMM15,%YMM1,%YMM9

0x56f966 VMOVAPD	%YMM14,%YMM1

0x56f96a VPTERNLOGQ	$-0x8,%YMM5,%YMM2,%YMM1

0x56f971 VADDPD	%YMM1,%YMM2,%YMM4

0x56f975 VADDPD	%YMM10,%YMM0,%YMM15

0x56f97a VRNDSCALEPD	$0x3,%YMM4,%YMM3

0x56f981 VRNDSCALEPD	$0x3,%YMM15,%YMM1

0x56f988 VSUBPD	%YMM3,%YMM2,%YMM2

0x56f98c VSUBPD	%YMM1,%YMM0,%YMM0

0x56f990 VMULPD	0x120(%RBX){1to4},%YMM2,%YMM4    [6]

0x56f997 VFMADD231PD	0x118(%RBX){1to4},%YMM9,%YMM4    [6]

0x56f99e VFMADD231PD	0x128(%RBX){1to4},%YMM0,%YMM4    [6]

0x56f9a5 VMOVAPD	%YMM4,(%R12,%R8,1)    [3]

0x56f9ab VMULPD	0x138(%RBX){1to4},%YMM2,%YMM3    [6]

0x56f9b2 VFMADD231PD	0x130(%RBX){1to4},%YMM9,%YMM3    [6]

0x56f9b9 VFMADD231PD	0x140(%RBX){1to4},%YMM0,%YMM3    [6]

0x56f9c0 VMOVAPD	%YMM3,(%RAX,%R8,1)    [5]

0x56f9c6 VMULPD	0x150(%RBX){1to4},%YMM2,%YMM2    [6]

0x56f9cd VFMADD132PD	0x148(%RBX){1to4},%YMM2,%YMM9    [6]

0x56f9d4 VFMADD132PD	0x158(%RBX){1to4},%YMM9,%YMM0    [6]

0x56f9db VMOVAPD	%YMM0,(%RDX,%R8,1)    [8]

0x56f9e1 VMOVAPD	(%RAX,%R8,1),%YMM10    [5]

0x56f9e7 VMOVAPD	(%R12,%R8,1),%YMM9    [3]

0x56f9ed VMULPD	%YMM10,%YMM10,%YMM15

0x56f9f2 VFMADD132PD	%YMM9,%YMM15,%YMM9

0x56f9f7 VFMADD132PD	%YMM0,%YMM9,%YMM0

0x56f9fc VSQRTPD	%YMM0,%YMM1

0x56fa00 VMOVAPD	%YMM1,(%R13,%R8,1)    [4]

0x56fa07 ADD	$0x20,%R8

0x56fa0b CMP	%R8,%R11

0x56fa0e JNE	56f8e0

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 237 - 255

--------------------------------------------------------------------------------

237:       T displ_0 = px[iat] - x0;

238:       T displ_1 = py[iat] - y0;

239:       T displ_2 = pz[iat] - z0;

240:

241:       T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

242:       T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

243:       T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

244:

245:       //put them in the box

246:       ar_0 -= round(ar_0);

247:       ar_1 -= round(ar_1);

248:       ar_2 -= round(ar_2);

249:

250:       //unit2cart

251:       dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

252:       dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

253:       dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

254:

255:       temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

Coverage (%)	Name	Source Location	Module
►97.43+	qmcplusplus::ParticleSet::make[...]	stl_vector.h:993	exec
○	main._omp_fn.1	stl_vector.h:1128	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►2.57+	qmcplusplus::ParticleSet::make[...]	stl_vector.h:993	exec
○	main._omp_fn.1	stl_vector.h:1128	exec
○	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.67
CQA speedup if fully vectorized	1.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P1,
Function	qmcplusplus::SoaDistanceTableAAOMPTarget::move(qmcplusplus::ParticleSet const&, qmcplusplus::TinyVector const&, int, bool)
Source	ParticleBConds3DSoa.h:237-255
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.00
CQA cycles if no scalar integer	15.00
CQA cycles if FP arith vectorized	9.00
CQA cycles if fully vectorized	9.00
Front-end cycles	9.00
P0 cycles	14.50
P1 cycles	15.00
P2 cycles	7.67
P3 cycles	7.67
P4 cycles	2.00
P5 cycles	11.00
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	7.67
DIV/SQRT cycles	9.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	52.00
Nb uops	54.00
Nb loads	23.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	12.00
Nb FLOP add-sub	36.00
Nb FLOP mul	28.00
Nb FLOP fma	56.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.80
Bytes prefetched	0.00
Bytes loaded	304.00
Bytes stored	128.00
Stride 0	1.00
Stride 1	7.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.67
CQA speedup if fully vectorized	1.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P1,
Function	qmcplusplus::SoaDistanceTableAAOMPTarget::move(qmcplusplus::ParticleSet const&, qmcplusplus::TinyVector const&, int, bool)
Source	ParticleBConds3DSoa.h:237-255
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.00
CQA cycles if no scalar integer	15.00
CQA cycles if FP arith vectorized	9.00
CQA cycles if fully vectorized	9.00
Front-end cycles	9.00
P0 cycles	14.50
P1 cycles	15.00
P2 cycles	7.67
P3 cycles	7.67
P4 cycles	2.00
P5 cycles	11.00
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	7.67
DIV/SQRT cycles	9.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	52.00
Nb uops	54.00
Nb loads	23.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	12.00
Nb FLOP add-sub	36.00
Nb FLOP mul	28.00
Nb FLOP fma	56.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.80
Bytes prefetched	0.00
Bytes loaded	304.00
Bytes stored	128.00
Stride 0	1.00
Stride 1	7.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::SoaDistanceTableAAOMPTarget::move(qmcplusplus::ParticleSet const&, qmcplusplus::TinyVector const&, int, bool)
Source file and lines	ParticleBConds3DSoa.h:237-255
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:237-255.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 56 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VRNDSCALEPD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:246
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:247
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:248

Type of elements and instruction set

34 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 180 FP arithmetical operations:

92: addition or subtraction (56 inside FMA instructions)
84: multiply (56 inside FMA instructions)
4: square root

The binary loop is loading 304 bytes (38 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.42 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	52
nb uops	54
loop length	308
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	13
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.00 cycles
front end	9.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	14.50	14.50	7.67	7.67	2.00	11.00	1.00	2.00	2.00	2.00	0.00	7.67
cycles	14.50	15.00	7.67	7.67	2.00	11.00	1.00	2.00	2.00	2.00	0.00	7.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	9.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.00
Dispatch	15.00
DIV/SQRT	9.00
Data deps.	1.00
Overall L1	15.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

INT

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	50%
load	50%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	50%

INT+FP

all	50%
load	50%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.00 cycles. At this rate:

10% of peak load performance is reached (20.27 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.53 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 56f8e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVAPD (%RSI,%R8,1),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD (%RDI,%R8,1),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPD %YMM8,%YMM0,%YMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM12,%YMM3,%YMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD (%RCX,%R8,1),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD 0x168(%RBX){1to4},%YMM15,%YMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VMULPD 0x198(%RBX){1to4},%YMM15,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VMULPD 0x180(%RBX){1to4},%YMM15,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VSUBPD %YMM7,%YMM9,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM14,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD231PD 0x160(%RBX){1to4},%YMM10,%YMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x178(%RBX){1to4},%YMM10,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD132PD 0x190(%RBX){1to4},%YMM4,%YMM10	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x170(%RBX){1to4},%YMM0,%YMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x188(%RBX){1to4},%YMM0,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD132PD 0x1a0(%RBX){1to4},%YMM10,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM1,%YMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM3,%YMM1,%YMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0x3,%YMM10,%YMM15	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VMOVAPD %YMM14,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM0,%YMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VSUBPD %YMM15,%YMM1,%YMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM14,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM2,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM1,%YMM2,%YMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM10,%YMM0,%YMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0x3,%YMM4,%YMM3	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VRNDSCALEPD $0x3,%YMM15,%YMM1	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VSUBPD %YMM3,%YMM2,%YMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM1,%YMM0,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD 0x120(%RBX){1to4},%YMM2,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x118(%RBX){1to4},%YMM9,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x128(%RBX){1to4},%YMM0,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VMOVAPD %YMM4,(%R12,%R8,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMULPD 0x138(%RBX){1to4},%YMM2,%YMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x130(%RBX){1to4},%YMM9,%YMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x140(%RBX){1to4},%YMM0,%YMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VMOVAPD %YMM3,(%RAX,%R8,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMULPD 0x150(%RBX){1to4},%YMM2,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD132PD 0x148(%RBX){1to4},%YMM2,%YMM9	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD132PD 0x158(%RBX){1to4},%YMM9,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VMOVAPD %YMM0,(%RDX,%R8,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPD (%RAX,%R8,1),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD (%R12,%R8,1),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM10,%YMM10,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM9,%YMM15,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM0,%YMM9,%YMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VSQRTPD %YMM0,%YMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VMOVAPD %YMM1,(%R13,%R8,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x20,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 56f8e0 <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE4moveERKNS_11ParticleSetERKNS_10TinyVectorIdLj3EEEib+0x6d0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	qmcplusplus::SoaDistanceTableAAOMPTarget::move(qmcplusplus::ParticleSet const&, qmcplusplus::TinyVector const&, int, bool)
Source file and lines	ParticleBConds3DSoa.h:237-255
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:237-255.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 56 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VRNDSCALEPD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:246
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:247
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:248

Type of elements and instruction set

34 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 180 FP arithmetical operations:

92: addition or subtraction (56 inside FMA instructions)
84: multiply (56 inside FMA instructions)
4: square root

The binary loop is loading 304 bytes (38 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.42 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	52
nb uops	54
loop length	308
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	13
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.00 cycles
front end	9.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	14.50	14.50	7.67	7.67	2.00	11.00	1.00	2.00	2.00	2.00	0.00	7.67
cycles	14.50	15.00	7.67	7.67	2.00	11.00	1.00	2.00	2.00	2.00	0.00	7.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	9.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.00
Dispatch	15.00
DIV/SQRT	9.00
Data deps.	1.00
Overall L1	15.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

INT

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	50%
load	50%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	50%

INT+FP

all	50%
load	50%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.00 cycles. At this rate:

10% of peak load performance is reached (20.27 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.53 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 56f8e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVAPD (%RSI,%R8,1),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD (%RDI,%R8,1),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPD %YMM8,%YMM0,%YMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM12,%YMM3,%YMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD (%RCX,%R8,1),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD 0x168(%RBX){1to4},%YMM15,%YMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VMULPD 0x198(%RBX){1to4},%YMM15,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VMULPD 0x180(%RBX){1to4},%YMM15,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VSUBPD %YMM7,%YMM9,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM14,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD231PD 0x160(%RBX){1to4},%YMM10,%YMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x178(%RBX){1to4},%YMM10,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD132PD 0x190(%RBX){1to4},%YMM4,%YMM10	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x170(%RBX){1to4},%YMM0,%YMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x188(%RBX){1to4},%YMM0,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD132PD 0x1a0(%RBX){1to4},%YMM10,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM1,%YMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM3,%YMM1,%YMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0x3,%YMM10,%YMM15	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VMOVAPD %YMM14,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM0,%YMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VSUBPD %YMM15,%YMM1,%YMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM14,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM2,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VADDPD %YMM1,%YMM2,%YMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM10,%YMM0,%YMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0x3,%YMM4,%YMM3	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VRNDSCALEPD $0x3,%YMM15,%YMM1	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (50.0%)
VSUBPD %YMM3,%YMM2,%YMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM1,%YMM0,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD 0x120(%RBX){1to4},%YMM2,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x118(%RBX){1to4},%YMM9,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x128(%RBX){1to4},%YMM0,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VMOVAPD %YMM4,(%R12,%R8,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMULPD 0x138(%RBX){1to4},%YMM2,%YMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x130(%RBX){1to4},%YMM9,%YMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x140(%RBX){1to4},%YMM0,%YMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VMOVAPD %YMM3,(%RAX,%R8,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMULPD 0x150(%RBX){1to4},%YMM2,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD132PD 0x148(%RBX){1to4},%YMM2,%YMM9	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD132PD 0x158(%RBX){1to4},%YMM9,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VMOVAPD %YMM0,(%RDX,%R8,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPD (%RAX,%R8,1),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD (%R12,%R8,1),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMULPD %YMM10,%YMM10,%YMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM9,%YMM15,%YMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM0,%YMM9,%YMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VSQRTPD %YMM0,%YMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	9	vect (50.0%)
VMOVAPD %YMM1,(%R13,%R8,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x20,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 56f8e0 <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE4moveERKNS_11ParticleSetERKNS_10TinyVectorIdLj3EEEib+0x6d0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code