OV - exec - Loop 121

	Loop Id: 121	Module: exec	Source: OperatorTags.h:43-63 [...]	Coverage: 0.09%

0x40eac0 INC	%R14

0x40eac3 CMP	%R8,%R14

0x40eac6 JAE	40ed76

0x40eacc MOV	-0xb0(%RBP),%R11

0x40ead3 LEA	(,%R14,8),%RDI

0x40eadb MOV	0x18(%R11),%RCX

0x40eadf ADD	%RDI,%RCX

0x40eae2 VMOVSD	(%RCX),%XMM0

0x40eae6 VCOMISD	0x1440(%R13),%XMM0

0x40eaef JAE	40eac0

0x40eaf1 MOV	0x2830(%R13),%R10

0x40eaf8 MOV	$-0x5555555555555555,%R8

0x40eb02 SUB	0x2828(%R13),%R10

0x40eb09 SAR	$0x3,%R10

0x40eb0d IMUL	%R8,%R10

0x40eb11 TEST	%R10D,%R10D

0x40eb14 JLE	40ed18

0x40eb1a MOV	-0x90(%RBP),%RAX

0x40eb21 DEC	%R10D

0x40eb24 MOVSXD	0x8(%RAX),%R11

0x40eb28 MOV	0x18(%RAX),%RDX

0x40eb2c LEA	(%R11,%R14,1),%R9

0x40eb30 ADD	%R9,%R11

0x40eb33 LEA	(%RDX,%R9,8),%R8

0x40eb37 MOV	-0x118(%RBP),%RSI

0x40eb3e LEA	(%RDX,%R11,8),%R9

0x40eb42 LEA	(%R10,%R10,2),%R11

0x40eb46 LEA	(%R12,%R11,8),%R10

0x40eb4a LEA	(%R11,%R11,2),%R11

0x40eb4e ADD	%RDX,%RDI

0x40eb51 MOV	-0x70(%RBP),%RAX

0x40eb55 ADD	0x40(%RBX),%RSI

0x40eb59 MOV	%R12,%RDX

0x40eb5c AND	$0x3,%R11D

0x40eb60 JE	40ece0

0x40eb66 VMOVSD	(%RDI),%XMM5

0x40eb6a VMOVSD	(%R9),%XMM3

0x40eb6f VMOVHPD	(%R8),%XMM5,%XMM6

0x40eb74 VADDPD	(%RSI),%XMM6,%XMM4

0x40eb78 VADDSD	0x10(%RSI),%XMM3,%XMM13

0x40eb7d VMOVDDUP	%XMM0,%XMM2

0x40eb81 VFMADD231PD	(%R12),%XMM2,%XMM4

0x40eb87 VFMADD132SD	0x10(%R12),%XMM13,%XMM0

0x40eb8e ADD	$0x18,%RAX

0x40eb92 LEA	0x18(%R12),%RDX

0x40eb97 VMOVUPD	%XMM4,-0x18(%RAX)

0x40eb9c VMOVSD	%XMM0,-0x8(%RAX)

0x40eba1 VMOVSD	(%RCX),%XMM0

0x40eba5 CMP	$0x1,%R11

0x40eba9 JE	40ece0

0x40ebaf CMP	$0x2,%R11

0x40ebb3 JE	40ebf4

0x40ebb5 VMOVSD	(%RDI),%XMM9

0x40ebb9 VMOVSD	(%R9),%XMM15

0x40ebbe VMOVHPD	(%R8),%XMM9,%XMM8

0x40ebc3 VADDPD	(%RSI),%XMM8,%XMM7

0x40ebc7 VADDSD	0x10(%RSI),%XMM15,%XMM1

0x40ebcc VMOVDDUP	%XMM0,%XMM10

0x40ebd0 VFMADD231PD	0x18(%R12),%XMM10,%XMM7

0x40ebd7 VFMADD132SD	0x10(%RDX),%XMM1,%XMM0

0x40ebdd ADD	$0x18,%RAX

0x40ebe1 LEA	0x30(%R12),%RDX

0x40ebe6 VMOVUPD	%XMM7,-0x18(%RAX)

0x40ebeb VMOVSD	%XMM0,-0x8(%RAX)

0x40ebf0 VMOVSD	(%RCX),%XMM0

0x40ebf4 VMOVSD	(%RDI),%XMM14

0x40ebf8 VMOVSD	(%R9),%XMM11

0x40ebfd VMOVHPD	(%R8),%XMM14,%XMM3

0x40ec02 VADDPD	(%RSI),%XMM3,%XMM2

0x40ec06 VADDSD	0x10(%RSI),%XMM11,%XMM5

0x40ec0b VMOVDDUP	%XMM0,%XMM12

0x40ec0f VFMADD231PD	(%RDX),%XMM12,%XMM2

0x40ec14 VFMADD132SD	0x10(%RDX),%XMM5,%XMM0

0x40ec1a ADD	$0x18,%RAX

0x40ec1e ADD	$0x18,%RDX

0x40ec22 VMOVUPD	%XMM2,-0x18(%RAX)

0x40ec27 VMOVSD	%XMM0,-0x8(%RAX)

0x40ec2c VMOVSD	(%RCX),%XMM0

0x40ec30 JMP	40ece0

  (122) 0x40ec35 VMOVSD	(%RDI),%XMM7

  (122) 0x40ec39 VMOVSD	(%R9),%XMM8

  (122) 0x40ec3e VMOVHPD	(%R8),%XMM7,%XMM1

  (122) 0x40ec43 VADDPD	(%RSI),%XMM1,%XMM11

  (122) 0x40ec47 VADDSD	0x10(%RSI),%XMM8,%XMM14

  (122) 0x40ec4c VMOVDDUP	(%RCX),%XMM12

  (122) 0x40ec50 VMOVSD	0x28(%RDX),%XMM3

  (122) 0x40ec55 VFMADD231PD	0x18(%RDX),%XMM12,%XMM11

  (122) 0x40ec5b VFMADD231SD	(%RCX),%XMM3,%XMM14

  (122) 0x40ec60 ADD	$0x60,%RAX

  (122) 0x40ec64 ADD	$0x60,%RDX

  (122) 0x40ec68 VMOVUPD	%XMM11,-0x48(%RAX)

  (122) 0x40ec6d VMOVSD	%XMM14,-0x38(%RAX)

  (122) 0x40ec72 VMOVSD	(%RDI),%XMM5

  (122) 0x40ec76 VMOVSD	(%R9),%XMM2

  (122) 0x40ec7b VMOVHPD	(%R8),%XMM5,%XMM0

  (122) 0x40ec80 VADDPD	(%RSI),%XMM0,%XMM4

  (122) 0x40ec84 VADDSD	0x10(%RSI),%XMM2,%XMM13

  (122) 0x40ec89 VMOVSD	-0x20(%RDX),%XMM15

  (122) 0x40ec8e VMOVDDUP	(%RCX),%XMM6

  (122) 0x40ec92 VFMADD231SD	(%RCX),%XMM15,%XMM13

  (122) 0x40ec97 VFMADD231PD	-0x30(%RDX),%XMM6,%XMM4

  (122) 0x40ec9d VMOVSD	%XMM13,-0x20(%RAX)

  (122) 0x40eca2 VMOVUPD	%XMM4,-0x30(%RAX)

  (122) 0x40eca7 VMOVSD	(%RDI),%XMM9

  (122) 0x40ecab VMOVSD	(%R9),%XMM10

  (122) 0x40ecb0 VMOVHPD	(%R8),%XMM9,%XMM8

  (122) 0x40ecb5 VADDPD	(%RSI),%XMM8,%XMM7

  (122) 0x40ecb9 VADDSD	0x10(%RSI),%XMM10,%XMM11

  (122) 0x40ecbe VMOVSD	-0x8(%RDX),%XMM12

  (122) 0x40ecc3 VMOVDDUP	(%RCX),%XMM1

  (122) 0x40ecc7 VFMADD231SD	(%RCX),%XMM12,%XMM11

  (122) 0x40eccc VFMADD231PD	-0x18(%RDX),%XMM1,%XMM7

  (122) 0x40ecd2 VMOVUPD	%XMM7,-0x18(%RAX)

  (122) 0x40ecd7 VMOVSD	%XMM11,-0x8(%RAX)

  (122) 0x40ecdc VMOVSD	(%RCX),%XMM0

  (122) 0x40ece0 VMOVSD	(%RDI),%XMM13

  (122) 0x40ece4 VMOVSD	(%R9),%XMM6

  (122) 0x40ece9 VMOVHPD	(%R8),%XMM13,%XMM15

  (122) 0x40ecee VADDPD	(%RSI),%XMM15,%XMM10

  (122) 0x40ecf2 VADDSD	0x10(%RSI),%XMM6,%XMM9

  (122) 0x40ecf7 VMOVDDUP	%XMM0,%XMM4

  (122) 0x40ecfb VFMADD231PD	(%RDX),%XMM4,%XMM10

  (122) 0x40ed00 VFMADD132SD	0x10(%RDX),%XMM9,%XMM0

  (122) 0x40ed06 VMOVUPD	%XMM10,(%RAX)

  (122) 0x40ed0a VMOVSD	%XMM0,0x10(%RAX)

  (122) 0x40ed0f CMP	%R10,%RDX

  (122) 0x40ed12 JNE	40ec35

0x40ed18 MOV	0x18(%R15),%R15

0x40ed1c MOV	0x2840(%R13),%RCX

0x40ed23 MOVSXD	(%R15,%R14,4),%RDI

0x40ed27 MOV	-0xd0(%RBP),%EDX

0x40ed2d MOV	(%RCX,%RDI,8),%R15

0x40ed31 MOV	%R14D,%R9D

0x40ed34 LEA	-0x70(%RBP),%RCX

0x40ed38 MOV	$0x1,%R8D

0x40ed3e MOV	%RBX,%RSI

0x40ed41 MOV	%R15,%RDI

0x40ed44 CALL	4da300 <_ZN11qmcplusplus18VirtualParticleSet9makeMovesERKNS_11ParticleSetEiRKSt6vectorINS_10TinyVectorIdLj3EEESaIS6_EEbi>

0x40ed49 MOV	-0x88(%RBP),%RDI

0x40ed50 LEA	-0x50(%RBP),%RDX

0x40ed54 MOV	%R15,%RSI

0x40ed57 CALL	418250 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE>

0x40ed5c MOV	0x2858(%R13),%R15

0x40ed63 INC	%R14

0x40ed66 MOV	0x260(%R15),%R8

0x40ed6d CMP	%R8,%R14

0x40ed70 JB	40eacc

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 43 - 63

--------------------------------------------------------------------------------

43:     return (a + b);

[...]

63:     return (a * b);

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 231 - 231

--------------------------------------------------------------------------------

231:   inline const AoSElement_t operator[](size_t i) const { return AoSElement_t(myData + i, nGhosts); }

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h: 993 - 993

--------------------------------------------------------------------------------

993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp: 126 - 135

--------------------------------------------------------------------------------

126:       for (int iat = 0; iat < ions_ref.getTotalNum(); ++iat)

127:       {

128:         //due to < Rmax condition, the actually iteration iat is [0,2] in a real simulation

129:         if (dist[iat] < Rmax)

130:         {

131:           for (int k = 0; k < size(); k++)

132:             virtualPos[k] = dist[iat] * rOnSphere[k] + displ[iat] + els.R[jel];

133:           auto& VP = *VPs[ions_ref.GroupID[iat]];

134:           VP.makeMoves(els, jel, virtualPos, true, iat);

135:           wf.evaluateRatios(VP, ratios);

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/unique_ptr.h: 193 - 193

--------------------------------------------------------------------------------

193:       pointer    _M_ptr() const noexcept { return std::get<0>(_M_t); }

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 145 - 145

--------------------------------------------------------------------------------

145:       X[i] = base[i * offset];

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 229 - 229

--------------------------------------------------------------------------------

229:     return X[i];

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 277 - 277

--------------------------------------------------------------------------------

277:   inline size_t getTotalNum() const { return TotalNum; }

Coverage (%)	Name	Source Location	Module
○97.89	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.11	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.74
CQA speedup if FP arith vectorized	1.79
CQA speedup if fully vectorized	9.85
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15
Bottlenecks	micro-operation queue,
Function	main._omp_fn.1
Source	OperatorTags.h:43-43,OperatorTags.h:63-63,VectorSoAContainer.h:231-231,stl_vector.h:993-993,NonLocalPP.hpp:126-126,NonLocalPP.hpp:129-135,unique_ptr.h:193-193,TinyVector.h:145-145,OhmmsVector.h:229-229,ParticleSet.h:277-277
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.83
CQA cycles if no scalar integer	9.67
CQA cycles if FP arith vectorized	9.42
CQA cycles if fully vectorized	1.71
Front-end cycles	16.83
P0 cycles	8.20
P1 cycles	8.30
P2 cycles	14.67
P3 cycles	14.67
P4 cycles	4.00
P5 cycles	8.20
P6 cycles	8.10
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	8.20
P11 cycles	14.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	99.00
Nb uops	101.00
Nb loads	44.00
Nb stores	6.00
Nb stack references	7.00
FLOP/cycle	1.60
Nb FLOP add-sub	9.00
Nb FLOP mul	0.00
Nb FLOP fma	9.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.33
Bytes prefetched	0.00
Bytes loaded	388.00
Bytes stored	72.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	23.08
Vectorization ratio load	23.08
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	50.00
Vectorization ratio fma	50.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	15.22
Vector-efficiency ratio load	15.38
Vector-efficiency ratio store	18.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	18.75
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.72

Metric	Value
CQA speedup if no scalar integer	1.74
CQA speedup if FP arith vectorized	1.79
CQA speedup if fully vectorized	9.85
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15
Bottlenecks	micro-operation queue,
Function	main._omp_fn.1
Source	OperatorTags.h:43-43,OperatorTags.h:63-63,VectorSoAContainer.h:231-231,stl_vector.h:993-993,NonLocalPP.hpp:126-126,NonLocalPP.hpp:129-135,unique_ptr.h:193-193,TinyVector.h:145-145,OhmmsVector.h:229-229,ParticleSet.h:277-277
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.83
CQA cycles if no scalar integer	9.67
CQA cycles if FP arith vectorized	9.42
CQA cycles if fully vectorized	1.71
Front-end cycles	16.83
P0 cycles	8.20
P1 cycles	8.30
P2 cycles	14.67
P3 cycles	14.67
P4 cycles	4.00
P5 cycles	8.20
P6 cycles	8.10
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	8.20
P11 cycles	14.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	99.00
Nb uops	101.00
Nb loads	44.00
Nb stores	6.00
Nb stack references	7.00
FLOP/cycle	1.60
Nb FLOP add-sub	9.00
Nb FLOP mul	0.00
Nb FLOP fma	9.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.33
Bytes prefetched	0.00
Bytes loaded	388.00
Bytes stored	72.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	23.08
Vectorization ratio load	23.08
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	50.00
Vectorization ratio fma	50.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	15.22
Vector-efficiency ratio load	15.38
Vector-efficiency ratio store	18.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	18.75
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.72

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.1
Source file and lines	OperatorTags.h:43-63
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43,63
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:993
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:126-135
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/unique_ptr.h:193
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:229
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:277

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=10
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 10 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.83 to 9.67 cycles (1.74x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 16.83 to 1.71 cycles (9.85x speedup).

Details

23% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

23% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 9 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

qmcplusplus::VirtualParticleSet::makeMoves(qmcplusplus::ParticleSet const&, int, std::vector
, std::allocator
> > const&, bool, int): 1 occurrences►
qmcplusplus::WaveFunction::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector
>&): 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:129

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 27 FP arithmetical operations:

18: addition or subtraction (9 inside FMA instructions)
9: multiply (all inside FMA instructions)

The binary loop is loading 388 bytes (48 double precision FP elements). The binary loop is storing 72 bytes (9 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	99
nb uops	101
loop length	467
used x86 registers	15
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	16.83 cycles
front end	16.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.20	8.30	14.67	14.67	4.00	8.20	8.10	4.00	4.00	4.00	8.20	14.67
cycles	8.20	8.30	14.67	14.67	4.00	8.20	8.10	4.00	4.00	4.00	8.20	14.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.83
Dispatch	14.67
Overall L1	16.83

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	25%
load	23%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	23%
load	23%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	15%
load	15%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	15%
load	15%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.83 cycles. At this rate:

12% of peak load performance is reached (23.05 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.28 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.83 to 14.67 cycles (1.15x speedup).

ASM code

In the binary file, the address of the loop is: 40eacc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
INC %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 40ed76 <main._omp_fn.1+0x30e6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xb0(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R14,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x18(%R11),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%RCX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCOMISD 0x1440(%R13),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 40eac0 <main._omp_fn.1+0x2e30>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x2830(%R13),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $-0x5555555555555555,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
SUB 0x2828(%R13),%R10	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
SAR $0x3,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
IMUL %R8,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
TEST %R10D,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 40ed18 <main._omp_fn.1+0x3088>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x90(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DEC %R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD 0x8(%RAX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RAX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R11,%R14,1),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R9,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RDX,%R9,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x118(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%R11,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R10,%R10,2),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R12,%R11,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R11,%R11,2),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RDX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x70(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD 0x40(%RBX),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x3,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 40ece0 <main._omp_fn.1+0x3050>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RDI),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R9),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVHPD (%R8),%XMM5,%XMM6	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
VADDPD (%RSI),%XMM6,%XMM4	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (25.0%)
VADDSD 0x10(%RSI),%XMM3,%XMM13	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVDDUP %XMM0,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VFMADD231PD (%R12),%XMM2,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD132SD 0x10(%R12),%XMM13,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x18(%R12),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVUPD %XMM4,-0x18(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM0,-0x8(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RCX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP $0x1,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40ece0 <main._omp_fn.1+0x3050>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40ebf4 <main._omp_fn.1+0x2f64>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RDI),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R9),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVHPD (%R8),%XMM9,%XMM8	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
VADDPD (%RSI),%XMM8,%XMM7	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (25.0%)
VADDSD 0x10(%RSI),%XMM15,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVDDUP %XMM0,%XMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VFMADD231PD 0x18(%R12),%XMM10,%XMM7	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD132SD 0x10(%RDX),%XMM1,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x30(%R12),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVUPD %XMM7,-0x18(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM0,-0x8(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RCX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RDI),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R9),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVHPD (%R8),%XMM14,%XMM3	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
VADDPD (%RSI),%XMM3,%XMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (25.0%)
VADDSD 0x10(%RSI),%XMM11,%XMM5	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVDDUP %XMM0,%XMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VFMADD231PD (%RDX),%XMM12,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD132SD 0x10(%RDX),%XMM5,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %XMM2,-0x18(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM0,-0x8(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RCX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 40ece0 <main._omp_fn.1+0x3050>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV 0x18(%R15),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2840(%R13),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD (%R15,%R14,4),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xd0(%RBP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RDI,8),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R14D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x70(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x1,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4da300 <_ZN11qmcplusplus18VirtualParticleSet9makeMovesERKNS_11ParticleSetEiRKSt6vectorINS_10TinyVectorIdLj3EEESaIS6_EEbi>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x88(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA -0x50(%RBP),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 418250 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x2858(%R13),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x260(%R15),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R8,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JB 40eacc <main._omp_fn.1+0x2e3c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	main._omp_fn.1
Source file and lines	OperatorTags.h:43-63
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43,63
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:993
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:126-135
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/unique_ptr.h:193
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:229
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:277

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=10
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.83 to 9.67 cycles (1.74x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

23% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

23% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 9 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

qmcplusplus::VirtualParticleSet::makeMoves(qmcplusplus::ParticleSet const&, int, std::vector
, std::allocator
> > const&, bool, int): 1 occurrences►
qmcplusplus::WaveFunction::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector
>&): 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:129

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 27 FP arithmetical operations:

18: addition or subtraction (9 inside FMA instructions)
9: multiply (all inside FMA instructions)

The binary loop is loading 388 bytes (48 double precision FP elements). The binary loop is storing 72 bytes (9 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	99
nb uops	101
loop length	467
used x86 registers	15
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	16.83 cycles
front end	16.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.20	8.30	14.67	14.67	4.00	8.20	8.10	4.00	4.00	4.00	8.20	14.67
cycles	8.20	8.30	14.67	14.67	4.00	8.20	8.10	4.00	4.00	4.00	8.20	14.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.83
Dispatch	14.67
Overall L1	16.83

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	25%
load	23%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	23%
load	23%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	15%
load	15%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	15%
load	15%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.83 cycles. At this rate:

12% of peak load performance is reached (23.05 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.28 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 40eacc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
INC %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 40ed76 <main._omp_fn.1+0x30e6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xb0(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R14,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x18(%R11),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%RCX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCOMISD 0x1440(%R13),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 40eac0 <main._omp_fn.1+0x2e30>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x2830(%R13),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $-0x5555555555555555,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
SUB 0x2828(%R13),%R10	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
SAR $0x3,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
IMUL %R8,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
TEST %R10D,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 40ed18 <main._omp_fn.1+0x3088>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x90(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DEC %R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD 0x8(%RAX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RAX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R11,%R14,1),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R9,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RDX,%R9,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x118(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%R11,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R10,%R10,2),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R12,%R11,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R11,%R11,2),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RDX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x70(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD 0x40(%RBX),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x3,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 40ece0 <main._omp_fn.1+0x3050>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RDI),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R9),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVHPD (%R8),%XMM5,%XMM6	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
VADDPD (%RSI),%XMM6,%XMM4	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (25.0%)
VADDSD 0x10(%RSI),%XMM3,%XMM13	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVDDUP %XMM0,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VFMADD231PD (%R12),%XMM2,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD132SD 0x10(%R12),%XMM13,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x18(%R12),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVUPD %XMM4,-0x18(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM0,-0x8(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RCX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP $0x1,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40ece0 <main._omp_fn.1+0x3050>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40ebf4 <main._omp_fn.1+0x2f64>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RDI),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R9),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVHPD (%R8),%XMM9,%XMM8	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
VADDPD (%RSI),%XMM8,%XMM7	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (25.0%)
VADDSD 0x10(%RSI),%XMM15,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVDDUP %XMM0,%XMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VFMADD231PD 0x18(%R12),%XMM10,%XMM7	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD132SD 0x10(%RDX),%XMM1,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x30(%R12),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVUPD %XMM7,-0x18(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM0,-0x8(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RCX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RDI),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R9),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVHPD (%R8),%XMM14,%XMM3	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
VADDPD (%RSI),%XMM3,%XMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (25.0%)
VADDSD 0x10(%RSI),%XMM11,%XMM5	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVDDUP %XMM0,%XMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VFMADD231PD (%RDX),%XMM12,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD132SD 0x10(%RDX),%XMM5,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %XMM2,-0x18(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM0,-0x8(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RCX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 40ece0 <main._omp_fn.1+0x3050>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV 0x18(%R15),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2840(%R13),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD (%R15,%R14,4),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xd0(%RBP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RDI,8),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R14D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x70(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x1,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4da300 <_ZN11qmcplusplus18VirtualParticleSet9makeMovesERKNS_11ParticleSetEiRKSt6vectorINS_10TinyVectorIdLj3EEESaIS6_EEbi>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x88(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA -0x50(%RBP),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 418250 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x2858(%R13),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x260(%R15),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R8,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JB 40eacc <main._omp_fn.1+0x2e3c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code