OV - exec - Loop 1126

0x49b280 VMOVUPD	(%RCX,%RAX,1),%YMM11    [2]

0x49b285 VMOVUPD	0x20(%RCX,%RAX,1),%YMM12    [2]

0x49b28b VFMADD231PD	(%R10,%RAX,1),%YMM11,%YMM8    [1]

0x49b291 VMOVUPD	0x40(%RCX,%RAX,1),%YMM13    [2]

0x49b297 VMOVUPD	0x60(%RCX,%RAX,1),%YMM14    [2]

0x49b29d VMOVUPD	0x80(%RCX,%RAX,1),%YMM15    [2]

0x49b2a6 VMOVUPD	0xa0(%RCX,%RAX,1),%YMM0    [2]

0x49b2af VFMADD231PD	0x20(%R10,%RAX,1),%YMM12,%YMM8    [1]

0x49b2b6 VMOVUPD	0xc0(%RCX,%RAX,1),%YMM1    [2]

0x49b2bf VMOVUPD	0xe0(%RCX,%RAX,1),%YMM2    [2]

0x49b2c8 VFMADD231PD	0x40(%R10,%RAX,1),%YMM13,%YMM8    [1]

0x49b2cf VFMADD231PD	0x60(%R10,%RAX,1),%YMM14,%YMM8    [1]

0x49b2d6 VFMADD231PD	0x80(%R10,%RAX,1),%YMM15,%YMM8    [1]

0x49b2e0 VFMADD231PD	0xa0(%R10,%RAX,1),%YMM0,%YMM8    [1]

0x49b2ea VFMADD231PD	0xc0(%R10,%RAX,1),%YMM1,%YMM8    [1]

0x49b2f4 VFMADD231PD	0xe0(%R10,%RAX,1),%YMM2,%YMM8    [1]

0x49b2fe ADD	$0x100,%RAX

0x49b304 CMP	%RAX,%RDX

0x49b307 JNE	49b280

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 82 - 83

--------------------------------------------------------------------------------

82:   for (int i = 0; i < n; i++)

83:     res += a[i] * b[i];

Coverage (%)	Name	Source Location	Module
►49.57+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:266	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►48.20+	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:993	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►1.20+	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:993	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
►1.03+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:266	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.23
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	6.00
Bottlenecks
Function	miniqmcreference::DiracDeterminantRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	inner_product.hpp:82-83
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	32.00
CQA cycles if no scalar integer	32.00
CQA cycles if FP arith vectorized	26.11
CQA cycles if fully vectorized	16.00
Front-end cycles	4.33
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	5.33
P3 cycles	5.33
P4 cycles	0.00
P5 cycles	0.60
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.40
P11 cycles	5.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	32
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	18.00
Nb loads	16.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	32.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.23
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	6.00
Bottlenecks
Function	miniqmcreference::DiracDeterminantRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	inner_product.hpp:82-83
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	32.00
CQA cycles if no scalar integer	32.00
CQA cycles if FP arith vectorized	26.11
CQA cycles if fully vectorized	16.00
Front-end cycles	4.33
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	5.33
P3 cycles	5.33
P4 cycles	0.00
P5 cycles	0.60
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.40
P11 cycles	5.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	32
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	18.00
Nb loads	16.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	32.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::DiracDeterminantRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	inner_product.hpp:82-83
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 32 FMA (fused multiply-add) operations.

Vector unaligned load/store instructions

Detected 8 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:83
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:83
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:83
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:83
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:83
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:83
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:83
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:83

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

8 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

32: addition or subtraction (all inside FMA instructions)
32: multiply (all inside FMA instructions)

The binary loop is loading 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	19
nb uops	18
loop length	141
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	9
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.33 cycles
front end	4.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.00	4.00	5.33	5.33	0.00	0.60	1.00	0.00	0.00	0.00	0.40	5.33
cycles	4.00	4.00	5.33	5.33	0.00	0.60	1.00	0.00	0.00	0.00	0.40	5.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	32.00

Cycles summary

Front-end	4.33
Dispatch	5.33
Data deps.	32.00
Overall L1	32.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.00 cycles. At this rate:

8% of peak load performance is reached (16.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 49b280

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%RCX,%RAX,1),%YMM11	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%RCX,%RAX,1),%YMM12	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD231PD (%R10,%RAX,1),%YMM11,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMOVUPD 0x40(%RCX,%RAX,1),%YMM13	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x60(%RCX,%RAX,1),%YMM14	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x80(%RCX,%RAX,1),%YMM15	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0xa0(%RCX,%RAX,1),%YMM0	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD231PD 0x20(%R10,%RAX,1),%YMM12,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMOVUPD 0xc0(%RCX,%RAX,1),%YMM1	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0xe0(%RCX,%RAX,1),%YMM2	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD231PD 0x40(%R10,%RAX,1),%YMM13,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x60(%R10,%RAX,1),%YMM14,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x80(%R10,%RAX,1),%YMM15,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0xa0(%R10,%RAX,1),%YMM0,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0xc0(%R10,%RAX,1),%YMM1,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0xe0(%R10,%RAX,1),%YMM2,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
ADD $0x100,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
CMP %RAX,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 49b280 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x370>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	miniqmcreference::DiracDeterminantRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	inner_product.hpp:82-83
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 32 FMA (fused multiply-add) operations.

Vector unaligned load/store instructions

Detected 8 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:83
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:83
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:83
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:83
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:83
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:83
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:83
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:83

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

8 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

32: addition or subtraction (all inside FMA instructions)
32: multiply (all inside FMA instructions)

The binary loop is loading 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	19
nb uops	18
loop length	141
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	9
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.33 cycles
front end	4.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.00	4.00	5.33	5.33	0.00	0.60	1.00	0.00	0.00	0.00	0.40	5.33
cycles	4.00	4.00	5.33	5.33	0.00	0.60	1.00	0.00	0.00	0.00	0.40	5.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	32.00

Cycles summary

Front-end	4.33
Dispatch	5.33
Data deps.	32.00
Overall L1	32.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.00 cycles. At this rate:

8% of peak load performance is reached (16.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 49b280

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%RCX,%RAX,1),%YMM11	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%RCX,%RAX,1),%YMM12	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD231PD (%R10,%RAX,1),%YMM11,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMOVUPD 0x40(%RCX,%RAX,1),%YMM13	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x60(%RCX,%RAX,1),%YMM14	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x80(%RCX,%RAX,1),%YMM15	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0xa0(%RCX,%RAX,1),%YMM0	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD231PD 0x20(%R10,%RAX,1),%YMM12,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VMOVUPD 0xc0(%RCX,%RAX,1),%YMM1	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0xe0(%RCX,%RAX,1),%YMM2	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD231PD 0x40(%R10,%RAX,1),%YMM13,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x60(%R10,%RAX,1),%YMM14,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0x80(%R10,%RAX,1),%YMM15,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0xa0(%R10,%RAX,1),%YMM0,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0xc0(%R10,%RAX,1),%YMM1,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD231PD 0xe0(%R10,%RAX,1),%YMM2,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
ADD $0x100,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
CMP %RAX,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 49b280 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x370>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code