OV - exec - Function miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::resize(int, int)

	Function: miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::resize ...	Module: exec	Source: DiracDeterminantRef.cpp:61-79 [...]	Coverage (incl. loops): 0.03% \| (excl. loops): 0.00%

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/alloc_traits.h: 513 - 513

--------------------------------------------------------------------------------

513:       { __a.deallocate(__p, __n); }

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_construct.h: 119 - 119

--------------------------------------------------------------------------------

119:       ::new((void*)__p) _Tp(std::forward<_Args>(__args)...);

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h: 62 - 62

--------------------------------------------------------------------------------

62:     V.resize(delay, norb);

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_uninitialized.h: 667 - 1129

--------------------------------------------------------------------------------

667: 	      ++__first;

[...]

1117:       if (__count > 0)

[...]

1129: 	  __builtin_memcpy(__result, __first, __count * sizeof(_Tp));

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp: 61 - 79

--------------------------------------------------------------------------------

61: void DiracDeterminantRef<DU_TYPE>::resize(int nel, int morb)

62: {

63:   int norb = morb;

64:   if (norb <= 0)

65:     norb = nel; // for morb == -1 (default)

66:   updateEng.resize(norb, ndelay);

67:   psiM.resize(nel, norb);

[...]

73:   LastIndex   = FirstIndex + nel;

74:   NumPtcls    = nel;

75:   NumOrbitals = norb;

76:

77:   dpsiV.resize(NumOrbitals);

78:   d2psiV.resize(NumOrbitals);

79: }

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h: 993 - 1949

--------------------------------------------------------------------------------

993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1015: 	if (__new_size > size())

1016: 	  _M_default_append(__new_size - size());

1017: 	else if (__new_size < size())

1018: 	  _M_erase_at_end(this->_M_impl._M_start + __new_size);

[...]

1908: 	if (max_size() - size() < __n)

1909: 	  __throw_length_error(__N(__s));

1910:

1911: 	const size_type __len = size() + (std::max)(size(), __n);

[...]

1945: 	if (size_type __n = this->_M_impl._M_finish - __pos)

1946: 	  {

1947: 	    std::_Destroy(__pos, this->_M_impl._M_finish,

1948: 			  _M_get_Tp_allocator());

1949: 	    this->_M_impl._M_finish = __pos;

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h: 101 - 103

--------------------------------------------------------------------------------

101:     D1      = n;

102:     D2      = m;

103:     TotSize = n * m;

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/new_allocator.h: 134 - 172

--------------------------------------------------------------------------------

134: 	if (__builtin_expect(__n > this->_M_max_size(), false))

135: 	  {

136: 	    // _GLIBCXX_RESOLVE_LIB_DEFECTS

137: 	    // 3190. allocator::allocate sometimes returns too little storage

138: 	    if (__n > (std::size_t(-1) / sizeof(_Tp)))

139: 	      std::__throw_bad_array_new_length();

140: 	    std::__throw_bad_alloc();

[...]

151: 	return static_cast<_Tp*>(_GLIBCXX_OPERATOR_NEW(__n * sizeof(_Tp)));

[...]

172: 	_GLIBCXX_OPERATOR_DELETE(_GLIBCXX_SIZED_DEALLOC(__p, __n));

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h: 262 - 1151

--------------------------------------------------------------------------------

262:       if (__a < __b)

[...]

939:       for (; __first != __last; ++__first)

940: 	*__first = __value;

[...]

951:       for (; __first != __last; ++__first)

952: 	*__first = __tmp;

[...]

1146:       if (__n <= 0)

1147: 	return __first;

1148:

1149:       __glibcxx_requires_can_increment(__first, __n);

1150:

1151:       std::__fill_a(__first, __first + __n, __value);

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/vector.tcc: 812 - 910

--------------------------------------------------------------------------------

812: 					 - this->_M_impl._M_finish);

813:

814: 	  if (__size > max_size() || __navail > max_size() - __size)

815: 	    __builtin_unreachable();

816:

817: 	  if (__navail >= __n)

818: 	    {

819: 	      _GLIBCXX_ASAN_ANNOTATE_GROW(__n);

820: 	      this->_M_impl._M_finish =

[...]

851: 		  if (_M_storage)

[...]

863: 		std::__uninitialized_default_n_a(__new_start + __size, __n,

[...]

903: 		__guard._M_len = this->_M_impl._M_end_of_storage - __old_start;

904: 	      }

905: 	      // deallocate should be called before assignments to _M_impl,

906: 	      // to avoid call-clobbering

907:

908: 	      this->_M_impl._M_start = __new_start;

909: 	      this->_M_impl._M_finish = __new_start + __size + __n;

910: 	      this->_M_impl._M_end_of_storage = __new_start + __len;

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 181 - 301

--------------------------------------------------------------------------------

181:   inline void resize(size_t n, Type_t val = Type_t())

182:   {

183:     static_assert(std::is_same<value_type, typename Alloc::value_type>::value,

184:                   "Vector and Alloc data types must agree!");

185:     if (nLocal > nAllocated)

186:       throw std::runtime_error("Resize not allowed on Vector constructed by initialized memory.");

187:

188:     if (n > nAllocated)

[...]

195:       if (n > nLocal)

196:         qmc_allocator_traits<Alloc>::fill_n(X + nLocal, n - nLocal, val);

197:       nLocal = n;

[...]

296:     if (nAllocated)

297:     {

298:       mAllocator.deallocate(X, nAllocated);

299:     }

300:     X          = mAllocator.allocate(n);

301:     nLocal     = n;

0x4a35b0 PUSH	%RBP

0x4a35b1 VMOVD	%ESI,%XMM2

0x4a35b5 MOV	%RSP,%RBP

0x4a35b8 PUSH	%R15

0x4a35ba PUSH	%R14

0x4a35bc PUSH	%R13

0x4a35be PUSH	%R12

0x4a35c0 PUSH	%RBX

0x4a35c1 SUB	$0x88,%RSP

0x4a35c8 TEST	%EDX,%EDX

0x4a35ca CMOVLE	%ESI,%EDX

0x4a35cd VMOVD	0x488(%RDI),%XMM3

0x4a35d5 MOVSXD	%EDX,%R12

0x4a35d8 VPINSRD	$0x1,%R12D,%XMM3,%XMM7

0x4a35de VPMOVSXDQ	%XMM7,%XMM11

0x4a35e3 VMOVQ	%XMM11,%R14

0x4a35e8 MOV	%R12,%RBX

0x4a35eb IMUL	%R14,%RBX

0x4a35ef VMOVD	%R12D,%XMM5

0x4a35f4 MOV	%ESI,0x44(%RSP)

0x4a35f8 VPINSRD	$0x1,%R12D,%XMM2,%XMM0

0x4a35fe VPUNPCKLDQ	%XMM3,%XMM5,%XMM1

0x4a3602 MOV	0x268(%RDI),%RAX

0x4a3609 MOV	0x270(%RDI),%RSI

0x4a3610 VPMOVSXDQ	%XMM0,%XMM4

0x4a3615 VPMOVSXDQ	%XMM1,%XMM6

0x4a361a VPBROADCASTQ	%R12,%XMM8

0x4a3620 VPUNPCKLQDQ	%XMM11,%XMM11,%XMM9

0x4a3625 VPBROADCASTQ	%RBX,%XMM10

0x4a362b MOV	%RBX,0x258(%RDI)

0x4a3632 VMOVDQA	%XMM4,0x70(%RSP)

0x4a3638 VMOVQ	%XMM4,0x48(%RSP)

0x4a363e VMOVDQA	%XMM6,0x50(%RSP)

0x4a3644 VMOVDQA	%XMM8,0x30(%RSP)

0x4a364a VMOVDQA	%XMM9,0x60(%RSP)

0x4a3650 VMOVDQU	%XMM11,0x248(%RDI)

0x4a3658 VMOVDQA	%XMM10,0x20(%RSP)

0x4a365e CMP	%RAX,%RSI

0x4a3661 JB	4a4f7a

0x4a3667 MOV	%RDI,%R15

0x4a366a MOV	%R12,%R13

0x4a366d CMP	%RBX,%RSI

0x4a3670 JB	4a4148

0x4a3676 CMP	%RBX,%RAX

0x4a3679 JB	4a3cf0

0x4a367f MOV	%RBX,0x268(%R15)

(1182) 0x4a3686 MOV	0x228(%R15),%R8

(1182) 0x4a368d MOV	0x230(%R15),%RSI

(1182) 0x4a3694 MOV	%RBX,0x218(%R15)

(1182) 0x4a369b VMOVDQU	%XMM11,0x208(%R15)

(1182) 0x4a36a4 CMP	%R8,%RSI

(1182) 0x4a36a7 JB	4a5032

(1182) 0x4a36ad CMP	%RBX,%RSI

(1182) 0x4a36b0 JB	4a41b0

(1182) 0x4a36b6 CMP	%RBX,%R8

(1182) 0x4a36b9 JB	4a3d28

(1182) 0x4a36bf MOV	%RBX,0x228(%R15)

(1182) 0x4a36c6 MOV	0x338(%R15),%R11

(1182) 0x4a36cd MOV	0x340(%R15),%RSI

(1182) 0x4a36d4 CMP	%R11,%RSI

(1182) 0x4a36d7 JB	4a4f32

(1182) 0x4a36dd CMP	%R14,%RSI

(1182) 0x4a36e0 JB	4a4208

(1182) 0x4a36e6 CMP	%R14,%R11

(1182) 0x4a36e9 JB	4a3d50

(1182) 0x4a36ef MOV	%R14,0x338(%R15)

(1182) 0x4a36f6 MOV	0x310(%R15),%R8

(1182) 0x4a36fd MOV	0x318(%R15),%RSI

(1182) 0x4a3704 CMP	%R8,%RSI

(1182) 0x4a3707 JB	4a4f99

(1182) 0x4a370d CMP	%R12,%RSI

(1182) 0x4a3710 JB	4a4260

(1182) 0x4a3716 CMP	%R12,%R8

(1182) 0x4a3719 JB	4a3d80

(1182) 0x4a371f MOV	%R12,0x310(%R15)

(1182) 0x4a3726 VMOVDQA	0x50(%RSP),%XMM2

(1182) 0x4a372c MOV	0x2e8(%R15),%R10

(1182) 0x4a3733 MOV	0x2f0(%R15),%RSI

(1182) 0x4a373a MOV	%RBX,0x2d8(%R15)

(1182) 0x4a3741 VMOVDQU	%XMM2,0x2c8(%R15)

(1182) 0x4a374a CMP	%R10,%RSI

(1182) 0x4a374d JB	4a4eae

(1182) 0x4a3753 CMP	%RBX,%RSI

(1182) 0x4a3756 JB	4a42b8

(1182) 0x4a375c CMP	%RBX,%R10

(1182) 0x4a375f JB	4a3db0

(1182) 0x4a3765 MOV	%RBX,0x2e8(%R15)

(1182) 0x4a376c MOV	%R14,%RCX

(1182) 0x4a376f IMUL	%R14,%RCX

(1182) 0x4a3773 VMOVDQA	0x60(%RSP),%XMM4

(1182) 0x4a3779 MOV	0x2a8(%R15),%RBX

(1182) 0x4a3780 MOV	0x2b0(%R15),%RSI

(1182) 0x4a3787 MOV	%RCX,0x298(%R15)

(1182) 0x4a378e VMOVDQU	%XMM4,0x288(%R15)

(1182) 0x4a3797 CMP	%RBX,%RSI

(1182) 0x4a379a JB	4a4f51

(1182) 0x4a37a0 CMP	%RCX,%RSI

(1182) 0x4a37a3 JB	4a4308

(1182) 0x4a37a9 CMP	%RCX,%RBX

(1182) 0x4a37ac JB	4a3de0

(1182) 0x4a37b2 MOV	%RCX,0x2a8(%R15)

(1182) 0x4a37b9 MOV	0x360(%R15),%R10

(1182) 0x4a37c0 MOV	0x358(%R15),%R11

(1182) 0x4a37c7 MOV	%R10,%RBX

(1182) 0x4a37ca SUB	%R11,%RBX

(1182) 0x4a37cd MOV	%RBX,%RAX

(1182) 0x4a37d0 SAR	$0x2,%RAX

(1182) 0x4a37d4 CMP	%R14,%RAX

(1182) 0x4a37d7 JB	4a4370

(1182) 0x4a37dd CMP	%RAX,%R14

(1182) 0x4a37e0 JB	4a3e18

(1182) 0x4a37e6 MOV	0x48(%RSP),%RBX

(1182) 0x4a37eb VMOVDQA	0x70(%RSP),%XMM6

(1182) 0x4a37f1 IMUL	%R12,%RBX

(1182) 0x4a37f5 MOV	0xf0(%R15),%RCX

(1182) 0x4a37fc MOV	0xf8(%R15),%RSI

(1182) 0x4a3803 VPBROADCASTQ	%RBX,%XMM7

(1182) 0x4a3809 MOV	%RBX,0xe0(%R15)

(1182) 0x4a3810 VMOVDQU	%XMM6,0xd0(%R15)

(1182) 0x4a3819 VMOVDQA	%XMM7,0x60(%RSP)

(1182) 0x4a381f CMP	%RCX,%RSI

(1182) 0x4a3822 JB	4a4e6f

(1182) 0x4a3828 CMP	%RBX,%RSI

(1182) 0x4a382b JB	4a4460

(1182) 0x4a3831 CMP	%RBX,%RCX

(1182) 0x4a3834 JB	4a3e38

(1182) 0x4a383a MOV	%RBX,0xf0(%R15)

(1182) 0x4a3841 VMOVDQA	0x70(%RSP),%XMM9

(1182) 0x4a3847 MOV	0x130(%R15),%RSI

(1182) 0x4a384e MOV	0x138(%R15),%R8

(1182) 0x4a3855 MOV	%RBX,0x120(%R15)

(1182) 0x4a385c VMOVDQU	%XMM9,0x110(%R15)

(1182) 0x4a3865 CMP	%RSI,%R8

(1182) 0x4a3868 JB	4a4e92

(1182) 0x4a386e CMP	%RBX,%R8

(1182) 0x4a3871 JB	4a44b0

(1182) 0x4a3877 CMP	%RBX,%RSI

(1182) 0x4a387a JB	4a3e60

(1182) 0x4a3880 MOV	%RBX,0x130(%R15)

(1182) 0x4a3887 VMOVDQA	0x70(%RSP),%XMM0

(1182) 0x4a388d MOV	0x170(%R15),%R9

(1182) 0x4a3894 MOV	0x178(%R15),%RSI

(1182) 0x4a389b MOV	%RBX,0x160(%R15)

(1182) 0x4a38a2 VMOVDQU	%XMM0,0x150(%R15)

(1182) 0x4a38ab CMP	%R9,%RSI

(1182) 0x4a38ae JB	4a4eca

(1182) 0x4a38b4 CMP	%RBX,%RSI

(1182) 0x4a38b7 JB	4a4760

(1182) 0x4a38bd CMP	%RBX,%R9

(1182) 0x4a38c0 JB	4a40c0

(1182) 0x4a38c6 MOV	%RBX,0x170(%R15)

(1182) 0x4a38cd MOV	0x198(%R15),%R10

(1182) 0x4a38d4 MOV	0x1a0(%R15),%RSI

(1182) 0x4a38db CMP	%R10,%RSI

(1182) 0x4a38de JB	4a4e40

(1182) 0x4a38e4 CMP	%R12,%RSI

(1182) 0x4a38e7 JB	4a40f0

(1182) 0x4a38ed CMP	%R12,%R10

(1182) 0x4a38f0 JAE	4a3913

(1182) 0x4a38f2 MOV	%R12,%RDX

(1182) 0x4a38f5 MOV	0x1a8(%R15),%RAX

(1182) 0x4a38fc SUB	%R10,%RDX

(1182) 0x4a38ff SAL	$0x3,%RDX

(1182) 0x4a3903 LEA	(%RAX,%R10,8),%RDI

(1182) 0x4a3907 JE	4a3913

(1182) 0x4a3909 XOR	%ESI,%ESI

(1182) 0x4a390b VZEROUPPER

(1182) 0x4a390e CALL	404140 <memset@plt>

(1182) 0x4a3913 MOV	%R12,0x198(%R15)

(1182) 0x4a391a MOV	0x410(%R15),%R11

(1182) 0x4a3921 MOV	0x418(%R15),%RSI

(1182) 0x4a3928 CMP	%R11,%RSI

(1182) 0x4a392b JB	4a4fc2

(1182) 0x4a3931 CMP	%R12,%RSI

(1182) 0x4a3934 JB	4a47b8

(1182) 0x4a393a CMP	%R12,%R11

(1182) 0x4a393d JAE	4a3960

(1182) 0x4a393f MOV	0x420(%R15),%RDX

(1182) 0x4a3946 LEA	(%RDX,%R11,8),%RDI

(1182) 0x4a394a MOV	%R12,%RDX

(1182) 0x4a394d SUB	%R11,%RDX

(1182) 0x4a3950 SAL	$0x3,%RDX

(1182) 0x4a3954 JE	4a3960

(1182) 0x4a3956 XOR	%ESI,%ESI

(1182) 0x4a3958 VZEROUPPER

(1182) 0x4a395b CALL	404140 <memset@plt>

(1182) 0x4a3960 MOV	%R12,0x410(%R15)

(1182) 0x4a3967 VMOVDQA	0x70(%RSP),%XMM1

(1182) 0x4a396d MOV	0xb0(%R15),%R9

(1182) 0x4a3974 MOV	0xb8(%R15),%RSI

(1182) 0x4a397b MOV	%RBX,0xa0(%R15)

(1182) 0x4a3982 VMOVDQU	%XMM1,0x90(%R15)

(1182) 0x4a398b CMP	%R9,%RSI

(1182) 0x4a398e JB	4a4fe4

(1182) 0x4a3994 CMP	%RBX,%RSI

(1182) 0x4a3997 JB	4a4810

(1182) 0x4a399d CMP	%RBX,%R9

(1182) 0x4a39a0 JAE	4a39c3

(1182) 0x4a39a2 MOV	%RBX,%RDX

(1182) 0x4a39a5 MOV	0xc0(%R15),%RDI

(1182) 0x4a39ac SUB	%R9,%RDX

(1182) 0x4a39af SAL	$0x3,%RDX

(1182) 0x4a39b3 LEA	(%RDI,%R9,8),%RDI

(1182) 0x4a39b7 JE	4a39c3

(1182) 0x4a39b9 XOR	%ESI,%ESI

(1182) 0x4a39bb VZEROUPPER

(1182) 0x4a39be CALL	404140 <memset@plt>

(1182) 0x4a39c3 MOV	%RBX,0xb0(%R15)

(1182) 0x4a39ca MOV	0x44(%RSP),%EBX

(1182) 0x4a39ce MOV	0x478(%R15),%R10D

(1182) 0x4a39d5 MOV	0x1c8(%R15),%RAX

(1182) 0x4a39dc ADD	%EBX,%R10D

(1182) 0x4a39df VMOVD	%R10D,%XMM7

(1182) 0x4a39e4 VPINSRD	$0x1,%R13D,%XMM7,%XMM8

(1182) 0x4a39ea MOV	0x1c0(%R15),%R13

(1182) 0x4a39f1 MOV	%EBX,0x484(%R15)

(1182) 0x4a39f8 VMOVQ	%XMM8,0x47c(%R15)

(1182) 0x4a3a01 CMP	%R13,%RAX

(1182) 0x4a3a04 JB	4a5010

(1182) 0x4a3a0a CMP	%R12,%RAX

(1182) 0x4a3a0d JB	4a4860

(1182) 0x4a3a13 CMP	%R12,%R13

(1182) 0x4a3a16 JAE	4a3c81

(1182) 0x4a3a1c MOV	%R12,%RDX

(1182) 0x4a3a1f SUB	%R13,%RDX

(1182) 0x4a3a22 MOV	0x1d0(%R15),%RCX

(1182) 0x4a3a29 LEA	(%RDX,%RDX,2),%RSI

(1182) 0x4a3a2d LEA	(%R13,%R13,2),%R11

(1182) 0x4a3a32 SAL	$0x3,%RSI

(1182) 0x4a3a36 LEA	(%RCX,%R11,8),%R8

(1182) 0x4a3a3a JE	4a3c81

(1182) 0x4a3a40 LEA	-0x18(%RSI),%R14

(1182) 0x4a3a44 SHR	$0x3,%R14

(1182) 0x4a3a48 MOV	$0xaaaaaaaaaaaaaab,%R9

(1182) 0x4a3a52 IMUL	%R9,%R14

(1182) 0x4a3a56 MOV	$0x1fffffffffffffff,%RDI

(1182) 0x4a3a60 AND	%RDI,%R14

(1182) 0x4a3a63 LEA	0x1(%R14),%R10

(1182) 0x4a3a67 CMP	$0x2,%R14

(1182) 0x4a3a6b JBE	4a4e20

(1182) 0x4a3a71 MOV	%R10,%R11

(1182) 0x4a3a74 SHR	$0x2,%R11

(1182) 0x4a3a78 LEA	(%R11,%R11,2),%RDX

(1182) 0x4a3a7c SAL	$0x5,%RDX

(1182) 0x4a3a80 LEA	(%RDX,%R8,1),%RSI

(1182) 0x4a3a84 SUB	$0x60,%RDX

(1182) 0x4a3a88 SHR	$0x5,%RDX

(1182) 0x4a3a8c MOV	$0x2aaaaaaaaaaaaab,%R9

(1182) 0x4a3a96 IMUL	%R9,%RDX

(1182) 0x4a3a9a MOV	%R8,%RAX

(1182) 0x4a3a9d VXORPD	%XMM9,%XMM9,%XMM9

(1182) 0x4a3aa2 INC	%RDX

(1182) 0x4a3aa5 AND	$0x7,%EDX

(1182) 0x4a3aa8 JE	4a3b60

(1182) 0x4a3aae CMP	$0x1,%RDX

(1182) 0x4a3ab2 JE	4a3b45

(1182) 0x4a3ab8 CMP	$0x2,%RDX

(1182) 0x4a3abc JE	4a3b33

(1182) 0x4a3abe CMP	$0x3,%RDX

(1182) 0x4a3ac2 JE	4a3b21

(1182) 0x4a3ac4 CMP	$0x4,%RDX

(1182) 0x4a3ac8 JE	4a3b0f

(1182) 0x4a3aca CMP	$0x5,%RDX

(1182) 0x4a3ace JE	4a3afd

(1182) 0x4a3ad0 CMP	$0x6,%RDX

(1182) 0x4a3ad4 JE	4a3aeb

(1182) 0x4a3ad6 VMOVUPD	%YMM9,(%R8)

(1182) 0x4a3adb VMOVUPD	%YMM9,0x20(%R8)

(1182) 0x4a3ae1 VMOVUPD	%YMM9,0x40(%R8)

(1182) 0x4a3ae7 LEA	0x60(%R8),%RAX

(1182) 0x4a3aeb VMOVUPD	%YMM9,(%RAX)

(1182) 0x4a3aef VMOVUPD	%YMM9,0x20(%RAX)

(1182) 0x4a3af4 VMOVUPD	%YMM9,0x40(%RAX)

(1182) 0x4a3af9 ADD	$0x60,%RAX

(1182) 0x4a3afd VMOVUPD	%YMM9,(%RAX)

(1182) 0x4a3b01 VMOVUPD	%YMM9,0x20(%RAX)

(1182) 0x4a3b06 VMOVUPD	%YMM9,0x40(%RAX)

(1182) 0x4a3b0b ADD	$0x60,%RAX

(1182) 0x4a3b0f VMOVUPD	%YMM9,(%RAX)

(1182) 0x4a3b13 VMOVUPD	%YMM9,0x20(%RAX)

(1182) 0x4a3b18 VMOVUPD	%YMM9,0x40(%RAX)

(1182) 0x4a3b1d ADD	$0x60,%RAX

(1182) 0x4a3b21 VMOVUPD	%YMM9,(%RAX)

(1182) 0x4a3b25 VMOVUPD	%YMM9,0x20(%RAX)

(1182) 0x4a3b2a VMOVUPD	%YMM9,0x40(%RAX)

(1182) 0x4a3b2f ADD	$0x60,%RAX

(1182) 0x4a3b33 VMOVUPD	%YMM9,(%RAX)

(1182) 0x4a3b37 VMOVUPD	%YMM9,0x20(%RAX)

(1182) 0x4a3b3c VMOVUPD	%YMM9,0x40(%RAX)

(1182) 0x4a3b41 ADD	$0x60,%RAX

(1182) 0x4a3b45 VMOVUPD	%YMM9,(%RAX)

(1182) 0x4a3b49 VMOVUPD	%YMM9,0x20(%RAX)

(1182) 0x4a3b4e VMOVUPD	%YMM9,0x40(%RAX)

(1182) 0x4a3b53 ADD	$0x60,%RAX

(1182) 0x4a3b57 CMP	%RAX,%RSI

(1182) 0x4a3b5a JE	4a3c22

  (1184) 0x4a3b60 VMOVUPD	%YMM9,(%RAX)

  (1184) 0x4a3b64 VMOVUPD	%YMM9,0x20(%RAX)

  (1184) 0x4a3b69 VMOVUPD	%YMM9,0x40(%RAX)

  (1184) 0x4a3b6e VMOVUPD	%YMM9,0x60(%RAX)

  (1184) 0x4a3b73 VMOVUPD	%YMM9,0x80(%RAX)

  (1184) 0x4a3b7b VMOVUPD	%YMM9,0xa0(%RAX)

  (1184) 0x4a3b83 VMOVUPD	%YMM9,0xc0(%RAX)

  (1184) 0x4a3b8b VMOVUPD	%YMM9,0xe0(%RAX)

  (1184) 0x4a3b93 VMOVUPD	%YMM9,0x100(%RAX)

  (1184) 0x4a3b9b VMOVUPD	%YMM9,0x120(%RAX)

  (1184) 0x4a3ba3 VMOVUPD	%YMM9,0x140(%RAX)

  (1184) 0x4a3bab VMOVUPD	%YMM9,0x160(%RAX)

  (1184) 0x4a3bb3 VMOVUPD	%YMM9,0x180(%RAX)

  (1184) 0x4a3bbb VMOVUPD	%YMM9,0x1a0(%RAX)

  (1184) 0x4a3bc3 VMOVUPD	%YMM9,0x1c0(%RAX)

  (1184) 0x4a3bcb VMOVUPD	%YMM9,0x1e0(%RAX)

  (1184) 0x4a3bd3 VMOVUPD	%YMM9,0x200(%RAX)

  (1184) 0x4a3bdb VMOVUPD	%YMM9,0x220(%RAX)

  (1184) 0x4a3be3 VMOVUPD	%YMM9,0x240(%RAX)

  (1184) 0x4a3beb VMOVUPD	%YMM9,0x260(%RAX)

  (1184) 0x4a3bf3 VMOVUPD	%YMM9,0x280(%RAX)

  (1184) 0x4a3bfb VMOVUPD	%YMM9,0x2a0(%RAX)

  (1184) 0x4a3c03 VMOVUPD	%YMM9,0x2c0(%RAX)

  (1184) 0x4a3c0b VMOVUPD	%YMM9,0x2e0(%RAX)

  (1184) 0x4a3c13 ADD	$0x300,%RAX

  (1184) 0x4a3c19 CMP	%RAX,%RSI

  (1184) 0x4a3c1c JNE	4a3b60

(1182) 0x4a3c22 TEST	$0x3,%R10B

(1182) 0x4a3c26 JE	4a3c81

(1182) 0x4a3c28 MOV	%R10,%RBX

(1182) 0x4a3c2b AND	$-0x4,%RBX

(1182) 0x4a3c2f LEA	(%RBX,%RBX,2),%RDI

(1182) 0x4a3c33 LEA	(%R8,%RDI,8),%R8

(1182) 0x4a3c37 SUB	%RBX,%R10

(1182) 0x4a3c3a CMP	%RBX,%R14

(1182) 0x4a3c3d JE	4a3c6f

(1182) 0x4a3c3f ADD	%R13,%RBX

(1182) 0x4a3c42 LEA	(%RBX,%RBX,2),%R13

(1182) 0x4a3c46 LEA	(%RCX,%R13,8),%RCX

(1182) 0x4a3c4a VXORPD	%XMM10,%XMM10,%XMM10

(1182) 0x4a3c4f VMOVUPD	%XMM10,(%RCX)

(1182) 0x4a3c53 VMOVUPD	%XMM10,0x10(%RCX)

(1182) 0x4a3c58 VMOVUPD	%XMM10,0x20(%RCX)

(1182) 0x4a3c5d TEST	$0x1,%R10B

(1182) 0x4a3c61 JE	4a3c81

(1182) 0x4a3c63 AND	$-0x2,%R10

(1182) 0x4a3c67 LEA	(%R10,%R10,2),%R14

(1182) 0x4a3c6b LEA	(%R8,%R14,8),%R8

(1182) 0x4a3c6f MOVQ	$0,0x10(%R8)

(1182) 0x4a3c77 VXORPD	%XMM11,%XMM11,%XMM11

(1182) 0x4a3c7c VMOVUPD	%XMM11,(%R8)

(1182) 0x4a3c81 MOV	%R12,0x1c0(%R15)

(1182) 0x4a3c88 VZEROUPPER

(1182) 0x4a3c8b MOV	0x1e8(%R15),%R9

(1182) 0x4a3c92 MOV	0x1f0(%R15),%RSI

(1182) 0x4a3c99 CMP	%R9,%RSI

(1182) 0x4a3c9c JB	4a4eec

(1182) 0x4a3ca2 CMP	%R12,%RSI

(1182) 0x4a3ca5 JB	4a4af8

0x4a3cab CMP	%R12,%R9

0x4a3cae JAE	4a3cce

0x4a3cb0 MOV	%R12,%RDX

0x4a3cb3 MOV	0x1f8(%R15),%RSI

0x4a3cba SUB	%R9,%RDX

0x4a3cbd SAL	$0x3,%RDX

0x4a3cc1 LEA	(%RSI,%R9,8),%RDI

0x4a3cc5 JE	4a3cce

0x4a3cc7 XOR	%ESI,%ESI

0x4a3cc9 CALL	404140 <memset@plt>

0x4a3cce MOV	%R12,0x1e8(%R15)

0x4a3cd5 ADD	$0x88,%RSP

0x4a3cdc POP	%RBX

0x4a3cdd POP	%R12

0x4a3cdf POP	%R13

0x4a3ce1 POP	%R14

0x4a3ce3 POP	%R15

0x4a3ce5 POP	%RBP

0x4a3ce6 RET

0x4a3ce7 NOPW	(%RAX,%RAX,1)

0x4a3cf0 MOV	0x278(%RDI),%RDX

0x4a3cf7 LEA	(%RDX,%RAX,8),%RDI

0x4a3cfb MOV	%RBX,%RDX

0x4a3cfe SUB	%RAX,%RDX

0x4a3d01 SAL	$0x3,%RDX

0x4a3d05 JE	4a367f

0x4a3d0b XOR	%ESI,%ESI

0x4a3d0d VMOVDQA	%XMM11,0x10(%RSP)

0x4a3d13 CALL	404140 <memset@plt>

0x4a3d18 VMOVDQA	0x10(%RSP),%XMM11

0x4a3d1e JMP	4a367f

0x4a3d23 NOPL	(%RAX,%RAX,1)

(1182) 0x4a3d28 MOV	%RBX,%RDX

(1182) 0x4a3d2b MOV	0x238(%R15),%RDI

(1182) 0x4a3d32 SUB	%R8,%RDX

(1182) 0x4a3d35 SAL	$0x3,%RDX

(1182) 0x4a3d39 LEA	(%RDI,%R8,8),%RDI

(1182) 0x4a3d3d JE	4a36bf

(1182) 0x4a3d43 XOR	%ESI,%ESI

(1182) 0x4a3d45 CALL	404140 <memset@plt>

(1182) 0x4a3d4a JMP	4a36bf

0x4a3d4f NOP

(1182) 0x4a3d50 MOV	%R14,%RDX

(1182) 0x4a3d53 MOV	0x348(%R15),%RAX

(1182) 0x4a3d5a SUB	%R11,%RDX

(1182) 0x4a3d5d SAL	$0x3,%RDX

(1182) 0x4a3d61 LEA	(%RAX,%R11,8),%RDI

(1182) 0x4a3d65 JE	4a36ef

(1182) 0x4a3d6b XOR	%ESI,%ESI

(1182) 0x4a3d6d CALL	404140 <memset@plt>

(1182) 0x4a3d72 JMP	4a36ef

0x4a3d77 NOPW	(%RAX,%RAX,1)

(1182) 0x4a3d80 MOV	%R12,%RDX

(1182) 0x4a3d83 MOV	0x320(%R15),%RSI

(1182) 0x4a3d8a SUB	%R8,%RDX

(1182) 0x4a3d8d SAL	$0x3,%RDX

(1182) 0x4a3d91 LEA	(%RSI,%R8,8),%RDI

(1182) 0x4a3d95 JE	4a371f

(1182) 0x4a3d9b XOR	%ESI,%ESI

(1182) 0x4a3d9d CALL	404140 <memset@plt>

(1182) 0x4a3da2 JMP	4a371f

0x4a3da7 NOPW	(%RAX,%RAX,1)

(1182) 0x4a3db0 MOV	%RBX,%RDX

(1182) 0x4a3db3 MOV	0x2f8(%R15),%R11

(1182) 0x4a3dba SUB	%R10,%RDX

(1182) 0x4a3dbd SAL	$0x3,%RDX

(1182) 0x4a3dc1 LEA	(%R11,%R10,8),%RDI

(1182) 0x4a3dc5 JE	4a3765

(1182) 0x4a3dcb XOR	%ESI,%ESI

(1182) 0x4a3dcd CALL	404140 <memset@plt>

(1182) 0x4a3dd2 JMP	4a3765

0x4a3dd7 NOPW	(%RAX,%RAX,1)

(1182) 0x4a3de0 MOV	0x2b8(%R15),%RDX

(1182) 0x4a3de7 LEA	(%RDX,%RBX,8),%RDI

(1182) 0x4a3deb MOV	%RCX,%RDX

(1182) 0x4a3dee SUB	%RBX,%RDX

(1182) 0x4a3df1 SAL	$0x3,%RDX

(1182) 0x4a3df5 JE	4a37b2

(1182) 0x4a3dfb XOR	%ESI,%ESI

(1182) 0x4a3dfd MOV	%RCX,0x60(%RSP)

(1182) 0x4a3e02 CALL	404140 <memset@plt>

(1182) 0x4a3e07 MOV	0x60(%RSP),%RCX

(1182) 0x4a3e0c JMP	4a37b2

0x4a3e11 NOPL	(%RAX)

(1182) 0x4a3e18 LEA	(%R11,%R14,4),%R14

(1182) 0x4a3e1c CMP	%R14,%R10

(1182) 0x4a3e1f JE	4a37e6

(1182) 0x4a3e25 MOV	%R14,0x360(%R15)

(1182) 0x4a3e2c JMP	4a37e6

0x4a3e31 NOPL	(%RAX)

(1182) 0x4a3e38 MOV	0x100(%R15),%RDX

(1182) 0x4a3e3f LEA	(%RDX,%RCX,8),%RDI

(1182) 0x4a3e43 MOV	%RBX,%RDX

(1182) 0x4a3e46 SUB	%RCX,%RDX

(1182) 0x4a3e49 SAL	$0x3,%RDX

(1182) 0x4a3e4d JE	4a383a

(1182) 0x4a3e53 XOR	%ESI,%ESI

(1182) 0x4a3e55 CALL	404140 <memset@plt>

(1182) 0x4a3e5a JMP	4a383a

0x4a3e5f NOP

(1182) 0x4a3e60 MOV	%RBX,%RAX

(1182) 0x4a3e63 SUB	%RSI,%RAX

(1182) 0x4a3e66 MOV	0x140(%R15),%RCX

(1182) 0x4a3e6d LEA	(%RAX,%RAX,2),%R9

(1182) 0x4a3e71 LEA	(%RSI,%RSI,2),%R11

(1182) 0x4a3e75 SAL	$0x3,%R9

(1182) 0x4a3e79 LEA	(%RCX,%R11,8),%RDI

(1182) 0x4a3e7d JE	4a3880

(1182) 0x4a3e83 LEA	-0x18(%R9),%RDX

(1182) 0x4a3e87 SHR	$0x3,%RDX

(1182) 0x4a3e8b MOV	$0xaaaaaaaaaaaaaab,%R10

(1182) 0x4a3e95 IMUL	%R10,%RDX

(1182) 0x4a3e99 MOV	$0x1fffffffffffffff,%R14

(1182) 0x4a3ea3 AND	%R14,%RDX

(1182) 0x4a3ea6 LEA	0x1(%RDX),%R8

(1182) 0x4a3eaa CMP	$0x2,%RDX

(1182) 0x4a3eae JBE	4a4e00

(1182) 0x4a3eb4 MOV	%R8,%R9

(1182) 0x4a3eb7 SHR	$0x2,%R9

(1182) 0x4a3ebb LEA	(%R9,%R9,2),%R10

(1182) 0x4a3ebf SAL	$0x5,%R10

(1182) 0x4a3ec3 LEA	(%R10,%RDI,1),%R11

(1182) 0x4a3ec7 SUB	$0x60,%R10

(1182) 0x4a3ecb SHR	$0x5,%R10

(1182) 0x4a3ecf MOV	$0x2aaaaaaaaaaaaab,%R14

(1182) 0x4a3ed9 IMUL	%R14,%R10

(1182) 0x4a3edd MOV	%RDI,%RAX

(1182) 0x4a3ee0 VXORPD	%XMM10,%XMM10,%XMM10

(1182) 0x4a3ee5 INC	%R10

(1182) 0x4a3ee8 AND	$0x7,%R10D

(1182) 0x4a3eec JE	4a3f8f

(1182) 0x4a3ef2 CMP	$0x1,%R10

(1182) 0x4a3ef6 JE	4a3f74

(1182) 0x4a3ef8 CMP	$0x2,%R10

(1182) 0x4a3efc JE	4a3f62

(1182) 0x4a3efe CMP	$0x3,%R10

(1182) 0x4a3f02 JE	4a3f50

(1182) 0x4a3f04 CMP	$0x4,%R10

(1182) 0x4a3f08 JE	4a3f3e

(1182) 0x4a3f0a CMP	$0x5,%R10

(1182) 0x4a3f0e JE	4a3f2c

(1182) 0x4a3f10 CMP	$0x6,%R10

(1182) 0x4a3f14 JNE	4a4d80

(1182) 0x4a3f1a VMOVUPD	%YMM10,(%RAX)

(1182) 0x4a3f1e VMOVUPD	%YMM10,0x20(%RAX)

(1182) 0x4a3f23 VMOVUPD	%YMM10,0x40(%RAX)

(1182) 0x4a3f28 ADD	$0x60,%RAX

(1182) 0x4a3f2c VMOVUPD	%YMM10,(%RAX)

(1182) 0x4a3f30 VMOVUPD	%YMM10,0x20(%RAX)

(1182) 0x4a3f35 VMOVUPD	%YMM10,0x40(%RAX)

(1182) 0x4a3f3a ADD	$0x60,%RAX

(1182) 0x4a3f3e VMOVUPD	%YMM10,(%RAX)

(1182) 0x4a3f42 VMOVUPD	%YMM10,0x20(%RAX)

(1182) 0x4a3f47 VMOVUPD	%YMM10,0x40(%RAX)

(1182) 0x4a3f4c ADD	$0x60,%RAX

(1182) 0x4a3f50 VMOVUPD	%YMM10,(%RAX)

(1182) 0x4a3f54 VMOVUPD	%YMM10,0x20(%RAX)

(1182) 0x4a3f59 VMOVUPD	%YMM10,0x40(%RAX)

(1182) 0x4a3f5e ADD	$0x60,%RAX

(1182) 0x4a3f62 VMOVUPD	%YMM10,(%RAX)

(1182) 0x4a3f66 VMOVUPD	%YMM10,0x20(%RAX)

(1182) 0x4a3f6b VMOVUPD	%YMM10,0x40(%RAX)

(1182) 0x4a3f70 ADD	$0x60,%RAX

(1182) 0x4a3f74 VMOVUPD	%YMM10,(%RAX)

(1182) 0x4a3f78 VMOVUPD	%YMM10,0x20(%RAX)

(1182) 0x4a3f7d VMOVUPD	%YMM10,0x40(%RAX)

(1182) 0x4a3f82 ADD	$0x60,%RAX

(1182) 0x4a3f86 CMP	%RAX,%R11

(1182) 0x4a3f89 JE	4a4051

  (1186) 0x4a3f8f VMOVUPD	%YMM10,(%RAX)

  (1186) 0x4a3f93 VMOVUPD	%YMM10,0x20(%RAX)

  (1186) 0x4a3f98 VMOVUPD	%YMM10,0x40(%RAX)

  (1186) 0x4a3f9d VMOVUPD	%YMM10,0x60(%RAX)

  (1186) 0x4a3fa2 VMOVUPD	%YMM10,0x80(%RAX)

  (1186) 0x4a3faa VMOVUPD	%YMM10,0xa0(%RAX)

  (1186) 0x4a3fb2 VMOVUPD	%YMM10,0xc0(%RAX)

  (1186) 0x4a3fba VMOVUPD	%YMM10,0xe0(%RAX)

  (1186) 0x4a3fc2 VMOVUPD	%YMM10,0x100(%RAX)

  (1186) 0x4a3fca VMOVUPD	%YMM10,0x120(%RAX)

  (1186) 0x4a3fd2 VMOVUPD	%YMM10,0x140(%RAX)

  (1186) 0x4a3fda VMOVUPD	%YMM10,0x160(%RAX)

  (1186) 0x4a3fe2 VMOVUPD	%YMM10,0x180(%RAX)

  (1186) 0x4a3fea VMOVUPD	%YMM10,0x1a0(%RAX)

  (1186) 0x4a3ff2 VMOVUPD	%YMM10,0x1c0(%RAX)

  (1186) 0x4a3ffa VMOVUPD	%YMM10,0x1e0(%RAX)

  (1186) 0x4a4002 VMOVUPD	%YMM10,0x200(%RAX)

  (1186) 0x4a400a VMOVUPD	%YMM10,0x220(%RAX)

  (1186) 0x4a4012 VMOVUPD	%YMM10,0x240(%RAX)

  (1186) 0x4a401a VMOVUPD	%YMM10,0x260(%RAX)

  (1186) 0x4a4022 VMOVUPD	%YMM10,0x280(%RAX)

  (1186) 0x4a402a VMOVUPD	%YMM10,0x2a0(%RAX)

  (1186) 0x4a4032 VMOVUPD	%YMM10,0x2c0(%RAX)

  (1186) 0x4a403a VMOVUPD	%YMM10,0x2e0(%RAX)

  (1186) 0x4a4042 ADD	$0x300,%RAX

  (1186) 0x4a4048 CMP	%RAX,%R11

  (1186) 0x4a404b JNE	4a3f8f

(1182) 0x4a4051 MOV	%R8,%R11

(1182) 0x4a4054 AND	$-0x4,%R11

(1182) 0x4a4058 LEA	(%R11,%R11,2),%R9

(1182) 0x4a405c LEA	(%RDI,%R9,8),%RDI

(1182) 0x4a4060 TEST	$0x3,%R8B

(1182) 0x4a4064 JE	4a3880

(1182) 0x4a406a SUB	%R11,%R8

(1182) 0x4a406d CMP	%R11,%RDX

(1182) 0x4a4070 JE	4a40a6

(1182) 0x4a4072 ADD	%RSI,%R11

(1182) 0x4a4075 LEA	(%R11,%R11,2),%RSI

(1182) 0x4a4079 LEA	(%RCX,%RSI,8),%RCX

(1182) 0x4a407d VXORPD	%XMM11,%XMM11,%XMM11

(1182) 0x4a4082 VMOVUPD	%XMM11,(%RCX)

(1182) 0x4a4086 VMOVUPD	%XMM11,0x10(%RCX)

(1182) 0x4a408b VMOVUPD	%XMM11,0x20(%RCX)

(1182) 0x4a4090 TEST	$0x1,%R8B

(1182) 0x4a4094 JE	4a3880

(1182) 0x4a409a AND	$-0x2,%R8

(1182) 0x4a409e LEA	(%R8,%R8,2),%RDX

(1182) 0x4a40a2 LEA	(%RDI,%RDX,8),%RDI

(1182) 0x4a40a6 VXORPD	%XMM12,%XMM12,%XMM12

(1182) 0x4a40ab MOVQ	$0,0x10(%RDI)

(1182) 0x4a40b3 VMOVUPD	%XMM12,(%RDI)

(1182) 0x4a40b7 JMP	4a3880

0x4a40bc NOPL	(%RAX)

(1182) 0x4a40c0 MOV	%RBX,%RDX

(1182) 0x4a40c3 MOV	0x180(%R15),%RDI

(1182) 0x4a40ca SUB	%R9,%RDX

(1182) 0x4a40cd SAL	$0x3,%RDX

(1182) 0x4a40d1 LEA	(%RDI,%R9,8),%RDI

(1182) 0x4a40d5 JE	4a38c6

(1182) 0x4a40db XOR	%ESI,%ESI

(1182) 0x4a40dd VZEROUPPER

(1182) 0x4a40e0 CALL	404140 <memset@plt>

(1182) 0x4a40e5 JMP	4a38c6

0x4a40ea NOPW	(%RAX,%RAX,1)

(1182) 0x4a40f0 TEST	%RSI,%RSI

(1182) 0x4a40f3 JNE	4a4c30

(1182) 0x4a40f9 VZEROUPPER

(1182) 0x4a40fc MOV	%R12,%RCX

(1182) 0x4a40ff SHR	$0x3c,%RCX

(1182) 0x4a4103 JNE	4a4cd0

(1182) 0x4a4109 LEA	(,%R12,8),%R14

(1182) 0x4a4111 MOV	%R14,%RDI

(1182) 0x4a4114 CALL	404430 <_Znwm@plt>

(1182) 0x4a4119 MOV	%RAX,0x1a8(%R15)

(1182) 0x4a4120 VMOVDQA	0x30(%RSP),%XMM3

(1182) 0x4a4126 MOV	%RAX,%RDI

(1182) 0x4a4129 VMOVDQU	%XMM3,0x198(%R15)

(1182) 0x4a4132 MOV	%R14,%RDX

(1182) 0x4a4135 XOR	%ESI,%ESI

(1182) 0x4a4137 CALL	404140 <memset@plt>

(1182) 0x4a413c JMP	4a391a

0x4a4141 NOPL	(%RAX)

0x4a4148 TEST	%RSI,%RSI

0x4a414b JNE	4a4ce8

(1182) 0x4a4151 MOV	%RBX,%RCX

(1182) 0x4a4154 SHR	$0x3c,%RCX

(1182) 0x4a4158 JNE	4a4cd8

(1182) 0x4a415e LEA	(,%RBX,8),%RSI

(1182) 0x4a4166 MOV	%RSI,%RDI

(1182) 0x4a4169 VMOVDQA	%XMM11,(%RSP)

(1182) 0x4a416e MOV	%RSI,0x10(%RSP)

(1182) 0x4a4173 CALL	404430 <_Znwm@plt>

(1182) 0x4a4178 MOV	%RAX,0x278(%R15)

(1182) 0x4a417f VPBROADCASTQ	%RBX,%XMM12

(1182) 0x4a4185 MOV	0x10(%RSP),%RDX

(1182) 0x4a418a MOV	%RAX,%RDI

(1182) 0x4a418d VMOVDQU	%XMM12,0x268(%R15)

(1182) 0x4a4196 XOR	%ESI,%ESI

(1182) 0x4a4198 CALL	404140 <memset@plt>

(1182) 0x4a419d VMOVDQA	(%RSP),%XMM11

(1182) 0x4a41a2 JMP	4a3686

0x4a41a7 NOPW	(%RAX,%RAX,1)

(1182) 0x4a41b0 TEST	%RSI,%RSI

(1182) 0x4a41b3 JNE	4a4d10

(1182) 0x4a41b9 MOV	%RBX,%R9

(1182) 0x4a41bc SHR	$0x3c,%R9

(1182) 0x4a41c0 JNE	4a4cd8

(1182) 0x4a41c6 LEA	(,%RBX,8),%R10

(1182) 0x4a41ce MOV	%R10,%RDI

(1182) 0x4a41d1 MOV	%R10,0x10(%RSP)

(1182) 0x4a41d6 CALL	404430 <_Znwm@plt>

(1182) 0x4a41db MOV	%RAX,0x238(%R15)

(1182) 0x4a41e2 VPBROADCASTQ	%RBX,%XMM13

(1182) 0x4a41e8 MOV	0x10(%RSP),%RDX

(1182) 0x4a41ed MOV	%RAX,%RDI

(1182) 0x4a41f0 VMOVDQU	%XMM13,0x228(%R15)

(1182) 0x4a41f9 XOR	%ESI,%ESI

(1182) 0x4a41fb CALL	404140 <memset@plt>

(1182) 0x4a4200 JMP	4a36c6

0x4a4205 NOPL	(%RAX)

(1182) 0x4a4208 TEST	%RSI,%RSI

(1182) 0x4a420b JNE	4a4d28

(1182) 0x4a4211 MOV	%R14,%RDX

(1182) 0x4a4214 SHR	$0x3c,%RDX

(1182) 0x4a4218 JNE	4a4cd0

(1182) 0x4a421e LEA	(,%R14,8),%RCX

(1182) 0x4a4226 MOV	%RCX,%RDI

(1182) 0x4a4229 MOV	%RCX,0x10(%RSP)

(1182) 0x4a422e CALL	404430 <_Znwm@plt>

(1182) 0x4a4233 MOV	%RAX,0x348(%R15)

(1182) 0x4a423a VMOVDQA	0x60(%RSP),%XMM14

(1182) 0x4a4240 MOV	0x10(%RSP),%RDX

(1182) 0x4a4245 MOV	%RAX,%RDI

(1182) 0x4a4248 VMOVDQU	%XMM14,0x338(%R15)

(1182) 0x4a4251 XOR	%ESI,%ESI

(1182) 0x4a4253 CALL	404140 <memset@plt>

(1182) 0x4a4258 JMP	4a36f6

0x4a425d NOPL	(%RAX)

(1182) 0x4a4260 TEST	%RSI,%RSI

(1182) 0x4a4263 JNE	4a4b90

(1182) 0x4a4269 MOV	%R12,%RDI

(1182) 0x4a426c SHR	$0x3c,%RDI

(1182) 0x4a4270 JNE	4a4cd0

(1182) 0x4a4276 LEA	(,%R12,8),%R9

(1182) 0x4a427e MOV	%R9,%RDI

(1182) 0x4a4281 MOV	%R9,0x10(%RSP)

(1182) 0x4a4286 CALL	404430 <_Znwm@plt>

(1182) 0x4a428b MOV	%RAX,0x320(%R15)

(1182) 0x4a4292 VPBROADCASTQ	%R12,%XMM15

(1182) 0x4a4298 MOV	0x10(%RSP),%RDX

(1182) 0x4a429d MOV	%RAX,%RDI

(1182) 0x4a42a0 VMOVDQU	%XMM15,0x310(%R15)

(1182) 0x4a42a9 XOR	%ESI,%ESI

(1182) 0x4a42ab CALL	404140 <memset@plt>

(1182) 0x4a42b0 JMP	4a3726

0x4a42b5 NOPL	(%RAX)

(1182) 0x4a42b8 TEST	%RSI,%RSI

(1182) 0x4a42bb JNE	4a4ba8

(1182) 0x4a42c1 MOV	%RBX,%RAX

(1182) 0x4a42c4 SHR	$0x3c,%RAX

(1182) 0x4a42c8 JNE	4a4cd8

(1182) 0x4a42ce SAL	$0x3,%RBX

(1182) 0x4a42d2 MOV	%RBX,%RDI

(1182) 0x4a42d5 CALL	404430 <_Znwm@plt>

(1182) 0x4a42da MOV	%RAX,0x2f8(%R15)

(1182) 0x4a42e1 VMOVDQA	0x20(%RSP),%XMM0

(1182) 0x4a42e7 MOV	%RAX,%RDI

(1182) 0x4a42ea VMOVDQU	%XMM0,0x2e8(%R15)

(1182) 0x4a42f3 MOV	%RBX,%RDX

(1182) 0x4a42f6 XOR	%ESI,%ESI

(1182) 0x4a42f8 CALL	404140 <memset@plt>

(1182) 0x4a42fd JMP	4a376c

0x4a4302 NOPW	(%RAX,%RAX,1)

(1182) 0x4a4308 TEST	%RSI,%RSI

(1182) 0x4a430b JNE	4a4bc0

(1182) 0x4a4311 MOV	%RCX,%R8

(1182) 0x4a4314 SHR	$0x3c,%R8

(1182) 0x4a4318 JNE	4a4cc8

(1182) 0x4a431e LEA	(,%RCX,8),%RSI

(1182) 0x4a4326 MOV	%RSI,%RDI

(1182) 0x4a4329 MOV	%RSI,0x60(%RSP)

(1182) 0x4a432e MOV	%RCX,0x50(%RSP)

(1182) 0x4a4333 CALL	404430 <_Znwm@plt>

(1182) 0x4a4338 MOV	0x50(%RSP),%R9

(1182) 0x4a433d MOV	%RAX,0x2b8(%R15)

(1182) 0x4a4344 VPBROADCASTQ	%R9,%XMM3

(1182) 0x4a434a MOV	0x60(%RSP),%RDX

(1182) 0x4a434f MOV	%RAX,%RDI

(1182) 0x4a4352 VMOVDQU	%XMM3,0x2a8(%R15)

(1182) 0x4a435b XOR	%ESI,%ESI

(1182) 0x4a435d CALL	404140 <memset@plt>

(1182) 0x4a4362 JMP	4a37b9

0x4a4367 NOPW	(%RAX,%RAX,1)

(1182) 0x4a4370 MOV	0x368(%R15),%RDI

(1182) 0x4a4377 MOV	%R14,%RDX

(1182) 0x4a437a SUB	%R10,%RDI

(1182) 0x4a437d SUB	%RAX,%RDX

(1182) 0x4a4380 SAR	$0x2,%RDI

(1182) 0x4a4384 CMP	%RDX,%RDI

(1182) 0x4a4387 JAE	4a4b58

(1182) 0x4a438d MOV	$0x1fffffffffffffff,%RCX

(1182) 0x4a4397 SUB	%RAX,%RCX

(1182) 0x4a439a CMP	%RDX,%RCX

(1182) 0x4a439d JB	4a4e36

(1182) 0x4a43a3 CMP	%RDX,%RAX

(1182) 0x4a43a6 MOV	%RDX,%R8

(1182) 0x4a43a9 CMOVAE	%RAX,%R8

(1182) 0x4a43ad MOV	%RBX,0x20(%RSP)

(1182) 0x4a43b2 ADD	%R8,%RAX

(1182) 0x4a43b5 SAL	$0x2,%RAX

(1182) 0x4a43b9 MOV	%RAX,%RDI

(1182) 0x4a43bc MOV	%R11,0x50(%RSP)

(1182) 0x4a43c1 MOV	%RDX,0x60(%RSP)

(1182) 0x4a43c6 MOV	%RAX,%RBX

(1182) 0x4a43c9 CALL	404430 <_Znwm@plt>

(1182) 0x4a43ce MOV	0x20(%RSP),%R9

(1182) 0x4a43d3 MOV	0x60(%RSP),%R11

(1182) 0x4a43d8 LEA	(%RAX,%R9,1),%RSI

(1182) 0x4a43dc DEC	%R11

(1182) 0x4a43df MOV	%RAX,%R10

(1182) 0x4a43e2 MOVL	$0,(%RSI)

(1182) 0x4a43e8 MOV	0x50(%RSP),%RAX

(1182) 0x4a43ed JE	4a4420

(1182) 0x4a43ef LEA	0x4(%RSI),%RDI

(1182) 0x4a43f3 LEA	(,%R11,4),%RDX

(1182) 0x4a43fb XOR	%ESI,%ESI

(1182) 0x4a43fd MOV	%R10,0x20(%RSP)

(1182) 0x4a4402 MOV	%R9,0x50(%RSP)

(1182) 0x4a4407 MOV	%RAX,0x60(%RSP)

(1182) 0x4a440c CALL	404140 <memset@plt>

(1182) 0x4a4411 MOV	0x60(%RSP),%RAX

(1182) 0x4a4416 MOV	0x50(%RSP),%R9

(1182) 0x4a441b MOV	0x20(%RSP),%R10

(1182) 0x4a4420 TEST	%R9,%R9

(1182) 0x4a4423 JNE	4a4d40

(1182) 0x4a4429 TEST	%RAX,%RAX

(1182) 0x4a442c JNE	4a4e27

(1182) 0x4a4432 LEA	(%R10,%R14,4),%R14

(1182) 0x4a4436 VMOVQ	%R10,%XMM5

(1182) 0x4a443b VPINSRQ	$0x1,%R14,%XMM5,%XMM1

(1182) 0x4a4441 ADD	%RBX,%R10

(1182) 0x4a4444 MOV	%R10,0x368(%R15)

(1182) 0x4a444b VMOVDQU	%XMM1,0x358(%R15)

(1182) 0x4a4454 JMP	4a37e6

0x4a4459 NOPL	(%RAX)

(1182) 0x4a4460 TEST	%RSI,%RSI

(1182) 0x4a4463 JNE	4a4be0

(1182) 0x4a4469 MOV	%RBX,%RDI

(1182) 0x4a446c SHR	$0x3c,%RDI

(1182) 0x4a4470 JNE	4a4cd8

(1182) 0x4a4476 LEA	(,%RBX,8),%R14

(1182) 0x4a447e MOV	%R14,%RDI

(1182) 0x4a4481 CALL	404430 <_Znwm@plt>

(1182) 0x4a4486 MOV	%RAX,0x100(%R15)

(1182) 0x4a448d VPBROADCASTQ	%RBX,%XMM8

(1182) 0x4a4493 MOV	%RAX,%RDI

(1182) 0x4a4496 VMOVDQU	%XMM8,0xf0(%R15)

(1182) 0x4a449f MOV	%R14,%RDX

(1182) 0x4a44a2 XOR	%ESI,%ESI

(1182) 0x4a44a4 CALL	404140 <memset@plt>

(1182) 0x4a44a9 JMP	4a3841

0x4a44ae XCHG	%AX,%AX

(1182) 0x4a44b0 TEST	%R8,%R8

(1182) 0x4a44b3 JNE	4a4bf8

(1182) 0x4a44b9 MOV	$0x555555555555555,%R8

(1182) 0x4a44c3 CMP	%RBX,%R8

(1182) 0x4a44c6 JB	4a4dd0

(1182) 0x4a44cc LEA	(%RBX,%RBX,2),%R14

(1182) 0x4a44d0 SAL	$0x3,%R14

(1182) 0x4a44d4 MOV	%R14,%RDI

(1182) 0x4a44d7 SHR	$0x3,%R14

(1182) 0x4a44db CALL	404430 <_Znwm@plt>

(1182) 0x4a44e0 LEA	-0x3(%R14),%RCX

(1182) 0x4a44e4 MOV	$0xaaaaaaaaaaaaaab,%R10

(1182) 0x4a44ee IMUL	%R10,%RCX

(1182) 0x4a44f2 MOV	%RAX,0x140(%R15)

(1182) 0x4a44f9 MOV	%RAX,%R11

(1182) 0x4a44fc MOV	$0x1fffffffffffffff,%RAX

(1182) 0x4a4506 VPBROADCASTQ	%RBX,%XMM13

(1182) 0x4a450c AND	%RAX,%RCX

(1182) 0x4a450f VMOVDQU	%XMM13,0x130(%R15)

(1182) 0x4a4518 LEA	0x1(%RCX),%RDX

(1182) 0x4a451c CMP	$0x2,%RCX

(1182) 0x4a4520 JBE	4a4df0

(1182) 0x4a4526 MOV	%RDX,%RSI

(1182) 0x4a4529 SHR	$0x2,%RSI

(1182) 0x4a452d LEA	(%RSI,%RSI,2),%RDI

(1182) 0x4a4531 SAL	$0x5,%RDI

(1182) 0x4a4535 LEA	(%RDI,%R11,1),%R8

(1182) 0x4a4539 SUB	$0x60,%RDI

(1182) 0x4a453d SHR	$0x5,%RDI

(1182) 0x4a4541 MOV	$0x2aaaaaaaaaaaaab,%R14

(1182) 0x4a454b IMUL	%R14,%RDI

(1182) 0x4a454f MOV	%R11,%R10

(1182) 0x4a4552 VXORPD	%XMM14,%XMM14,%XMM14

(1182) 0x4a4557 INC	%RDI

(1182) 0x4a455a AND	$0x7,%EDI

(1182) 0x4a455d JE	4a4616

(1182) 0x4a4563 CMP	$0x1,%RDI

(1182) 0x4a4567 JE	4a45f8

(1182) 0x4a456d CMP	$0x2,%RDI

(1182) 0x4a4571 JE	4a45e3

(1182) 0x4a4573 CMP	$0x3,%RDI

(1182) 0x4a4577 JE	4a45ce

(1182) 0x4a4579 CMP	$0x4,%RDI

(1182) 0x4a457d JE	4a45b9

(1182) 0x4a457f CMP	$0x5,%RDI

(1182) 0x4a4583 JE	4a45a4

(1182) 0x4a4585 CMP	$0x6,%RDI

(1182) 0x4a4589 JNE	4a4da0

(1182) 0x4a458f VMOVUPD	%YMM14,(%R10)

(1182) 0x4a4594 VMOVUPD	%YMM14,0x20(%R10)

(1182) 0x4a459a VMOVUPD	%YMM14,0x40(%R10)

(1182) 0x4a45a0 ADD	$0x60,%R10

(1182) 0x4a45a4 VMOVUPD	%YMM14,(%R10)

(1182) 0x4a45a9 VMOVUPD	%YMM14,0x20(%R10)

(1182) 0x4a45af VMOVUPD	%YMM14,0x40(%R10)

(1182) 0x4a45b5 ADD	$0x60,%R10

(1182) 0x4a45b9 VMOVUPD	%YMM14,(%R10)

(1182) 0x4a45be VMOVUPD	%YMM14,0x20(%R10)

(1182) 0x4a45c4 VMOVUPD	%YMM14,0x40(%R10)

(1182) 0x4a45ca ADD	$0x60,%R10

(1182) 0x4a45ce VMOVUPD	%YMM14,(%R10)

(1182) 0x4a45d3 VMOVUPD	%YMM14,0x20(%R10)

(1182) 0x4a45d9 VMOVUPD	%YMM14,0x40(%R10)

(1182) 0x4a45df ADD	$0x60,%R10

(1182) 0x4a45e3 VMOVUPD	%YMM14,(%R10)

(1182) 0x4a45e8 VMOVUPD	%YMM14,0x20(%R10)

(1182) 0x4a45ee VMOVUPD	%YMM14,0x40(%R10)

(1182) 0x4a45f4 ADD	$0x60,%R10

(1182) 0x4a45f8 VMOVUPD	%YMM14,(%R10)

(1182) 0x4a45fd VMOVUPD	%YMM14,0x20(%R10)

(1182) 0x4a4603 VMOVUPD	%YMM14,0x40(%R10)

(1182) 0x4a4609 ADD	$0x60,%R10

(1182) 0x4a460d CMP	%R8,%R10

(1182) 0x4a4610 JE	4a46f1

  (1185) 0x4a4616 VMOVUPD	%YMM14,(%R10)

  (1185) 0x4a461b VMOVUPD	%YMM14,0x20(%R10)

  (1185) 0x4a4621 VMOVUPD	%YMM14,0x40(%R10)

  (1185) 0x4a4627 VMOVUPD	%YMM14,0x60(%R10)

  (1185) 0x4a462d VMOVUPD	%YMM14,0x80(%R10)

  (1185) 0x4a4636 VMOVUPD	%YMM14,0xa0(%R10)

  (1185) 0x4a463f VMOVUPD	%YMM14,0xc0(%R10)

  (1185) 0x4a4648 VMOVUPD	%YMM14,0xe0(%R10)

  (1185) 0x4a4651 VMOVUPD	%YMM14,0x100(%R10)

  (1185) 0x4a465a VMOVUPD	%YMM14,0x120(%R10)

  (1185) 0x4a4663 VMOVUPD	%YMM14,0x140(%R10)

  (1185) 0x4a466c VMOVUPD	%YMM14,0x160(%R10)

  (1185) 0x4a4675 VMOVUPD	%YMM14,0x180(%R10)

  (1185) 0x4a467e VMOVUPD	%YMM14,0x1a0(%R10)

  (1185) 0x4a4687 VMOVUPD	%YMM14,0x1c0(%R10)

  (1185) 0x4a4690 VMOVUPD	%YMM14,0x1e0(%R10)

  (1185) 0x4a4699 VMOVUPD	%YMM14,0x200(%R10)

  (1185) 0x4a46a2 VMOVUPD	%YMM14,0x220(%R10)

  (1185) 0x4a46ab VMOVUPD	%YMM14,0x240(%R10)

  (1185) 0x4a46b4 VMOVUPD	%YMM14,0x260(%R10)

  (1185) 0x4a46bd VMOVUPD	%YMM14,0x280(%R10)

  (1185) 0x4a46c6 VMOVUPD	%YMM14,0x2a0(%R10)

  (1185) 0x4a46cf VMOVUPD	%YMM14,0x2c0(%R10)

  (1185) 0x4a46d8 VMOVUPD	%YMM14,0x2e0(%R10)

  (1185) 0x4a46e1 ADD	$0x300,%R10

  (1185) 0x4a46e8 CMP	%R8,%R10

  (1185) 0x4a46eb JNE	4a4616

(1182) 0x4a46f1 MOV	%RDX,%R9

(1182) 0x4a46f4 AND	$-0x4,%R9

(1182) 0x4a46f8 LEA	(%R9,%R9,2),%RAX

(1182) 0x4a46fc LEA	(%R11,%RAX,8),%RSI

(1182) 0x4a4700 TEST	$0x3,%DL

(1182) 0x4a4703 JE	4a3887

(1182) 0x4a4709 SUB	%R9,%RDX

(1182) 0x4a470c CMP	%R9,%RCX

(1182) 0x4a470f JE	4a4744

(1182) 0x4a4711 LEA	(%R9,%R9,2),%RCX

(1182) 0x4a4715 LEA	(%R11,%RCX,8),%R11

(1182) 0x4a4719 VXORPD	%XMM15,%XMM15,%XMM15

(1182) 0x4a471e VMOVUPD	%XMM15,(%R11)

(1182) 0x4a4723 VMOVUPD	%XMM15,0x10(%R11)

(1182) 0x4a4729 VMOVUPD	%XMM15,0x20(%R11)

(1182) 0x4a472f TEST	$0x1,%DL

(1182) 0x4a4732 JE	4a3887

(1182) 0x4a4738 AND	$-0x2,%RDX

(1182) 0x4a473c LEA	(%RDX,%RDX,2),%RDX

(1182) 0x4a4740 LEA	(%RSI,%RDX,8),%RSI

(1182) 0x4a4744 VXORPD	%XMM2,%XMM2,%XMM2

(1182) 0x4a4748 MOVQ	$0,0x10(%RSI)

(1182) 0x4a4750 VMOVUPD	%XMM2,(%RSI)

(1182) 0x4a4754 JMP	4a3887

0x4a4759 NOPL	(%RAX)

(1182) 0x4a4760 TEST	%RSI,%RSI

(1182) 0x4a4763 JNE	4a4c18

(1182) 0x4a4769 VZEROUPPER

(1182) 0x4a476c MOV	%RBX,%R8

(1182) 0x4a476f SHR	$0x3c,%R8

(1182) 0x4a4773 JNE	4a4cd8

(1182) 0x4a4779 LEA	(,%RBX,8),%R14

(1182) 0x4a4781 MOV	%R14,%RDI

(1182) 0x4a4784 CALL	404430 <_Znwm@plt>

(1182) 0x4a4789 MOV	%RAX,0x180(%R15)

(1182) 0x4a4790 VMOVDQA	0x60(%RSP),%XMM4

(1182) 0x4a4796 MOV	%RAX,%RDI

(1182) 0x4a4799 VMOVDQU	%XMM4,0x170(%R15)

(1182) 0x4a47a2 MOV	%R14,%RDX

(1182) 0x4a47a5 XOR	%ESI,%ESI

(1182) 0x4a47a7 CALL	404140 <memset@plt>

(1182) 0x4a47ac JMP	4a38cd

0x4a47b1 NOPL	(%RAX)

(1182) 0x4a47b8 TEST	%RSI,%RSI

(1182) 0x4a47bb JNE	4a4c50

(1182) 0x4a47c1 VZEROUPPER

(1182) 0x4a47c4 MOV	%R12,%RSI

(1182) 0x4a47c7 SHR	$0x3c,%RSI

(1182) 0x4a47cb JNE	4a4cd0

(1182) 0x4a47d1 LEA	(,%R12,8),%R14

(1182) 0x4a47d9 MOV	%R14,%RDI

(1182) 0x4a47dc CALL	404430 <_Znwm@plt>

(1182) 0x4a47e1 MOV	%RAX,0x420(%R15)

(1182) 0x4a47e8 VMOVDQA	0x30(%RSP),%XMM5

(1182) 0x4a47ee MOV	%RAX,%RDI

(1182) 0x4a47f1 VMOVDQU	%XMM5,0x410(%R15)

(1182) 0x4a47fa MOV	%R14,%RDX

(1182) 0x4a47fd XOR	%ESI,%ESI

(1182) 0x4a47ff CALL	404140 <memset@plt>

(1182) 0x4a4804 JMP	4a3967

0x4a4809 NOPL	(%RAX)

(1182) 0x4a4810 TEST	%RSI,%RSI

(1182) 0x4a4813 JNE	4a4c70

(1182) 0x4a4819 VZEROUPPER

(1182) 0x4a481c MOV	%RBX,%R8

(1182) 0x4a481f SHR	$0x3c,%R8

(1182) 0x4a4823 JNE	4a4cd8

(1182) 0x4a4829 SAL	$0x3,%RBX

(1182) 0x4a482d MOV	%RBX,%RDI

(1182) 0x4a4830 CALL	404430 <_Znwm@plt>

(1182) 0x4a4835 MOV	%RAX,0xc0(%R15)

(1182) 0x4a483c VMOVDQA	0x60(%RSP),%XMM6

(1182) 0x4a4842 MOV	%RAX,%RDI

(1182) 0x4a4845 VMOVDQU	%XMM6,0xb0(%R15)

(1182) 0x4a484e MOV	%RBX,%RDX

(1182) 0x4a4851 XOR	%ESI,%ESI

(1182) 0x4a4853 CALL	404140 <memset@plt>

(1182) 0x4a4858 JMP	4a39ca

0x4a485d NOPL	(%RAX)

(1182) 0x4a4860 TEST	%RAX,%RAX

(1182) 0x4a4863 JNE	4a4c90

(1182) 0x4a4869 VZEROUPPER

(1182) 0x4a486c MOV	$0x555555555555555,%R10

(1182) 0x4a4876 CMP	%R12,%R10

(1182) 0x4a4879 JB	4a4cd0

(1182) 0x4a487f LEA	(%R12,%R12,2),%R12

(1182) 0x4a4883 SAL	$0x3,%R12

(1182) 0x4a4887 MOV	%R12,%RDI

(1182) 0x4a488a SHR	$0x3,%R12

(1182) 0x4a488e CALL	404430 <_Znwm@plt>

(1182) 0x4a4893 LEA	-0x3(%R12),%R11

(1182) 0x4a4898 MOV	$0xaaaaaaaaaaaaaab,%RDX

(1182) 0x4a48a2 IMUL	%RDX,%R11

(1182) 0x4a48a6 VMOVDQA	0x30(%RSP),%XMM12

(1182) 0x4a48ac MOV	$0x1fffffffffffffff,%RSI

(1182) 0x4a48b6 AND	%RSI,%R11

(1182) 0x4a48b9 MOV	%RAX,0x1d0(%R15)

(1182) 0x4a48c0 MOV	%RAX,%RBX

(1182) 0x4a48c3 VMOVDQU	%XMM12,0x1c0(%R15)

(1182) 0x4a48cc LEA	0x1(%R11),%RDI

(1182) 0x4a48d0 CMP	$0x2,%R11

(1182) 0x4a48d4 JBE	4a4e10

(1182) 0x4a48da MOV	%RDI,%R9

(1182) 0x4a48dd SHR	$0x2,%R9

(1182) 0x4a48e1 LEA	(%R9,%R9,2),%R13

(1182) 0x4a48e5 SAL	$0x5,%R13

(1182) 0x4a48e9 LEA	(%R13,%RAX,1),%RCX

(1182) 0x4a48ee SUB	$0x60,%R13

(1182) 0x4a48f2 SHR	$0x5,%R13

(1182) 0x4a48f6 MOV	$0x2aaaaaaaaaaaaab,%R14

(1182) 0x4a4900 IMUL	%R14,%R13

(1182) 0x4a4904 VXORPD	%XMM13,%XMM13,%XMM13

(1182) 0x4a4909 INC	%R13

(1182) 0x4a490c AND	$0x7,%R13D

(1182) 0x4a4910 JE	4a49c5

(1182) 0x4a4916 CMP	$0x1,%R13

(1182) 0x4a491a JE	4a49aa

(1182) 0x4a4920 CMP	$0x2,%R13

(1182) 0x4a4924 JE	4a4998

(1182) 0x4a4926 CMP	$0x3,%R13

(1182) 0x4a492a JE	4a4986

(1182) 0x4a492c CMP	$0x4,%R13

(1182) 0x4a4930 JE	4a4974

(1182) 0x4a4932 CMP	$0x5,%R13

(1182) 0x4a4936 JE	4a4962

(1182) 0x4a4938 CMP	$0x6,%R13

(1182) 0x4a493c JE	4a4950

(1182) 0x4a493e VMOVUPD	%YMM13,(%RAX)

(1182) 0x4a4942 VMOVUPD	%YMM13,0x20(%RAX)

(1182) 0x4a4947 VMOVUPD	%YMM13,0x40(%RAX)

(1182) 0x4a494c LEA	0x60(%RAX),%RAX

(1182) 0x4a4950 VMOVUPD	%YMM13,(%RAX)

(1182) 0x4a4954 VMOVUPD	%YMM13,0x20(%RAX)

(1182) 0x4a4959 VMOVUPD	%YMM13,0x40(%RAX)

(1182) 0x4a495e ADD	$0x60,%RAX

(1182) 0x4a4962 VMOVUPD	%YMM13,(%RAX)

(1182) 0x4a4966 VMOVUPD	%YMM13,0x20(%RAX)

(1182) 0x4a496b VMOVUPD	%YMM13,0x40(%RAX)

(1182) 0x4a4970 ADD	$0x60,%RAX

(1182) 0x4a4974 VMOVUPD	%YMM13,(%RAX)

(1182) 0x4a4978 VMOVUPD	%YMM13,0x20(%RAX)

(1182) 0x4a497d VMOVUPD	%YMM13,0x40(%RAX)

(1182) 0x4a4982 ADD	$0x60,%RAX

(1182) 0x4a4986 VMOVUPD	%YMM13,(%RAX)

(1182) 0x4a498a VMOVUPD	%YMM13,0x20(%RAX)

(1182) 0x4a498f VMOVUPD	%YMM13,0x40(%RAX)

(1182) 0x4a4994 ADD	$0x60,%RAX

(1182) 0x4a4998 VMOVUPD	%YMM13,(%RAX)

(1182) 0x4a499c VMOVUPD	%YMM13,0x20(%RAX)

(1182) 0x4a49a1 VMOVUPD	%YMM13,0x40(%RAX)

(1182) 0x4a49a6 ADD	$0x60,%RAX

(1182) 0x4a49aa VMOVUPD	%YMM13,(%RAX)

(1182) 0x4a49ae VMOVUPD	%YMM13,0x20(%RAX)

(1182) 0x4a49b3 VMOVUPD	%YMM13,0x40(%RAX)

(1182) 0x4a49b8 ADD	$0x60,%RAX

(1182) 0x4a49bc CMP	%RAX,%RCX

(1182) 0x4a49bf JE	4a4a87

  (1183) 0x4a49c5 VMOVUPD	%YMM13,(%RAX)

  (1183) 0x4a49c9 VMOVUPD	%YMM13,0x20(%RAX)

  (1183) 0x4a49ce VMOVUPD	%YMM13,0x40(%RAX)

  (1183) 0x4a49d3 VMOVUPD	%YMM13,0x60(%RAX)

  (1183) 0x4a49d8 VMOVUPD	%YMM13,0x80(%RAX)

  (1183) 0x4a49e0 VMOVUPD	%YMM13,0xa0(%RAX)

  (1183) 0x4a49e8 VMOVUPD	%YMM13,0xc0(%RAX)

  (1183) 0x4a49f0 VMOVUPD	%YMM13,0xe0(%RAX)

  (1183) 0x4a49f8 VMOVUPD	%YMM13,0x100(%RAX)

  (1183) 0x4a4a00 VMOVUPD	%YMM13,0x120(%RAX)

  (1183) 0x4a4a08 VMOVUPD	%YMM13,0x140(%RAX)

  (1183) 0x4a4a10 VMOVUPD	%YMM13,0x160(%RAX)

  (1183) 0x4a4a18 VMOVUPD	%YMM13,0x180(%RAX)

  (1183) 0x4a4a20 VMOVUPD	%YMM13,0x1a0(%RAX)

  (1183) 0x4a4a28 VMOVUPD	%YMM13,0x1c0(%RAX)

  (1183) 0x4a4a30 VMOVUPD	%YMM13,0x1e0(%RAX)

  (1183) 0x4a4a38 VMOVUPD	%YMM13,0x200(%RAX)

  (1183) 0x4a4a40 VMOVUPD	%YMM13,0x220(%RAX)

  (1183) 0x4a4a48 VMOVUPD	%YMM13,0x240(%RAX)

  (1183) 0x4a4a50 VMOVUPD	%YMM13,0x260(%RAX)

  (1183) 0x4a4a58 VMOVUPD	%YMM13,0x280(%RAX)

  (1183) 0x4a4a60 VMOVUPD	%YMM13,0x2a0(%RAX)

  (1183) 0x4a4a68 VMOVUPD	%YMM13,0x2c0(%RAX)

  (1183) 0x4a4a70 VMOVUPD	%YMM13,0x2e0(%RAX)

  (1183) 0x4a4a78 ADD	$0x300,%RAX

  (1183) 0x4a4a7e CMP	%RAX,%RCX

  (1183) 0x4a4a81 JNE	4a49c5

(1182) 0x4a4a87 MOV	%RDI,%R8

(1182) 0x4a4a8a AND	$-0x4,%R8

(1182) 0x4a4a8e LEA	(%R8,%R8,2),%R10

(1182) 0x4a4a92 LEA	(%RBX,%R10,8),%RDX

(1182) 0x4a4a96 TEST	$0x3,%DIL

(1182) 0x4a4a9a JE	4a4dc0

(1182) 0x4a4aa0 VZEROUPPER

(1182) 0x4a4aa3 SUB	%R8,%RDI

(1182) 0x4a4aa6 CMP	%R11,%R8

(1182) 0x4a4aa9 JE	4a4ad8

(1182) 0x4a4aab LEA	(%R8,%R8,2),%R12

(1182) 0x4a4aaf LEA	(%RBX,%R12,8),%RBX

(1182) 0x4a4ab3 VXORPD	%XMM14,%XMM14,%XMM14

(1182) 0x4a4ab8 VMOVUPD	%XMM14,(%RBX)

(1182) 0x4a4abc VMOVUPD	%XMM14,0x10(%RBX)

(1182) 0x4a4ac1 VMOVUPD	%XMM14,0x20(%RBX)

(1182) 0x4a4ac6 TEST	$0x1,%DIL

(1182) 0x4a4aca JE	4a4ae9

(1182) 0x4a4acc AND	$-0x2,%RDI

(1182) 0x4a4ad0 LEA	(%RDI,%RDI,2),%R11

(1182) 0x4a4ad4 LEA	(%RDX,%R11,8),%RDX

(1182) 0x4a4ad8 MOVQ	$0,0x10(%RDX)

(1182) 0x4a4ae0 VXORPD	%XMM15,%XMM15,%XMM15

(1182) 0x4a4ae5 VMOVUPD	%XMM15,(%RDX)

(1182) 0x4a4ae9 MOVSXD	0x480(%R15),%R12

(1182) 0x4a4af0 JMP	4a3c8b

0x4a4af5 NOPL	(%RAX)

(1182) 0x4a4af8 TEST	%RSI,%RSI

(1182) 0x4a4afb JNE	4a4cb0

(1182) 0x4a4b01 MOV	%R12,%RDI

(1182) 0x4a4b04 SHR	$0x3c,%RDI

(1182) 0x4a4b08 JNE	4a4cd0

0x4a4b0e LEA	(,%R12,8),%R13

0x4a4b16 MOV	%R13,%RDI

0x4a4b19 CALL	404430 <_Znwm@plt>

0x4a4b1e MOV	%RAX,0x1f8(%R15)

0x4a4b25 VPBROADCASTQ	%R12,%XMM2

0x4a4b2b VMOVDQU	%XMM2,0x1e8(%R15)

0x4a4b34 ADD	$0x88,%RSP

0x4a4b3b POP	%RBX

0x4a4b3c POP	%R12

0x4a4b3e MOV	%R13,%RDX

0x4a4b41 POP	%R13

0x4a4b43 POP	%R14

0x4a4b45 POP	%R15

0x4a4b47 MOV	%RAX,%RDI

0x4a4b4a XOR	%ESI,%ESI

0x4a4b4c POP	%RBP

0x4a4b4d JMP	404140

0x4a4b52 NOPW	(%RAX,%RAX,1)

(1182) 0x4a4b58 MOVL	$0,(%R10)

(1182) 0x4a4b5f LEA	0x4(%R10),%RDI

(1182) 0x4a4b63 DEC	%RDX

(1182) 0x4a4b66 JE	4a4b80

(1182) 0x4a4b68 LEA	(%RDI,%RDX,4),%R14

(1182) 0x4a4b6c MOV	%R14,%RDX

(1182) 0x4a4b6f SUB	%R10,%RDX

(1182) 0x4a4b72 SUB	$0x4,%RDX

(1182) 0x4a4b76 XOR	%ESI,%ESI

(1182) 0x4a4b78 CALL	404140 <memset@plt>

(1182) 0x4a4b7d MOV	%R14,%RDI

(1182) 0x4a4b80 MOV	%RDI,0x360(%R15)

(1182) 0x4a4b87 JMP	4a37e6

0x4a4b8c NOPL	(%RAX)

(1182) 0x4a4b90 MOV	0x320(%R15),%RDI

(1182) 0x4a4b97 SAL	$0x3,%RSI

(1182) 0x4a4b9b CALL	404070 <_ZdlPvm@plt>

(1182) 0x4a4ba0 JMP	4a4269

0x4a4ba5 NOPL	(%RAX)

(1182) 0x4a4ba8 MOV	0x2f8(%R15),%RDI

(1182) 0x4a4baf SAL	$0x3,%RSI

(1182) 0x4a4bb3 CALL	404070 <_ZdlPvm@plt>

(1182) 0x4a4bb8 JMP	4a42c1

0x4a4bbd NOPL	(%RAX)

(1182) 0x4a4bc0 MOV	0x2b8(%R15),%RDI

(1182) 0x4a4bc7 SAL	$0x3,%RSI

(1182) 0x4a4bcb MOV	%RCX,0x60(%RSP)

(1182) 0x4a4bd0 CALL	404070 <_ZdlPvm@plt>

(1182) 0x4a4bd5 MOV	0x60(%RSP),%RCX

(1182) 0x4a4bda JMP	4a4311

0x4a4bdf NOP

(1182) 0x4a4be0 MOV	0x100(%R15),%RDI

(1182) 0x4a4be7 SAL	$0x3,%RSI

(1182) 0x4a4beb CALL	404070 <_ZdlPvm@plt>

(1182) 0x4a4bf0 JMP	4a4469

0x4a4bf5 NOPL	(%RAX)

(1182) 0x4a4bf8 LEA	(%R8,%R8,2),%RSI

(1182) 0x4a4bfc MOV	0x140(%R15),%RDI

(1182) 0x4a4c03 SAL	$0x3,%RSI

(1182) 0x4a4c07 CALL	404070 <_ZdlPvm@plt>

(1182) 0x4a4c0c JMP	4a44b9

0x4a4c11 NOPL	(%RAX)

(1182) 0x4a4c18 MOV	0x180(%R15),%RDI

(1182) 0x4a4c1f SAL	$0x3,%RSI

(1182) 0x4a4c23 VZEROUPPER

(1182) 0x4a4c26 CALL	404070 <_ZdlPvm@plt>

(1182) 0x4a4c2b JMP	4a476c

(1182) 0x4a4c30 MOV	0x1a8(%R15),%RDI

(1182) 0x4a4c37 SAL	$0x3,%RSI

(1182) 0x4a4c3b VZEROUPPER

(1182) 0x4a4c3e CALL	404070 <_ZdlPvm@plt>

(1182) 0x4a4c43 JMP	4a40fc

0x4a4c48 NOPL	(%RAX,%RAX,1)

(1182) 0x4a4c50 MOV	0x420(%R15),%RDI

(1182) 0x4a4c57 SAL	$0x3,%RSI

(1182) 0x4a4c5b VZEROUPPER

(1182) 0x4a4c5e CALL	404070 <_ZdlPvm@plt>

(1182) 0x4a4c63 JMP	4a47c4

0x4a4c68 NOPL	(%RAX,%RAX,1)

(1182) 0x4a4c70 MOV	0xc0(%R15),%RDI

(1182) 0x4a4c77 SAL	$0x3,%RSI

(1182) 0x4a4c7b VZEROUPPER

(1182) 0x4a4c7e CALL	404070 <_ZdlPvm@plt>

(1182) 0x4a4c83 JMP	4a481c

0x4a4c88 NOPL	(%RAX,%RAX,1)

(1182) 0x4a4c90 LEA	(%RAX,%RAX,2),%RSI

(1182) 0x4a4c94 MOV	0x1d0(%R15),%RDI

(1182) 0x4a4c9b SAL	$0x3,%RSI

(1182) 0x4a4c9f VZEROUPPER

(1182) 0x4a4ca2 CALL	404070 <_ZdlPvm@plt>

(1182) 0x4a4ca7 JMP	4a486c

0x4a4cac NOPL	(%RAX)

(1182) 0x4a4cb0 MOV	0x1f8(%R15),%RDI

(1182) 0x4a4cb7 SAL	$0x3,%RSI

(1182) 0x4a4cbb CALL	404070 <_ZdlPvm@plt>

(1182) 0x4a4cc0 JMP	4a4b01

0x4a4cc5 NOPL	(%RAX)

(1182) 0x4a4cc8 SHR	$0x3d,%RCX

(1182) 0x4a4ccc JE	4a4cde

(1182) 0x4a4cce XCHG	%AX,%AX

  (1181) 0x4a4cd0 CALL	404500 <_ZSt28__throw_bad_array_new_lengthv@plt>

  (1181) 0x4a4cd5 NOPL	(%RAX)

  (1181) 0x4a4cd8 SHR	$0x3d,%RBX

  (1181) 0x4a4cdc JNE	4a4cd0

(1182) 0x4a4cde CALL	404420 <_ZSt17__throw_bad_allocv@plt>

(1182) 0x4a4ce3 NOPL	(%RAX,%RAX,1)

(1182) 0x4a4ce8 MOV	0x278(%RDI),%RDI

(1182) 0x4a4cef SAL	$0x3,%RSI

(1182) 0x4a4cf3 VMOVDQA	%XMM11,0x10(%RSP)

(1182) 0x4a4cf9 CALL	404070 <_ZdlPvm@plt>

(1182) 0x4a4cfe VMOVDQA	0x10(%RSP),%XMM11

(1182) 0x4a4d04 JMP	4a4151

0x4a4d09 NOPL	(%RAX)

(1182) 0x4a4d10 MOV	0x238(%R15),%RDI

(1182) 0x4a4d17 SAL	$0x3,%RSI

(1182) 0x4a4d1b CALL	404070 <_ZdlPvm@plt>

(1182) 0x4a4d20 JMP	4a41b9

0x4a4d25 NOPL	(%RAX)

(1182) 0x4a4d28 MOV	0x348(%R15),%RDI

(1182) 0x4a4d2f SAL	$0x3,%RSI

(1182) 0x4a4d33 CALL	404070 <_ZdlPvm@plt>

(1182) 0x4a4d38 JMP	4a4211

0x4a4d3d NOPL	(%RAX)

(1182) 0x4a4d40 MOV	%RAX,%RSI

(1182) 0x4a4d43 MOV	%R10,%RDI

(1182) 0x4a4d46 MOV	%R9,%RDX

(1182) 0x4a4d49 MOV	%RAX,0x60(%RSP)

(1182) 0x4a4d4e CALL	404410 <memcpy@plt>

(1182) 0x4a4d53 MOV	%RAX,%R10

(1182) 0x4a4d56 MOV	0x368(%R15),%RSI

(1182) 0x4a4d5d MOV	0x60(%RSP),%RAX

(1182) 0x4a4d62 SUB	%RAX,%RSI

(1182) 0x4a4d65 MOV	%RAX,%RDI

(1182) 0x4a4d68 MOV	%R10,0x60(%RSP)

(1182) 0x4a4d6d CALL	404070 <_ZdlPvm@plt>

(1182) 0x4a4d72 MOV	0x60(%RSP),%R10

(1182) 0x4a4d77 JMP	4a4432

0x4a4d7c NOPL	(%RAX)

(1182) 0x4a4d80 VMOVUPD	%YMM10,(%RDI)

(1182) 0x4a4d84 VMOVUPD	%YMM10,0x20(%RDI)

(1182) 0x4a4d89 VMOVUPD	%YMM10,0x40(%RDI)

(1182) 0x4a4d8e LEA	0x60(%RDI),%RAX

(1182) 0x4a4d92 JMP	4a3f1a

0x4a4d97 NOPW	(%RAX,%RAX,1)

(1182) 0x4a4da0 VMOVUPD	%YMM14,(%R11)

(1182) 0x4a4da5 VMOVUPD	%YMM14,0x20(%R11)

(1182) 0x4a4dab VMOVUPD	%YMM14,0x40(%R11)

(1182) 0x4a4db1 LEA	0x60(%R11),%R10

(1182) 0x4a4db5 JMP	4a458f

0x4a4dba NOPW	(%RAX,%RAX,1)

(1182) 0x4a4dc0 VZEROUPPER

(1182) 0x4a4dc3 JMP	4a4ae9

0x4a4dc8 NOPL	(%RAX,%RAX,1)

(1182) 0x4a4dd0 MOV	$0xaaaaaaaaaaaaaaa,%R15

(1182) 0x4a4dda CMP	%RBX,%R15

(1182) 0x4a4ddd JB	4a4cd0

(1182) 0x4a4de3 JMP	4a4cde

0x4a4de8 NOPL	(%RAX,%RAX,1)

(1182) 0x4a4df0 MOV	%R11,%RSI

(1182) 0x4a4df3 XOR	%R9D,%R9D

(1182) 0x4a4df6 JMP	4a4709

0x4a4dfb NOPL	(%RAX,%RAX,1)

(1182) 0x4a4e00 XOR	%R11D,%R11D

(1182) 0x4a4e03 JMP	4a406a

0x4a4e08 NOPL	(%RAX,%RAX,1)

(1182) 0x4a4e10 MOV	%RAX,%RDX

(1182) 0x4a4e13 XOR	%R8D,%R8D

(1182) 0x4a4e16 JMP	4a4aa3

0x4a4e1b NOPL	(%RAX,%RAX,1)

(1182) 0x4a4e20 XOR	%EBX,%EBX

(1182) 0x4a4e22 JMP	4a3c37

(1182) 0x4a4e27 MOV	0x368(%R15),%RSI

(1182) 0x4a4e2e SUB	%RAX,%RSI

(1182) 0x4a4e31 JMP	4a4d65

0x4a4e36 MOV	$0x5b5f7b,%EDI

0x4a4e3b CALL	404240 <_ZSt20__throw_length_errorPKc@plt>

0x4a4e40 MOV	$0x10,%EDI

0x4a4e45 VZEROUPPER

0x4a4e48 CALL	4044e0 <__cxa_allocate_exception@plt>

0x4a4e4d MOV	%RAX,%RDI

0x4a4e50 MOV	$0x5b60d0,%ESI

0x4a4e55 MOV	%RAX,%RBX

0x4a4e58 CALL	404110 <_ZNSt13runtime_errorC1EPKc@plt>

(1180) 0x4a4e5d MOV	$0x404710,%EDX

(1180) 0x4a4e62 MOV	$0x5d6b58,%ESI

(1180) 0x4a4e67 MOV	%RBX,%RDI

(1180) 0x4a4e6a CALL	404220 <__cxa_throw@plt>

(1180) 0x4a4e6f MOV	$0x10,%EDI

(1180) 0x4a4e74 CALL	4044e0 <__cxa_allocate_exception@plt>

(1180) 0x4a4e79 MOV	%RAX,%RDI

(1180) 0x4a4e7c MOV	$0x5b60d0,%ESI

(1180) 0x4a4e81 MOV	%RAX,%RBX

(1180) 0x4a4e84 CALL	404110 <_ZNSt13runtime_errorC1EPKc@plt>

(1180) 0x4a4e89 JMP	4a4e5d

(1179) 0x4a4e8b MOV	%RAX,%R14

(1179) 0x4a4e8e JMP	4a4f0b

0x4a4e90 JMP	4a4e8b

0x4a4e92 MOV	$0x10,%EDI

0x4a4e97 CALL	4044e0 <__cxa_allocate_exception@plt>

0x4a4e9c MOV	%RAX,%RDI

0x4a4e9f MOV	$0x5b60d0,%ESI

0x4a4ea4 MOV	%RAX,%RBX

0x4a4ea7 CALL	404110 <_ZNSt13runtime_errorC1EPKc@plt>

0x4a4eac JMP	4a4e5d

0x4a4eae MOV	$0x10,%EDI

0x4a4eb3 CALL	4044e0 <__cxa_allocate_exception@plt>

0x4a4eb8 MOV	%RAX,%RDI

0x4a4ebb MOV	$0x5b60d0,%ESI

0x4a4ec0 MOV	%RAX,%RBX

0x4a4ec3 CALL	404110 <_ZNSt13runtime_errorC1EPKc@plt>

0x4a4ec8 JMP	4a4e5d

0x4a4eca MOV	$0x10,%EDI

0x4a4ecf VZEROUPPER

0x4a4ed2 CALL	4044e0 <__cxa_allocate_exception@plt>

0x4a4ed7 MOV	%RAX,%RDI

0x4a4eda MOV	$0x5b60d0,%ESI

0x4a4edf MOV	%RAX,%RBX

0x4a4ee2 CALL	404110 <_ZNSt13runtime_errorC1EPKc@plt>

0x4a4ee7 JMP	4a4e5d

0x4a4eec MOV	$0x10,%EDI

0x4a4ef1 CALL	4044e0 <__cxa_allocate_exception@plt>

0x4a4ef6 MOV	%RAX,%RDI

0x4a4ef9 MOV	$0x5b60d0,%ESI

0x4a4efe MOV	%RAX,%RBX

0x4a4f01 CALL	404110 <_ZNSt13runtime_errorC1EPKc@plt>

0x4a4f06 JMP	4a4e5d

(1179) 0x4a4f0b MOV	%RBX,%RDI

(1179) 0x4a4f0e VZEROUPPER

(1179) 0x4a4f11 CALL	404750 <__cxa_free_exception@plt>

(1179) 0x4a4f16 MOV	%R14,%RDI

(1179) 0x4a4f19 CALL	404260 <_Unwind_Resume@plt>

(1179) 0x4a4f1e JMP	4a4e8b

0x4a4f23 JMP	4a4e8b

0x4a4f28 JMP	4a4e8b

0x4a4f2d JMP	4a4e8b

0x4a4f32 MOV	$0x10,%EDI

0x4a4f37 CALL	4044e0 <__cxa_allocate_exception@plt>

0x4a4f3c MOV	%RAX,%RDI

0x4a4f3f MOV	$0x5b60d0,%ESI

0x4a4f44 MOV	%RAX,%RBX

0x4a4f47 CALL	404110 <_ZNSt13runtime_errorC1EPKc@plt>

0x4a4f4c JMP	4a4e5d

0x4a4f51 MOV	$0x10,%EDI

0x4a4f56 CALL	4044e0 <__cxa_allocate_exception@plt>

0x4a4f5b MOV	%RAX,%RDI

0x4a4f5e MOV	$0x5b60d0,%ESI

0x4a4f63 MOV	%RAX,%RBX

0x4a4f66 CALL	404110 <_ZNSt13runtime_errorC1EPKc@plt>

0x4a4f6b JMP	4a4e5d

0x4a4f70 JMP	4a4e8b

0x4a4f75 JMP	4a4e8b

0x4a4f7a MOV	$0x10,%EDI

0x4a4f7f CALL	4044e0 <__cxa_allocate_exception@plt>

0x4a4f84 MOV	%RAX,%RDI

0x4a4f87 MOV	$0x5b60d0,%ESI

0x4a4f8c MOV	%RAX,%RBX

0x4a4f8f CALL	404110 <_ZNSt13runtime_errorC1EPKc@plt>

0x4a4f94 JMP	4a4e5d

0x4a4f99 MOV	$0x10,%EDI

0x4a4f9e CALL	4044e0 <__cxa_allocate_exception@plt>

0x4a4fa3 MOV	%RAX,%RDI

0x4a4fa6 MOV	$0x5b60d0,%ESI

0x4a4fab MOV	%RAX,%RBX

0x4a4fae CALL	404110 <_ZNSt13runtime_errorC1EPKc@plt>

0x4a4fb3 JMP	4a4e5d

0x4a4fb8 JMP	4a4e8b

0x4a4fbd JMP	4a4e8b

0x4a4fc2 MOV	$0x10,%EDI

0x4a4fc7 VZEROUPPER

0x4a4fca CALL	4044e0 <__cxa_allocate_exception@plt>

0x4a4fcf MOV	%RAX,%RDI

0x4a4fd2 MOV	$0x5b60d0,%ESI

0x4a4fd7 MOV	%RAX,%RBX

0x4a4fda CALL	404110 <_ZNSt13runtime_errorC1EPKc@plt>

0x4a4fdf JMP	4a4e5d

0x4a4fe4 MOV	$0x10,%EDI

0x4a4fe9 VZEROUPPER

0x4a4fec CALL	4044e0 <__cxa_allocate_exception@plt>

0x4a4ff1 MOV	%RAX,%RDI

0x4a4ff4 MOV	$0x5b60d0,%ESI

0x4a4ff9 MOV	%RAX,%RBX

0x4a4ffc CALL	404110 <_ZNSt13runtime_errorC1EPKc@plt>

0x4a5001 JMP	4a4e5d

0x4a5006 JMP	4a4e8b

0x4a500b JMP	4a4e8b

0x4a5010 MOV	$0x10,%EDI

0x4a5015 VZEROUPPER

0x4a5018 CALL	4044e0 <__cxa_allocate_exception@plt>

0x4a501d MOV	%RAX,%RDI

0x4a5020 MOV	$0x5b60d0,%ESI

0x4a5025 MOV	%RAX,%RBX

0x4a5028 CALL	404110 <_ZNSt13runtime_errorC1EPKc@plt>

0x4a502d JMP	4a4e5d

0x4a5032 MOV	$0x10,%EDI

0x4a5037 CALL	4044e0 <__cxa_allocate_exception@plt>

0x4a503c MOV	%RAX,%RDI

0x4a503f MOV	$0x5b60d0,%ESI

0x4a5044 MOV	%RAX,%RBX

0x4a5047 CALL	404110 <_ZNSt13runtime_errorC1EPKc@plt>

0x4a504c JMP	4a4e5d

0x4a5051 JMP	4a4e8b

0x4a5056 JMP	4a4e8b

0x4a505b NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►53.83+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	qmcplusplus::build_WaveFunctio[...]	unique_ptr.h:397	exec
○	main._omp_fn.0	NonLocalPP.hpp:88	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►43.70+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	qmcplusplus::build_WaveFunctio[...]	unique_ptr.h:397	exec
○	main._omp_fn.0	NonLocalPP.hpp:88	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►1.36+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	qmcplusplus::build_WaveFunctio[...]	unique_ptr.h:397	exec
○	main._omp_fn.0	NonLocalPP.hpp:88	exec
○	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
►1.12+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	qmcplusplus::build_WaveFunctio[...]	unique_ptr.h:397	exec
○	main._omp_fn.0	NonLocalPP.hpp:88	exec
○	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	DiracDeterminantRef.cpp:61-79
Module	exec

The function is defined in:

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/alloc_traits.h:513
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_construct.h:119
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h:62
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_uninitialized.h:667,1117,1129
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:61-67,73-79
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:993,1015-1018,1908-1911,1945-1949
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:101-103
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/new_allocator.h:134-140,151,172
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h:262,939-940,951-952,1146-1151
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/vector.tcc:812-820,851,863,903-910
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:181-188,195-197,296-301

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 48.33 to 7.83 cycles (6.17x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 48.33 to 3.71 cycles (13.02x speedup).

Details

31% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
57% of SSE/AVX stores are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
22% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__cxa_allocate_exception@plt: 13 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
memset@plt: 2 occurrences►
- /cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h:952
- /cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h:952
operator new(unsigned long): 1 occurrences►
- /cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/new_allocator.h:151
std::__throw_length_error(char const*): 1 occurrences►
- /cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:1909
std::runtime_error::runtime_error(char const*): 13 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPINSRD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h:62
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:67
VZEROUPPER: 5 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 172 bytes.

General properties

nb instructions	253
nb uops	290
loop length	1148
used x86 registers	12
used mmx registers	0
used xmm registers	12
used ymm registers	0
used zmm registers	0
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	48.33 cycles
front end	48.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.20	13.30	6.33	6.33	25.00	13.10	13.20	25.00	25.00	25.00	13.20	6.33
cycles	13.20	13.30	6.33	6.33	25.00	13.10	13.20	25.00	25.00	25.00	13.20	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	48.33
Dispatch	25.00
Overall L1	48.33

Vectorization ratios

all	31%
load	50%
store	57%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Vector efficiency ratios

all	14%
load	15%
store	19%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 48.33 cycles. At this rate:

0% of peak load performance is reached (1.08 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.56 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 48.33 to 25.00 cycles (1.93x speedup).

ASM code

In the binary file, the address of the function is: 4a35b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
VMOVD %ESI,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x88,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
TEST %EDX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
CMOVLE %ESI,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
VMOVD 0x488(%RDI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
MOVSXD %EDX,%R12	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
VPINSRD $0x1,%R12D,%XMM3,%XMM7	2	0	0.50	0	0	0	1.50	0	0	0	0	0	0	1-4	1	scal (6.3%)
VPMOVSXDQ %XMM7,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (12.5%)
VMOVQ %XMM11,%R14	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOV %R12,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
IMUL %R14,%RBX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVD %R12D,%XMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
MOV %ESI,0x44(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VPINSRD $0x1,%R12D,%XMM2,%XMM0	2	0	0.50	0	0	0	1.50	0	0	0	0	0	0	1-4	1	scal (6.3%)
VPUNPCKLDQ %XMM3,%XMM5,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
MOV 0x268(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x270(%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VPMOVSXDQ %XMM0,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (12.5%)
VPMOVSXDQ %XMM1,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (12.5%)
VPBROADCASTQ %R12,%XMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPUNPCKLQDQ %XMM11,%XMM11,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %RBX,%XMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RBX,0x258(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVDQA %XMM4,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVQ %XMM4,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVDQA %XMM6,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVDQA %XMM8,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVDQA %XMM9,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVDQU %XMM11,0x248(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVDQA %XMM10,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
CMP %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 4a4f7a <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x19ca>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R12,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RBX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 4a4148 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xb98>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %RBX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 4a3cf0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x740>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,0x268(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %R12,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 4a3cce <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x71e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x1f8(%R15),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %R9,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%RSI,%R9,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 4a3cce <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x71e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 404140 <memset@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %R12,0x1e8(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $0x88,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x278(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%RAX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JE 4a367f <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xcf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVDQA %XMM11,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
CALL 404140 <memset@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVDQA 0x10(%RSP),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
JMP 4a367f <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xcf>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %RSI,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 4a4ce8 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x1738>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%R12,8),%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404430 <_Znwm@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,0x1f8(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %R12,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVDQU %XMM2,0x1e8(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
ADD $0x88,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
MOV %R13,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 404140 <memset@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x5b5f7b,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 404240 <_ZSt20__throw_length_errorPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e8b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18db>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e5d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e5d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e5d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e5d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 4a4e8b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18db>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 4a4e8b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18db>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 4a4e8b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18db>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e5d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e5d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 4a4e8b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18db>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 4a4e8b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18db>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e5d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e5d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 4a4e8b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18db>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 4a4e8b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18db>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e5d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e5d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 4a4e8b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18db>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 4a4e8b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18db>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e5d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e5d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 4a4e8b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18db>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 4a4e8b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18db>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	DiracDeterminantRef.cpp:61-79
Module	exec

The function is defined in:

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/alloc_traits.h:513
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_construct.h:119
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h:62
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_uninitialized.h:667,1117,1129
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:61-67,73-79
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:993,1015-1018,1908-1911,1945-1949
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:101-103
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/new_allocator.h:134-140,151,172
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h:262,939-940,951-952,1146-1151
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/vector.tcc:812-820,851,863,903-910
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:181-188,195-197,296-301

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 48.33 to 7.83 cycles (6.17x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

31% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
57% of SSE/AVX stores are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
22% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__cxa_allocate_exception@plt: 13 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
memset@plt: 2 occurrences►
- /cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h:952
- /cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h:952
operator new(unsigned long): 1 occurrences►
- /cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/new_allocator.h:151
std::__throw_length_error(char const*): 1 occurrences►
- /cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:1909
std::runtime_error::runtime_error(char const*): 13 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPINSRD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h:62
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:67
VZEROUPPER: 5 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 172 bytes.

General properties

nb instructions	253
nb uops	290
loop length	1148
used x86 registers	12
used mmx registers	0
used xmm registers	12
used ymm registers	0
used zmm registers	0
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	48.33 cycles
front end	48.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.20	13.30	6.33	6.33	25.00	13.10	13.20	25.00	25.00	25.00	13.20	6.33
cycles	13.20	13.30	6.33	6.33	25.00	13.10	13.20	25.00	25.00	25.00	13.20	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	48.33
Dispatch	25.00
Overall L1	48.33

Vectorization ratios

all	31%
load	50%
store	57%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Vector efficiency ratios

all	14%
load	15%
store	19%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 48.33 cycles. At this rate:

0% of peak load performance is reached (1.08 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.56 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4a35b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
VMOVD %ESI,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x88,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
TEST %EDX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
CMOVLE %ESI,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
VMOVD 0x488(%RDI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
MOVSXD %EDX,%R12	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
VPINSRD $0x1,%R12D,%XMM3,%XMM7	2	0	0.50	0	0	0	1.50	0	0	0	0	0	0	1-4	1	scal (6.3%)
VPMOVSXDQ %XMM7,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (12.5%)
VMOVQ %XMM11,%R14	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOV %R12,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
IMUL %R14,%RBX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVD %R12D,%XMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
MOV %ESI,0x44(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VPINSRD $0x1,%R12D,%XMM2,%XMM0	2	0	0.50	0	0	0	1.50	0	0	0	0	0	0	1-4	1	scal (6.3%)
VPUNPCKLDQ %XMM3,%XMM5,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
MOV 0x268(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x270(%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VPMOVSXDQ %XMM0,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (12.5%)
VPMOVSXDQ %XMM1,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (12.5%)
VPBROADCASTQ %R12,%XMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPUNPCKLQDQ %XMM11,%XMM11,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %RBX,%XMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RBX,0x258(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVDQA %XMM4,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVQ %XMM4,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVDQA %XMM6,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVDQA %XMM8,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVDQA %XMM9,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVDQU %XMM11,0x248(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVDQA %XMM10,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
CMP %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 4a4f7a <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x19ca>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R12,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RBX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 4a4148 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xb98>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %RBX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 4a3cf0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x740>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,0x268(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %R12,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 4a3cce <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x71e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x1f8(%R15),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %R9,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%RSI,%R9,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 4a3cce <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x71e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 404140 <memset@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %R12,0x1e8(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $0x88,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x278(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%RAX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JE 4a367f <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xcf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVDQA %XMM11,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
CALL 404140 <memset@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVDQA 0x10(%RSP),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
JMP 4a367f <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xcf>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %RSI,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 4a4ce8 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x1738>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%R12,8),%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404430 <_Znwm@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,0x1f8(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %R12,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVDQU %XMM2,0x1e8(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
ADD $0x88,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
MOV %R13,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 404140 <memset@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x5b5f7b,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 404240 <_ZSt20__throw_length_errorPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e8b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18db>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e5d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e5d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e5d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e5d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 4a4e8b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18db>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 4a4e8b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18db>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 4a4e8b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18db>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e5d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e5d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 4a4e8b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18db>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 4a4e8b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18db>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e5d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e5d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 4a4e8b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18db>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 4a4e8b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18db>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e5d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e5d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 4a4e8b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18db>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 4a4e8b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18db>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e5d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4044e0 <__cxa_allocate_exception@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x5b60d0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 4a4e5d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 4a4e8b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18db>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 4a4e8b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x18db>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::DiracDeterminantRef >::resize(int, int)–	0.03	0.03
▼Loop 1182 - stl_algobase.h:262-1151 - exec–	0.00	0.00
○Loop 1185 - stl_algobase.h:939-940 - exec	0.03	0.02
○Loop 1184 - stl_algobase.h:939-940 - exec	0.00	0.00
○Loop 1186 - stl_algobase.h:939-940 - exec	0.00	0.00
○Loop 1181 - new_allocator.h:138-139 - exec	0.00	0.00
○Loop 1183 - stl_algobase.h:939-940 - exec	0.00	0.00
○Loop 1180 - OhmmsVector.h:186-186 - exec	0.00	0.00
○Loop 1179 - OhmmsVector.h:186-186 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code