OV - exec - Function miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector<double, std::allocator<double> >&)

	Function: miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int ...	Module: exec	Source: einspline_spo_ref.hpp:172-189 [...]	Coverage (incl. loops): 19.28% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h: 150 - 152

--------------------------------------------------------------------------------

150:     return TinyVector<Type_t, 3>(lhs[0] * rhs[0] + lhs[1] * rhs[3] + lhs[2] * rhs[6],

151:                                  lhs[0] * rhs[1] + lhs[1] * rhs[4] + lhs[2] * rhs[7],

152:                                  lhs[0] * rhs[2] + lhs[1] * rhs[5] + lhs[2] * rhs[8]);

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 172 - 189

--------------------------------------------------------------------------------

172:     ScopedTimer local_timer(timer);

173:

174:     auto u = Lattice.toUnit_floor(P.activeR(iat));

175:     for (int i = 0; i < nBlocks; ++i)

176:       MultiBsplineEvalRef::evaluate_v(einsplines[i], u[0], u[1], u[2], psi[i].data(), nSplinesPerBlock);

177:   }

178:

179:   inline void evaluate(const ParticleSet& P, int iat, ValueVector_t& psi_v)

180:   {

181:     evaluate_v(P, iat);

182:

183:     for (int i = 0; i < nBlocks; ++i)

184:     {

185:       // in real simulation, phase needs to be applied. Here just fake computation

186:       const int first = i * nBlocks;

187:       std::copy_n(psi[i].data(), std::min((i + 1) * nSplinesPerBlock, OrbitalSetSize) - first, psi_v.data() + first);

188:     }

189:   }

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h: 1263 - 1263

--------------------------------------------------------------------------------

1263:       { return _M_data_ptr(this->_M_impl._M_start); }

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h: 170 - 173

--------------------------------------------------------------------------------

170:       if (-std::numeric_limits<T1>::epsilon() < val_dot[i] && val_dot[i] < 0)

171:         val_dot[i] = T1(0.0);

172:       else

173:         val_dot[i] -= std::floor(val_dot[i]);

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/Tensor.h: 213 - 213

--------------------------------------------------------------------------------

213:   inline Type_t operator[](unsigned int i) const { return X[i]; }

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h: 238 - 952

--------------------------------------------------------------------------------

238:       if (__b < __a)

[...]

413: 	{ *__to = *__from; }

[...]

451: 	  if (__builtin_expect(_Num > 1, true))

452: 	    __builtin_memmove(__result, __first, sizeof(_Tp) * _Num);

[...]

951:       for (; __first != __last; ++__first)

952: 	*__first = __tmp;

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algo.h: 683 - 709

--------------------------------------------------------------------------------

683:     { return std::copy(__first, __first + __n, __result); }

[...]

709:       if (__n2 <= 0)

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp: 53 - 63

--------------------------------------------------------------------------------

53:   if (x < 0)

[...]

60:     ind = static_cast<int>(x);

61:     dx = x - ind;

62:     // upper bound

63:     if (ind > nmax)

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 229 - 229

--------------------------------------------------------------------------------

229:     return X[i];

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 143 - 143

--------------------------------------------------------------------------------

143:     return (active_ptcl_ == iat) ? active_pos_ : R[iat];

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp: 54 - 57

--------------------------------------------------------------------------------

54:     a[0] = ((A00 * tx + A01) * tx + A02) * tx + A03;

55:     a[1] = ((A10 * tx + A11) * tx + A12) * tx + A13;

56:     a[2] = ((A20 * tx + A21) * tx + A22) * tx + A23;

57:     a[3] = ((A30 * tx + A31) * tx + A32) * tx + A33;

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 42 - 71

--------------------------------------------------------------------------------

42:   x -= spline_m->x_grid.start;

43:   y -= spline_m->y_grid.start;

44:   z -= spline_m->z_grid.start;

45:   T tx, ty, tz;

46:   int ix, iy, iz;

47:   spline2::getSplineBound(x * spline_m->x_grid.delta_inv, tx, ix, spline_m->x_grid.num - 1);

48:   spline2::getSplineBound(y * spline_m->y_grid.delta_inv, ty, iy, spline_m->y_grid.num - 1);

49:   spline2::getSplineBound(z * spline_m->z_grid.delta_inv, tz, iz, spline_m->z_grid.num - 1);

[...]

56:   const intptr_t xs = spline_m->x_stride;

57:   const intptr_t ys = spline_m->y_stride;

58:   const intptr_t zs = spline_m->z_stride;

59:

60:   constexpr T zero(0);

61:   std::fill(vals, vals + num_splines, zero);

62:

63:   for (size_t i = 0; i < 4; i++)

64:     for (size_t j = 0; j < 4; j++)

65:     {

66:       const T pre00           = a[i] * b[j];

67:       const T* restrict coefs = spline_m->coefs + (ix + i) * xs + (iy + j) * ys + iz * zs;

68:       for (size_t n = 0; n < num_splines; n++)

69:         vals[n] += pre00 *

70:             (c[0] * coefs[n] + c[1] * coefs[n + zs] + c[2] * coefs[n + 2 * zs] +

71:              c[3] * coefs[n + 3 * zs]);

0x47cbb0 PUSH	%RBP

0x47cbb1 MOV	%RSP,%RBP

0x47cbb4 PUSH	%R15

0x47cbb6 MOVSXD	%EDX,%R15

0x47cbb9 PUSH	%R14

0x47cbbb MOV	%RSI,%R14

0x47cbbe PUSH	%R13

0x47cbc0 PUSH	%R12

0x47cbc2 MOV	%RCX,%R12

0x47cbc5 PUSH	%RBX

0x47cbc6 MOV	%RDI,%RBX

0x47cbc9 AND	$-0x20,%RSP

0x47cbcd SUB	$0x120,%RSP

0x47cbd4 MOV	0x358(%RDI),%R13

0x47cbdb MOV	%R13,%RDI

0x47cbde CALL	52c850 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>

0x47cbe3 LEA	0x128(%R14),%RCX

0x47cbea CMP	0x124(%R14),%R15D

0x47cbf1 JE	47cbff

0x47cbf3 MOV	0x40(%R14),%RAX

0x47cbf7 LEA	(%R15,%R15,2),%RDX

0x47cbfb LEA	(%RAX,%RDX,8),%RCX

0x47cbff VMOVUPD	(%RCX),%XMM0

0x47cc03 VMOVSD	0x10(%RCX),%XMM2

0x47cc08 VPERMILPD	$0x3,%XMM0,%XMM4

0x47cc0e VMULPD	0xf0(%RBX),%XMM4,%XMM8

0x47cc16 VPERMILPD	$0,%XMM0,%XMM3

0x47cc1c VMULSD	0x118(%RBX),%XMM2,%XMM6

0x47cc24 VMOVDDUP	%XMM2,%XMM1

0x47cc28 VMOVSD	(%RCX),%XMM5

0x47cc2c VFMADD231PD	0xd8(%RBX),%XMM3,%XMM8

0x47cc35 VMOVDDUP	0x13aae3(%RIP),%XMM9

0x47cc3d VFMADD231SD	0xe8(%RBX),%XMM5,%XMM6

0x47cc46 VUNPCKHPD	%XMM0,%XMM0,%XMM7

0x47cc4a VXORPD	%XMM10,%XMM10,%XMM10

0x47cc4f VFMADD132PD	0x108(%RBX),%XMM8,%XMM1

0x47cc58 VXORPD	%XMM13,%XMM13,%XMM13

0x47cc5d VFMADD132SD	0x100(%RBX),%XMM6,%XMM7

0x47cc66 VCMPPD	$0xe,%XMM9,%XMM1,%K1

0x47cc6d VRNDSCALEPD	$0x9,%XMM1,%XMM11

0x47cc74 VCMPPD	$0x1,%XMM10,%XMM1,%K0{%K1}

0x47cc7b KMOVB	%K0,%ESI

0x47cc7f NOT	%ESI

0x47cc81 AND	$0x3,%ESI

0x47cc84 VCOMISD	%XMM7,%XMM13

0x47cc88 KMOVB	%ESI,%K2

0x47cc8c VSUBPD	%XMM11,%XMM1,%XMM12{%K2}{z}

0x47cc92 JBE	47cca2

0x47cc94 VCOMISD	0x13aa84(%RIP),%XMM7

0x47cc9c JA	47d615

0x47cca2 VRNDSCALESD	$0x9,%XMM7,%XMM7,%XMM14

0x47cca9 VSUBSD	%XMM14,%XMM7,%XMM15

0x47ccae MOVSXD	0x30(%RBX),%R8

0x47ccb2 TEST	%R8D,%R8D

0x47ccb5 JLE	47d452

0x47ccbb MOVSXD	0x40(%RBX),%R9

0x47ccbf MOV	0x2f8(%RBX),%R14

0x47ccc6 MOV	0x310(%RBX),%R11

0x47cccd LEA	(,%R9,8),%RDI

0x47ccd5 LEA	(%R14,%R8,8),%R15

0x47ccd9 LEA	-0x1(%R9),%RDX

0x47ccdd MOV	%R9,0xc0(%RSP)

0x47cce5 MOV	%RDI,0x50(%RSP)

0x47ccea MOV	%R11,0x48(%RSP)

0x47ccef MOV	%R15,0x38(%RSP)

0x47ccf4 MOV	%RDX,0x80(%RSP)

0x47ccfc MOV	%R9D,0x5c(%RSP)

0x47cd01 MOV	%RBX,0x10(%RSP)

0x47cd06 MOV	%R12,0x8(%RSP)

0x47cd0b MOV	%R13,0x18(%RSP)

0x47cd10 VMOVHPD	%XMM12,0x28(%RSP)

0x47cd16 VMOVLPD	%XMM12,0x30(%RSP)

0x47cd1c MOV	%R14,%R13

0x47cd1f VMOVSD	%XMM15,0x20(%RSP)

(953) 0x47cd25 MOV	(%R13),%RCX

(953) 0x47cd29 VMOVSD	0x30(%RSP),%XMM4

(953) 0x47cd2f VXORPD	%XMM5,%XMM5,%XMM5

(953) 0x47cd33 VSUBSD	0x28(%RCX),%XMM4,%XMM2

(953) 0x47cd38 MOV	0x48(%RSP),%RBX

(953) 0x47cd3d VMOVSD	0x28(%RSP),%XMM0

(953) 0x47cd43 VMULSD	0x48(%RCX),%XMM2,%XMM6

(953) 0x47cd48 VMOVSD	0x20(%RSP),%XMM3

(953) 0x47cd4e VSUBSD	0x50(%RCX),%XMM0,%XMM1

(953) 0x47cd53 VSUBSD	0x78(%RCX),%XMM3,%XMM11

(953) 0x47cd58 MOV	(%RBX),%R15

(953) 0x47cd5b VCOMISD	%XMM6,%XMM5

(953) 0x47cd5f JA	47d59b

(953) 0x47cd65 VCVTTSD2SI	%XMM6,%R12D

(953) 0x47cd69 MOV	0x38(%RCX),%EAX

(953) 0x47cd6c DEC	%EAX

(953) 0x47cd6e CMP	%R12D,%EAX

(953) 0x47cd71 JL	47d5c4

(953) 0x47cd77 VRNDSCALESD	$0xb,%XMM6,%XMM6,%XMM7

(953) 0x47cd7e VSUBSD	%XMM7,%XMM6,%XMM9

(953) 0x47cd82 VMOVSD	0x13a866(%RIP),%XMM13

(953) 0x47cd8a VMOVSD	0x13a7ee(%RIP),%XMM10

(953) 0x47cd92 VMULSD	0x13a98e(%RIP),%XMM9,%XMM12

(953) 0x47cd9a VMOVAPD	%XMM9,%XMM0

(953) 0x47cd9e VFNMADD132SD	%XMM13,%XMM13,%XMM0

(953) 0x47cda3 VMOVAPD	%XMM9,%XMM15

(953) 0x47cda8 VFMADD213SD	0x13a97f(%RIP),%XMM13,%XMM15

(953) 0x47cdb1 VADDSD	%XMM13,%XMM12,%XMM14

(953) 0x47cdb6 VMULSD	%XMM9,%XMM9,%XMM8

(953) 0x47cdbb VFMADD231SD	%XMM0,%XMM9,%XMM13

(953) 0x47cdc0 VFMADD213SD	0x13a817(%RIP),%XMM9,%XMM14

(953) 0x47cdc9 VXORPD	0x1390cf(%RIP),%XMM12,%XMM3

(953) 0x47cdd1 MOVSXD	%R12D,%RSI

(953) 0x47cdd4 VFMADD213SD	0x13a7d3(%RIP),%XMM8,%XMM15

(953) 0x47cddd VMULSD	%XMM8,%XMM3,%XMM4

(953) 0x47cde2 VFMADD132SD	%XMM9,%XMM10,%XMM14

(953) 0x47cde7 VFMADD231SD	%XMM13,%XMM9,%XMM10

(953) 0x47cdec MOV	%RSI,0xd8(%RSP)

(953) 0x47cdf4 VUNPCKLPD	%XMM15,%XMM14,%XMM6

(953) 0x47cdf9 VUNPCKLPD	%XMM4,%XMM10,%XMM2

(953) 0x47cdfd VINSERTF64X2	$0x1,%XMM2,%YMM6,%YMM13

(953) 0x47ce04 VMULSD	0x70(%RCX),%XMM1,%XMM1

(953) 0x47ce09 VXORPD	%XMM5,%XMM5,%XMM5

(953) 0x47ce0d VCOMISD	%XMM1,%XMM5

(953) 0x47ce11 JA	47d58b

(953) 0x47ce17 VCVTTSD2SI	%XMM1,%R9D

(953) 0x47ce1b MOV	0x60(%RCX),%R8D

(953) 0x47ce1f DEC	%R8D

(953) 0x47ce22 CMP	%R9D,%R8D

(953) 0x47ce25 JL	47d5b4

(953) 0x47ce2b VRNDSCALESD	$0xb,%XMM1,%XMM1,%XMM7

(953) 0x47ce32 VSUBSD	%XMM7,%XMM1,%XMM12

(953) 0x47ce36 VMOVSD	0x13a742(%RIP),%XMM14

(953) 0x47ce3e VMOVSD	0x13a7aa(%RIP),%XMM15

(953) 0x47ce46 VMULSD	%XMM14,%XMM12,%XMM10

(953) 0x47ce4b VMOVAPD	%XMM12,%XMM8

(953) 0x47ce50 VFNMADD132SD	%XMM15,%XMM15,%XMM8

(953) 0x47ce55 VMOVAPD	%XMM12,%XMM3

(953) 0x47ce59 VMULSD	%XMM12,%XMM12,%XMM9

(953) 0x47ce5e VSUBSD	%XMM10,%XMM15,%XMM0

(953) 0x47ce63 VFMADD213SD	0x13a8c4(%RIP),%XMM15,%XMM3

(953) 0x47ce6c VFMADD231SD	%XMM8,%XMM12,%XMM15

(953) 0x47ce71 VFMADD213SD	0x13a766(%RIP),%XMM12,%XMM0

(953) 0x47ce7a VMULSD	%XMM9,%XMM10,%XMM4

(953) 0x47ce7f MOVSXD	%R9D,%R11

(953) 0x47ce82 VFMADD213SD	0x13a725(%RIP),%XMM9,%XMM3

(953) 0x47ce8b VFMADD132SD	%XMM12,%XMM14,%XMM0

(953) 0x47ce90 VFMADD231SD	%XMM15,%XMM12,%XMM14

(953) 0x47ce95 VUNPCKLPD	%XMM3,%XMM0,%XMM2

(953) 0x47ce99 VUNPCKLPD	%XMM4,%XMM14,%XMM6

(953) 0x47ce9d VINSERTF64X2	$0x1,%XMM6,%YMM2,%YMM1

(953) 0x47cea4 VMULSD	0x98(%RCX),%XMM11,%XMM11

(953) 0x47ceac VXORPD	%XMM5,%XMM5,%XMM5

(953) 0x47ceb0 VCOMISD	%XMM11,%XMM5

(953) 0x47ceb5 JA	47d560

(953) 0x47cebb VCVTTSD2SI	%XMM11,%R10D

(953) 0x47cec0 MOV	0x88(%RCX),%EAX

(953) 0x47cec6 DEC	%EAX

(953) 0x47cec8 CMP	%R10D,%EAX

(953) 0x47cecb JL	47d5db

(953) 0x47ced1 VRNDSCALESD	$0xb,%XMM11,%XMM11,%XMM7

(953) 0x47ced8 VSUBSD	%XMM7,%XMM11,%XMM9

(953) 0x47cedc VMOVSD	0x13a70c(%RIP),%XMM15

(953) 0x47cee4 VMOVSD	0x13a694(%RIP),%XMM0

(953) 0x47ceec VMULSD	0x13a834(%RIP),%XMM9,%XMM14

(953) 0x47cef4 VMOVAPD	%XMM9,%XMM3

(953) 0x47cef8 VFNMADD132SD	%XMM15,%XMM15,%XMM3

(953) 0x47cefd VMOVAPD	%XMM9,%XMM12

(953) 0x47cf02 VMULSD	%XMM9,%XMM9,%XMM10

(953) 0x47cf07 VADDSD	%XMM15,%XMM14,%XMM11

(953) 0x47cf0c VFMADD213SD	0x13a81b(%RIP),%XMM15,%XMM12

(953) 0x47cf15 VFMADD231SD	%XMM3,%XMM9,%XMM15

(953) 0x47cf1a VFMADD213SD	0x13a6bd(%RIP),%XMM9,%XMM11

(953) 0x47cf23 VXORPD	0x138f75(%RIP),%XMM14,%XMM8

(953) 0x47cf2b MOVSXD	%R10D,%RDI

(953) 0x47cf2e VFMADD213SD	0x13a679(%RIP),%XMM10,%XMM12

(953) 0x47cf37 VMULSD	%XMM10,%XMM8,%XMM10

(953) 0x47cf3c VFMADD132SD	%XMM9,%XMM0,%XMM11

(953) 0x47cf41 VFMADD132SD	%XMM15,%XMM0,%XMM9

(953) 0x47cf46 MOV	%RDI,0xd0(%RSP)

(953) 0x47cf4e CMPQ	$0,0x50(%RSP)

(953) 0x47cf54 MOV	0x10(%RCX),%RBX

(953) 0x47cf58 MOV	0x18(%RCX),%R12

(953) 0x47cf5c MOV	0x20(%RCX),%R14

(953) 0x47cf60 VMOVAPD	%YMM13,0xe0(%RSP)

(953) 0x47cf69 VMOVAPD	%YMM1,0x100(%RSP)

(953) 0x47cf72 JE	47cfee

(953) 0x47cf74 MOV	%R11,0xb8(%RSP)

(953) 0x47cf7c MOV	%RCX,0xc8(%RSP)

(953) 0x47cf84 MOV	0x50(%RSP),%RDX

(953) 0x47cf89 VMOVSD	%XMM10,0x98(%RSP)

(953) 0x47cf92 VMOVSD	%XMM9,0xa0(%RSP)

(953) 0x47cf9b VMOVSD	%XMM12,0xa8(%RSP)

(953) 0x47cfa4 VMOVSD	%XMM11,0xb0(%RSP)

(953) 0x47cfad XOR	%ESI,%ESI

(953) 0x47cfaf MOV	%R15,%RDI

(953) 0x47cfb2 VZEROUPPER

(953) 0x47cfb5 CALL	404140 <memset@plt>

(953) 0x47cfba MOV	0xc8(%RSP),%RCX

(953) 0x47cfc2 MOV	0xb8(%RSP),%R11

(953) 0x47cfca VMOVSD	0xb0(%RSP),%XMM11

(953) 0x47cfd3 VMOVSD	0xa8(%RSP),%XMM12

(953) 0x47cfdc VMOVSD	0xa0(%RSP),%XMM9

(953) 0x47cfe5 VMOVSD	0x98(%RSP),%XMM10

(953) 0x47cfee MOV	0xd0(%RSP),%R9

(953) 0x47cff6 MOV	0xc0(%RSP),%RSI

(953) 0x47cffe IMUL	%R14,%R9

(953) 0x47d002 MOV	0x8(%RCX),%R8

(953) 0x47d006 TEST	%RSI,%RSI

(953) 0x47d009 JE	47d42b

(953) 0x47d00f MOV	0xd8(%RSP),%RDX

(953) 0x47d017 MOV	%R11,%RAX

(953) 0x47d01a LEA	0x1(%R11),%RCX

(953) 0x47d01e IMUL	%RBX,%RDX

(953) 0x47d022 IMUL	%R12,%RAX

(953) 0x47d026 IMUL	%R12,%RCX

(953) 0x47d02a SHR	$0x2,%RSI

(953) 0x47d02e ADD	%RDX,%RAX

(953) 0x47d031 ADD	%RDX,%RCX

(953) 0x47d034 LEA	(%RAX,%R9,1),%R10

(953) 0x47d038 LEA	(%RCX,%R9,1),%RCX

(953) 0x47d03c MOV	%R12,%R9

(953) 0x47d03f SAL	$0x4,%R9

(953) 0x47d043 SAL	$0x5,%RSI

(953) 0x47d047 MOV	%R9,0x90(%RSP)

(953) 0x47d04f MOV	%RSI,0xd8(%RSP)

(953) 0x47d057 MOV	%RBX,0x60(%RSP)

(953) 0x47d05c LEA	(%R12,%R12,1),%R12

(953) 0x47d060 LEA	(,%R14,8),%RDX

(953) 0x47d068 MOV	%R12,0x88(%RSP)

(953) 0x47d070 MOV	%R13,0x40(%RSP)

(953) 0x47d075 MOV	%R14,%R12

(953) 0x47d078 LEA	0xe0(%RSP),%RDI

(953) 0x47d080 VBROADCASTSD	%XMM11,%YMM5

(953) 0x47d085 VBROADCASTSD	%XMM12,%YMM4

(953) 0x47d08a VBROADCASTSD	%XMM9,%YMM3

(953) 0x47d08f MOV	%R8,%R14

(953) 0x47d092 MOV	%RDX,%R13

  (955) 0x47d095 MOV	0x5c(%RSP),%R8D

  (955) 0x47d09a LEA	0x100(%RSP),%RBX

  (955) 0x47d0a2 AND	$0x3,%R8D

  (955) 0x47d0a6 MOV	%RCX,0xc8(%RSP)

  (955) 0x47d0ae MOV	%R8D,0x98(%RSP)

  (955) 0x47d0b6 MOV	%RDI,0x78(%RSP)

  (955) 0x47d0bb MOV	%RCX,0x68(%RSP)

  (955) 0x47d0c0 LEA	(%R14,%R10,8),%RDX

  (955) 0x47d0c4 MOV	%R10,0xd0(%RSP)

  (955) 0x47d0cc MOV	%R10,0x70(%RSP)

  (955) 0x47d0d1 VMOVSD	(%RDI),%XMM8

  (955) 0x47d0d5 MOV	%RBX,%R10

  (955) 0x47d0d8 LEA	(%R14,%RCX,8),%RAX

  (955) 0x47d0dc MOV	%R14,%RBX

  (955) 0x47d0df VBROADCASTSD	%XMM10,%YMM2

  (955) 0x47d0e4 MOV	%R13,%R14

  (955) 0x47d0e7 VMOVDDUP	%XMM11,%XMM15

  (955) 0x47d0ec VMOVDDUP	%XMM12,%XMM14

  (955) 0x47d0f1 VMOVDDUP	%XMM9,%XMM13

  (955) 0x47d0f6 MOV	%R10,%R13

    (954) 0x47d0f9 CMPQ	$0x2,0x80(%RSP)

    (954) 0x47d102 VMULSD	(%R13),%XMM8,%XMM19

    (954) 0x47d109 JBE	47d559

    (954) 0x47d10f VMULSD	0x8(%R13),%XMM8,%XMM6

    (954) 0x47d115 LEA	(%R14,%RAX,1),%RDI

    (954) 0x47d119 LEA	(%R14,%RDX,1),%R9

    (954) 0x47d11d LEA	(%R14,%RDI,1),%RSI

    (954) 0x47d121 LEA	(%R9,%R14,1),%R8

    (954) 0x47d125 LEA	(%RSI,%R14,1),%R10

    (954) 0x47d129 MOV	%R10,0xb8(%RSP)

    (954) 0x47d131 LEA	(%R14,%R8,1),%R11

    (954) 0x47d135 VBROADCASTSD	%XMM19,%YMM7

    (954) 0x47d13b VBROADCASTSD	%XMM6,%YMM6

    (954) 0x47d140 XOR	%ECX,%ECX

    (954) 0x47d142 TESTB	$0x20,0xd8(%RSP)

    (954) 0x47d14a JNE	47d4e0

    (954) 0x47d150 MOV	%RBX,0xb0(%RSP)

    (954) 0x47d158 NOPL	(%RAX,%RAX,1)

      (956) 0x47d160 VMULPD	(%R9,%RCX,1),%YMM4,%YMM1

      (956) 0x47d166 VMULPD	(%R11,%RCX,1),%YMM2,%YMM23

      (956) 0x47d16d VMULPD	(%RDI,%RCX,1),%YMM4,%YMM0

      (956) 0x47d172 VMULPD	(%R10,%RCX,1),%YMM2,%YMM24

      (956) 0x47d179 VMULPD	0x20(%R11,%RCX,1),%YMM2,%YMM25

      (956) 0x47d181 VFMADD231PD	(%RDX,%RCX,1),%YMM5,%YMM1

      (956) 0x47d187 VFMADD231PD	(%R8,%RCX,1),%YMM3,%YMM23

      (956) 0x47d18e VFMADD231PD	(%RAX,%RCX,1),%YMM5,%YMM0

      (956) 0x47d194 VFMADD231PD	(%RSI,%RCX,1),%YMM3,%YMM24

      (956) 0x47d19b VFMADD231PD	0x20(%RCX,%R8,1),%YMM3,%YMM25

      (956) 0x47d1a3 VMULPD	0x20(%R10,%RCX,1),%YMM2,%YMM26

      (956) 0x47d1ab VADDPD	%YMM23,%YMM1,%YMM1

      (956) 0x47d1b1 MOV	0xd8(%RSP),%RBX

      (956) 0x47d1b9 VADDPD	%YMM24,%YMM0,%YMM0

      (956) 0x47d1bf VFMADD213PD	(%R15,%RCX,1),%YMM7,%YMM1

      (956) 0x47d1c5 VFMADD231PD	0x20(%RSI,%RCX,1),%YMM3,%YMM26

      (956) 0x47d1cd VFMADD132PD	%YMM6,%YMM1,%YMM0

      (956) 0x47d1d2 VMULPD	0x20(%R9,%RCX,1),%YMM4,%YMM1

      (956) 0x47d1d9 VMOVUPD	%YMM0,(%R15,%RCX,1)

      (956) 0x47d1df VFMADD231PD	0x20(%RCX,%RDX,1),%YMM5,%YMM1

      (956) 0x47d1e6 VMULPD	0x20(%RCX,%RDI,1),%YMM4,%YMM0

      (956) 0x47d1ec VADDPD	%YMM25,%YMM1,%YMM1

      (956) 0x47d1f2 VFMADD231PD	0x20(%RCX,%RAX,1),%YMM5,%YMM0

      (956) 0x47d1f9 VFMADD213PD	0x20(%R15,%RCX,1),%YMM7,%YMM1

      (956) 0x47d200 VADDPD	%YMM26,%YMM0,%YMM0

      (956) 0x47d206 VFMADD132PD	%YMM6,%YMM1,%YMM0

      (956) 0x47d20b VMOVUPD	%YMM0,0x20(%R15,%RCX,1)

      (956) 0x47d212 ADD	$0x40,%RCX

      (956) 0x47d216 CMP	%RBX,%RCX

      (956) 0x47d219 JNE	47d160

    (954) 0x47d21f MOV	0xb0(%RSP),%RBX

    (954) 0x47d227 MOV	0xc0(%RSP),%RCX

    (954) 0x47d22f MOV	0x98(%RSP),%ESI

    (954) 0x47d236 AND	$-0x4,%RCX

    (954) 0x47d23a TEST	%ESI,%ESI

    (954) 0x47d23c JE	47d3b6

    (954) 0x47d242 MOV	0xc0(%RSP),%R10

    (954) 0x47d24a SUB	%RCX,%R10

    (954) 0x47d24d CMP	$0x1,%R10

    (954) 0x47d251 JE	47d35a

    (954) 0x47d257 MOV	0xd0(%RSP),%RDI

    (954) 0x47d25f VMOVDDUP	%XMM10,%XMM6

    (954) 0x47d264 LEA	(%RDI,%R12,1),%R8

    (954) 0x47d268 LEA	(%R12,%R8,1),%RSI

    (954) 0x47d26c MOV	0xc8(%RSP),%RDI

    (954) 0x47d274 LEA	(%RSI,%RCX,1),%R11

    (954) 0x47d278 ADD	%R12,%RSI

    (954) 0x47d27b ADD	%RCX,%RSI

    (954) 0x47d27e MOV	%RSI,0xb0(%RSP)

    (954) 0x47d286 LEA	(%R12,%RDI,1),%RSI

    (954) 0x47d28a MOV	%R11,0xb8(%RSP)

    (954) 0x47d292 LEA	(%RDI,%RCX,1),%R11

    (954) 0x47d296 LEA	(%RCX,%RSI,1),%RDI

    (954) 0x47d29a MOV	%RDI,0xa8(%RSP)

    (954) 0x47d2a2 ADD	%RCX,%R8

    (954) 0x47d2a5 VMULPD	(%RBX,%R8,8),%XMM14,%XMM28

    (954) 0x47d2ac MOV	0xb0(%RSP),%R8

    (954) 0x47d2b4 ADD	%R12,%RSI

    (954) 0x47d2b7 VMULPD	(%RBX,%R8,8),%XMM6,%XMM7

    (954) 0x47d2bd MOV	0xa8(%RSP),%R8

    (954) 0x47d2c5 LEA	(%RCX,%RSI,1),%RDI

    (954) 0x47d2c9 VMULPD	(%RBX,%R8,8),%XMM14,%XMM31

    (954) 0x47d2d0 ADD	%R12,%RSI

    (954) 0x47d2d3 ADD	%RCX,%RSI

    (954) 0x47d2d6 MOV	%RSI,0xa0(%RSP)

    (954) 0x47d2de MOV	0xd0(%RSP),%RSI

    (954) 0x47d2e6 VFMADD231PD	(%RBX,%R11,8),%XMM15,%XMM31

    (954) 0x47d2ed ADD	%RCX,%RSI

    (954) 0x47d2f0 VFMADD231PD	(%RBX,%RSI,8),%XMM15,%XMM28

    (954) 0x47d2f7 MOV	0xa0(%RSP),%R11

    (954) 0x47d2ff MOV	0xb8(%RSP),%RSI

    (954) 0x47d307 VMULPD	(%RBX,%R11,8),%XMM6,%XMM0

    (954) 0x47d30d VFMADD231PD	(%RBX,%RSI,8),%XMM13,%XMM7

    (954) 0x47d313 LEA	(%R15,%RCX,8),%R9

    (954) 0x47d317 VMULSD	0x8(%R13),%XMM8,%XMM29

    (954) 0x47d31e VMOVDDUP	%XMM19,%XMM27

    (954) 0x47d324 VFMADD231PD	(%RBX,%RDI,8),%XMM13,%XMM0

    (954) 0x47d32a VADDPD	%XMM28,%XMM7,%XMM1

    (954) 0x47d330 VMOVDDUP	%XMM29,%XMM30

    (954) 0x47d336 VFMADD213PD	(%R9),%XMM27,%XMM1

    (954) 0x47d33c VADDPD	%XMM0,%XMM31,%XMM6

    (954) 0x47d342 VFMADD132PD	%XMM30,%XMM1,%XMM6

    (954) 0x47d348 VMOVUPD	%XMM6,(%R9)

    (954) 0x47d34d TEST	$0x1,%R10B

    (954) 0x47d351 JE	47d3b6

    (954) 0x47d353 AND	$-0x2,%R10

    (954) 0x47d357 ADD	%R10,%RCX

    (954) 0x47d35a LEA	(%R12,%RCX,1),%RSI

    (954) 0x47d35e LEA	(%R12,%RSI,1),%RDI

    (954) 0x47d362 LEA	(%RDI,%R12,1),%R9

    (954) 0x47d366 VMULSD	(%RDX,%RDI,8),%XMM9,%XMM7

    (954) 0x47d36b VMULSD	(%RDX,%R9,8),%XMM10,%XMM1

    (954) 0x47d371 VMULSD	(%RAX,%RDI,8),%XMM9,%XMM6

    (954) 0x47d376 VMULSD	(%RAX,%R9,8),%XMM10,%XMM0

    (954) 0x47d37c LEA	(%R15,%RCX,8),%R8

    (954) 0x47d380 VFMADD231SD	(%RDX,%RSI,8),%XMM12,%XMM7

    (954) 0x47d386 VFMADD231SD	(%RDX,%RCX,8),%XMM11,%XMM1

    (954) 0x47d38c VFMADD231SD	(%RAX,%RSI,8),%XMM12,%XMM6

    (954) 0x47d392 VFMADD231SD	(%RAX,%RCX,8),%XMM11,%XMM0

    (954) 0x47d398 VADDSD	%XMM7,%XMM1,%XMM1

    (954) 0x47d39c VMULSD	0x8(%R13),%XMM8,%XMM7

    (954) 0x47d3a2 VADDSD	%XMM6,%XMM0,%XMM6

    (954) 0x47d3a6 VFMADD213SD	(%R8),%XMM19,%XMM1

    (954) 0x47d3ac VFMADD132SD	%XMM7,%XMM1,%XMM6

    (954) 0x47d3b1 VMOVSD	%XMM6,(%R8)

    (954) 0x47d3b6 MOV	0x90(%RSP),%RCX

    (954) 0x47d3be MOV	0x88(%RSP),%R11

    (954) 0x47d3c6 ADD	$0x10,%R13

    (954) 0x47d3ca LEA	0x120(%RSP),%R10

    (954) 0x47d3d2 ADD	%R11,0xd0(%RSP)

    (954) 0x47d3da ADD	%R11,0xc8(%RSP)

    (954) 0x47d3e2 ADD	%RCX,%RDX

    (954) 0x47d3e5 ADD	%RCX,%RAX

    (954) 0x47d3e8 CMP	%R10,%R13

    (954) 0x47d3eb JNE	47d0f9

  (955) 0x47d3f1 MOV	0x78(%RSP),%RDI

  (955) 0x47d3f6 MOV	0x60(%RSP),%RDX

  (955) 0x47d3fb MOV	0x70(%RSP),%R10

  (955) 0x47d400 MOV	0x68(%RSP),%RCX

  (955) 0x47d405 ADD	$0x8,%RDI

  (955) 0x47d409 LEA	0x100(%RSP),%RAX

  (955) 0x47d411 MOV	%R14,%R13

  (955) 0x47d414 ADD	%RDX,%R10

  (955) 0x47d417 MOV	%RBX,%R14

  (955) 0x47d41a ADD	%RDX,%RCX

  (955) 0x47d41d CMP	%RAX,%RDI

  (955) 0x47d420 JNE	47d095

(953) 0x47d426 MOV	0x40(%RSP),%R13

(953) 0x47d42b ADD	$0x8,%R13

(953) 0x47d42f ADDQ	$0x18,0x48(%RSP)

(953) 0x47d435 CMP	%R13,0x38(%RSP)

(953) 0x47d43a JNE	47cd25

0x47d440 MOV	0x18(%RSP),%R13

0x47d445 MOV	0x10(%RSP),%RBX

0x47d44a MOV	0x8(%RSP),%R12

0x47d44f VZEROUPPER

0x47d452 MOV	%R13,%RDI

0x47d455 CALL	52ca80 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>

0x47d45a MOV	0x30(%RBX),%ESI

0x47d45d XOR	%R15D,%R15D

0x47d460 XOR	%R14D,%R14D

0x47d463 TEST	%ESI,%ESI

0x47d465 JLE	47d4c9

(952) 0x47d467 MOV	0x40(%RBX),%EAX

(952) 0x47d46a MOV	%ESI,%R8D

(952) 0x47d46d IMUL	%R14D,%R8D

(952) 0x47d471 INC	%R14D

(952) 0x47d474 IMUL	%R14D,%EAX

(952) 0x47d478 MOV	0x8(%RBX),%R9D

(952) 0x47d47c CMP	%R9D,%EAX

(952) 0x47d47f CMOVG	%R9D,%EAX

(952) 0x47d483 SUB	%R8D,%EAX

(952) 0x47d486 TEST	%EAX,%EAX

(952) 0x47d488 JLE	47d4c0

(952) 0x47d48a MOV	0x310(%RBX),%R11

(952) 0x47d491 MOV	0x18(%R12),%RDI

(952) 0x47d496 CLTQ

(952) 0x47d498 MOVSXD	%R8D,%RCX

(952) 0x47d49b LEA	(,%RAX,8),%RDX

(952) 0x47d4a3 MOV	(%R11,%R15,1),%R10

(952) 0x47d4a7 LEA	(%RDI,%RCX,8),%RDI

(952) 0x47d4ab CMP	$0x8,%RDX

(952) 0x47d4af JE	47d607

(952) 0x47d4b5 MOV	%R10,%RSI

(952) 0x47d4b8 CALL	4040d0 <memmove@plt>

(952) 0x47d4bd MOV	0x30(%RBX),%ESI

(952) 0x47d4c0 ADD	$0x18,%R15

(952) 0x47d4c4 CMP	%ESI,%R14D

(952) 0x47d4c7 JL	47d467

0x47d4c9 LEA	-0x28(%RBP),%RSP

0x47d4cd POP	%RBX

0x47d4ce POP	%R12

0x47d4d0 POP	%R13

0x47d4d2 POP	%R14

0x47d4d4 POP	%R15

0x47d4d6 POP	%RBP

0x47d4d7 RET

0x47d4d8 NOPL	(%RAX,%RAX,1)

    (954) 0x47d4e0 VMULPD	(%R9),%YMM4,%YMM17

    (954) 0x47d4e6 VMULPD	(%R11),%YMM2,%YMM16

    (954) 0x47d4ec VMULPD	(%R10),%YMM2,%YMM18

    (954) 0x47d4f2 VMULPD	(%RDI),%YMM4,%YMM21

    (954) 0x47d4f8 MOV	0xd8(%RSP),%R10

    (954) 0x47d500 VFMADD231PD	(%RDX),%YMM5,%YMM17

    (954) 0x47d506 VFMADD231PD	(%R8),%YMM3,%YMM16

    (954) 0x47d50c VFMADD231PD	(%RSI),%YMM3,%YMM18

    (954) 0x47d512 VFMADD231PD	(%RAX),%YMM5,%YMM21

    (954) 0x47d518 MOV	$0x20,%ECX

    (954) 0x47d51d VADDPD	%YMM16,%YMM17,%YMM20

    (954) 0x47d523 VADDPD	%YMM18,%YMM21,%YMM22

    (954) 0x47d529 VFMADD213PD	(%R15),%YMM7,%YMM20

    (954) 0x47d52f VFMADD132PD	%YMM6,%YMM20,%YMM22

    (954) 0x47d535 VMOVUPD	%YMM22,(%R15)

    (954) 0x47d53b CMP	%R10,%RCX

    (954) 0x47d53e JE	47d227

    (954) 0x47d544 MOV	%RBX,0xb0(%RSP)

    (954) 0x47d54c MOV	0xb8(%RSP),%R10

    (954) 0x47d554 JMP	47d160

    (954) 0x47d559 XOR	%ECX,%ECX

    (954) 0x47d55b JMP	47d242

(953) 0x47d560 VMOVSD	0x13a018(%RIP),%XMM9

(953) 0x47d568 MOVQ	$0,0xd0(%RSP)

(953) 0x47d574 VMOVSD	0x13a034(%RIP),%XMM12

(953) 0x47d57c VXORPD	%XMM10,%XMM10,%XMM10

(953) 0x47d581 VMOVAPD	%XMM9,%XMM11

(953) 0x47d586 JMP	47cf4e

(953) 0x47d58b VMOVAPD	0x139fed(%RIP),%YMM1

(953) 0x47d593 XOR	%R11D,%R11D

(953) 0x47d596 JMP	47cea4

(953) 0x47d59b MOVQ	$0,0xd8(%RSP)

(953) 0x47d5a7 VMOVAPD	0x139fd1(%RIP),%YMM13

(953) 0x47d5af JMP	47ce04

(953) 0x47d5b4 VMOVAPD	0x139fe4(%RIP),%YMM1

(953) 0x47d5bc MOVSXD	%R8D,%R11

(953) 0x47d5bf JMP	47cea4

(953) 0x47d5c4 CLTQ

(953) 0x47d5c6 MOV	%RAX,0xd8(%RSP)

(953) 0x47d5ce VMOVAPD	0x139fca(%RIP),%YMM13

(953) 0x47d5d6 JMP	47ce04

(953) 0x47d5db CLTQ

(953) 0x47d5dd MOV	%RAX,0xd0(%RSP)

(953) 0x47d5e5 VMOVSD	0x139fcb(%RIP),%XMM10

(953) 0x47d5ed VMOVSD	0x139fbb(%RIP),%XMM9

(953) 0x47d5f5 VMOVSD	0x139fab(%RIP),%XMM12

(953) 0x47d5fd VXORPD	%XMM11,%XMM11,%XMM11

(953) 0x47d602 JMP	47cf4e

(952) 0x47d607 VMOVSD	(%R10),%XMM8

(952) 0x47d60c VMOVSD	%XMM8,(%RDI)

(952) 0x47d610 JMP	47d4c0

0x47d615 VMOVAPD	%XMM13,%XMM15

0x47d61a JMP	47ccae

0x47d61f NOP

Coverage (%)	Name	Source Location	Module
►49.95+	miniqmcreference::DiracDetermi[...]	OhmmsVector.h:178	exec
○	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:993	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►47.76+	miniqmcreference::DiracDetermi[...]	OhmmsVector.h:178	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:266	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►1.18+	miniqmcreference::DiracDetermi[...]	OhmmsVector.h:178	exec
○	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:993	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
►1.12+	miniqmcreference::DiracDetermi[...]	OhmmsVector.h:178	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:266	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	einspline_spo_ref.hpp:172-189
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h:150-152
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:172-189
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:1263
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170-173
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/Tensor.h:213
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h:238,413,451-452,951-952
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algo.h:683,709
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:53,60-63
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:229
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:143
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:54-57
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:42-49,56-71

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.17 to 7.67 cycles (2.24x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 17.17 to 1.73 cycles (9.95x speedup).

Details

30% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

25% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
50% of SSE/AVX fused multiply-add instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

qmcplusplus::TimerType
::start(): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242
qmcplusplus::TimerType
::stop(): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170
VRNDSCALEPD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:173
VRNDSCALESD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:173
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:175

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 18 FP arithmetical operations:

9: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 192 bytes (24 double precision FP elements). The binary function is storing 92 bytes (11 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	97
nb uops	103
loop length	446
used x86 registers	15
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	13
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.17 cycles
front end	17.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.00	7.50	9.67	9.67	10.00	7.50	7.00	10.00	10.00	10.00	7.00	9.67
cycles	7.00	7.50	9.67	9.67	10.00	7.50	7.00	10.00	10.00	10.00	7.00	9.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.17
Dispatch	10.00
Overall L1	17.17

Vectorization ratios

INT

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	46%
load	36%
store	0%
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	61%

INT+FP

all	30%
load	25%
store	0%
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	12%
load	11%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	18%
load	17%
store	12%
mul	18%
add-sub	18%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	15%
load	15%
store	11%
mul	18%
add-sub	18%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 17.17 cycles. At this rate:

5% of peak load performance is reached (11.18 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.36 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 17.17 to 10.00 cycles (1.72x speedup).

ASM code

In the binary file, the address of the function is: 47cbb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOVSXD %EDX,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x20,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x120,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x358(%RDI),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 52c850 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
LEA 0x128(%R14),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP 0x124(%R14),%R15D	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 47cbff <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x4f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x40(%R14),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R15,%R15,2),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RAX,%RDX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVUPD (%RCX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0x10(%RCX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPERMILPD $0x3,%XMM0,%XMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	vect (25.0%)
VMULPD 0xf0(%RBX),%XMM4,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VPERMILPD $0,%XMM0,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	vect (25.0%)
VMULSD 0x118(%RBX),%XMM2,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVDDUP %XMM2,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMOVSD (%RCX),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD231PD 0xd8(%RBX),%XMM3,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VMOVDDUP 0x13aae3(%RIP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD231SD 0xe8(%RBX),%XMM5,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VUNPCKHPD %XMM0,%XMM0,%XMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VXORPD %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD132PD 0x108(%RBX),%XMM8,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VXORPD %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD132SD 0x100(%RBX),%XMM6,%XMM7	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VCMPPD $0xe,%XMM9,%XMM1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VRNDSCALEPD $0x9,%XMM1,%XMM11	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (25.0%)
VCMPPD $0x1,%XMM10,%XMM1,%K0{%K1}	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
KMOVB %K0,%ESI	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
NOT %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x3,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VCOMISD %XMM7,%XMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
KMOVB %ESI,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	N/A
VSUBPD %XMM11,%XMM1,%XMM12{%K2}{z}	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
JBE 47cca2 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xf2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VCOMISD 0x13aa84(%RIP),%XMM7	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JA 47d615 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xa65>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VRNDSCALESD $0x9,%XMM7,%XMM7,%XMM14	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VSUBSD %XMM14,%XMM7,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
MOVSXD 0x30(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %R8D,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 47d452 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x8a2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVSXD 0x40(%RBX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2f8(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x310(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (,%R9,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R14,%R8,8),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x1(%R9),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9D,0x5c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RBX,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVHPD %XMM12,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
VMOVLPD %XMM12,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
MOV %R14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVSD %XMM15,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 52ca80 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x30(%RBX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %ESI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JLE 47d4c9 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x919>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPD %XMM13,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JMP 47ccae <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xfe>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	einspline_spo_ref.hpp:172-189
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h:150-152
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:172-189
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:1263
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170-173
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/Tensor.h:213
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h:238,413,451-452,951-952
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algo.h:683,709
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:53,60-63
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:229
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:143
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:54-57
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:42-49,56-71

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.17 to 7.67 cycles (2.24x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

30% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

25% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
50% of SSE/AVX fused multiply-add instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

CALL instructions

Detected function call instructions.

Details

qmcplusplus::TimerType
::start(): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242
qmcplusplus::TimerType
::stop(): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:249

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170
VRNDSCALEPD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:173
VRNDSCALESD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:173
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:175

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 18 FP arithmetical operations:

9: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 192 bytes (24 double precision FP elements). The binary function is storing 92 bytes (11 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	97
nb uops	103
loop length	446
used x86 registers	15
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	13
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.17 cycles
front end	17.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.00	7.50	9.67	9.67	10.00	7.50	7.00	10.00	10.00	10.00	7.00	9.67
cycles	7.00	7.50	9.67	9.67	10.00	7.50	7.00	10.00	10.00	10.00	7.00	9.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.17
Dispatch	10.00
Overall L1	17.17

Vectorization ratios

INT

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	46%
load	36%
store	0%
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	61%

INT+FP

all	30%
load	25%
store	0%
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	12%
load	11%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	18%
load	17%
store	12%
mul	18%
add-sub	18%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	15%
load	15%
store	11%
mul	18%
add-sub	18%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 17.17 cycles. At this rate:

5% of peak load performance is reached (11.18 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.36 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 47cbb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOVSXD %EDX,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x20,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x120,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x358(%RDI),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 52c850 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
LEA 0x128(%R14),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP 0x124(%R14),%R15D	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 47cbff <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x4f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x40(%R14),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R15,%R15,2),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RAX,%RDX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVUPD (%RCX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0x10(%RCX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPERMILPD $0x3,%XMM0,%XMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	vect (25.0%)
VMULPD 0xf0(%RBX),%XMM4,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VPERMILPD $0,%XMM0,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	vect (25.0%)
VMULSD 0x118(%RBX),%XMM2,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVDDUP %XMM2,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMOVSD (%RCX),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD231PD 0xd8(%RBX),%XMM3,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VMOVDDUP 0x13aae3(%RIP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD231SD 0xe8(%RBX),%XMM5,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VUNPCKHPD %XMM0,%XMM0,%XMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VXORPD %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD132PD 0x108(%RBX),%XMM8,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VXORPD %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD132SD 0x100(%RBX),%XMM6,%XMM7	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VCMPPD $0xe,%XMM9,%XMM1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VRNDSCALEPD $0x9,%XMM1,%XMM11	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (25.0%)
VCMPPD $0x1,%XMM10,%XMM1,%K0{%K1}	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
KMOVB %K0,%ESI	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
NOT %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x3,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VCOMISD %XMM7,%XMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
KMOVB %ESI,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	N/A
VSUBPD %XMM11,%XMM1,%XMM12{%K2}{z}	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
JBE 47cca2 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xf2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VCOMISD 0x13aa84(%RIP),%XMM7	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JA 47d615 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xa65>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VRNDSCALESD $0x9,%XMM7,%XMM7,%XMM14	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VSUBSD %XMM14,%XMM7,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
MOVSXD 0x30(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %R8D,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 47d452 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x8a2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVSXD 0x40(%RBX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2f8(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x310(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (,%R9,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R14,%R8,8),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x1(%R9),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9D,0x5c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RBX,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVHPD %XMM12,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
VMOVLPD %XMM12,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
MOV %R14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVSD %XMM15,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 52ca80 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x30(%RBX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %ESI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JLE 47d4c9 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x919>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPD %XMM13,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JMP 47ccae <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xfe>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)–	19.28	16.44
▼Loop 953 - einspline_spo_ref.hpp:175-176 - exec–	0.00	0.01
▼Loop 955 - MultiBsplineRef.hpp:63-71 - exec–	0.00	0.01
▼Loop 954 - MultiBsplineRef.hpp:64-71 - exec–	0.00	0.01
○Loop 956 - MultiBsplineRef.hpp:68-71 - exec	19.27	16.14
○Loop 952 - einspline_spo_ref.hpp:183-187 - exec	0.00	0.01

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FMA

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

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Cycles summary

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Cycles and memory resources usage

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