OV - exec - Function miniqmcreference::OneBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector<double, std::allocator<double> >&)

	Function: miniqmcreference::OneBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::evaluateRatios( ...	Module: exec	Source: OneBodyJastrowRef.h:132-155 [...]	Coverage (incl. loops): 0.04% \| (excl. loops): 0.00%

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h: 993 - 1150

--------------------------------------------------------------------------------

993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1128:       operator[](size_type __n) _GLIBCXX_NOEXCEPT

1129:       {

1130: 	__glibcxx_requires_subscript(__n);

1131: 	return *(this->_M_impl._M_start + __n);

[...]

1147:       operator[](size_type __n) const _GLIBCXX_NOEXCEPT

1148:       {

1149: 	__glibcxx_requires_subscript(__n);

1150: 	return *(this->_M_impl._M_start + __n);

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/shared_ptr_base.h: 1667 - 1667

--------------------------------------------------------------------------------

1667:       { return _M_ptr; }

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/OneBodyJastrowRef.h: 132 - 155

--------------------------------------------------------------------------------

132:   inline void evaluateRatios(VirtualParticleSet& VP, std::vector<ValueType>& ratios)

133:   {

134:     for (int k = 0; k < ratios.size(); ++k)

135:       ratios[k] = std::exp(Vat[VP.refPtcl] - computeU(VP.getDistTableAB(myTableID).getDistRow(k).data()));

136:   }

137:

138:   inline valT computeU(const valT* dist)

139:   {

140:     valT curVat(0);

141:     if (NumGroups > 0)

142:     {

143:       for (int jg = 0; jg < NumGroups; ++jg)

144:       {

145:         if (F[jg] != nullptr)

146:           curVat += F[jg]->evaluateV(-1, Ions.first(jg), Ions.last(jg), dist, DistCompressed.data());

147:       }

148:     }

149:     else

150:     {

151:       for (int c = 0; c < Nions; ++c)

152:       {

153:         int gid = Ions.GroupID[c];

154:         if (F[gid] != nullptr)

155:           curVat += F[gid]->evaluate(dist[c]);

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 166 - 260

--------------------------------------------------------------------------------

166:     if (r >= cutoff_radius)

167:       return 0.0;

168:     r *= DeltaRInv;

169:     real_type ipart, t;

170:     t     = std::modf(r, &ipart);

171:     int i = (int)ipart;

172:     real_type tp[4];

173:     tp[0] = t * t * t;

[...]

179:       (SplineCoefs[i+0]*(A[ 0]*tp[0] + A[ 1]*tp[1] + A[ 2]*tp[2] + A[ 3]*tp[3])+

180:        SplineCoefs[i+1]*(A[ 4]*tp[0] + A[ 5]*tp[1] + A[ 6]*tp[2] + A[ 7]*tp[3])+

181:        SplineCoefs[i+2]*(A[ 8]*tp[0] + A[ 9]*tp[1] + A[10]*tp[2] + A[11]*tp[3])+

182:        SplineCoefs[i+3]*(A[12]*tp[0] + A[13]*tp[1] + A[14]*tp[2] + A[15]*tp[3]));

[...]

231:   ASSUME_ALIGNED(distArrayCompressed);

232:   int iCount       = 0;

233:   const int iLimit = iEnd - iStart;

234:

235: #pragma vector always

236:   for (int jat = 0; jat < iLimit; jat++)

237:   {

238:     real_type r = distArray[jat];

239:     // pick the distances smaller than the cutoff and avoid the reference atom

240:     if (r < cutoff_radius && iStart + jat != iat)

241:       distArrayCompressed[iCount++] = distArray[jat];

242:   }

243:

244:   real_type d = 0.0;

245:   //#pragma omp simd reduction(+:d)

246:   for (int jat = 0; jat < iCount; jat++)

247:   {

248:     real_type r = distArrayCompressed[jat];

249:     r *= DeltaRInv;

250:     int i         = (int)r;

251:     real_type t   = r - real_type(i);

252:     real_type tp0 = t * t * t;

253:     real_type tp1 = t * t;

254:     real_type tp2 = t;

255:

256:     real_type d1 = SplineCoefs[i + 0] * (A[0] * tp0 + A[1] * tp1 + A[2] * tp2 + A[3]);

257:     real_type d2 = SplineCoefs[i + 1] * (A[4] * tp0 + A[5] * tp1 + A[6] * tp2 + A[7]);

258:     real_type d3 = SplineCoefs[i + 2] * (A[8] * tp0 + A[9] * tp1 + A[10] * tp2 + A[11]);

259:     real_type d4 = SplineCoefs[i + 3] * (A[12] * tp0 + A[13] * tp1 + A[14] * tp2 + A[15]);

260:     d += (d1 + d2 + d3 + d4);

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 249

--------------------------------------------------------------------------------

223:     return X[i];

[...]

229:     return X[i];

[...]

249:   inline const_pointer data() const { return X; }

/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 313 - 316

--------------------------------------------------------------------------------

313:   inline int first(int igroup) const { return (*group_offsets_)[igroup]; }

314:

315:   ///return the last index of a group i

316:   inline int last(int igroup) const { return (*group_offsets_)[igroup + 1]; }

0x41f6f0 LEA	0x8(%RSP),%R10

0x41f6f5 AND	$-0x20,%RSP

0x41f6f9 PUSHQ	-0x8(%R10)

0x41f6fd MOV	$0x1,%EAX

0x41f702 VPBROADCASTD	%EAX,%XMM5

0x41f708 PUSH	%RBP

0x41f709 MOV	%RSP,%RBP

0x41f70c PUSH	%R15

0x41f70e PUSH	%R14

0x41f710 PUSH	%R13

0x41f712 PUSH	%R12

0x41f714 PUSH	%R10

0x41f716 PUSH	%RBX

0x41f717 SUB	$0x1a0,%RSP

0x41f71e MOV	0x8(%RDX),%RCX

0x41f722 MOV	%RSI,-0x1b8(%RBP)

0x41f729 VMOVDQA	%XMM5,-0x1a0(%RBP)

0x41f731 CMP	%RCX,(%RDX)

0x41f734 JE	4203df

0x41f73a XOR	%R15D,%R15D

0x41f73d MOV	%RDI,%RBX

0x41f740 MOV	%RDX,%R14

0x41f743 NOPL	(%RAX,%RAX,1)

(252) 0x41f748 MOV	-0x1b8(%RBP),%RDI

(252) 0x41f74f MOV	0xf0(%RBX),%RSI

(252) 0x41f756 MOVSXD	0x2a0(%RDI),%RDX

(252) 0x41f75d VMOVSD	(%RSI,%RDX,8),%XMM2

(252) 0x41f762 MOV	0xa8(%RBX),%ESI

(252) 0x41f768 VMOVSD	%XMM2,-0x70(%RBP)

(252) 0x41f76d CALL	4c58b0 <_ZNK11qmcplusplus11ParticleSet14getDistTableABEi>

(252) 0x41f772 MOV	0x48(%RAX),%R9

(252) 0x41f776 LEA	(%R15,%R15,4),%R8

(252) 0x41f77a MOVSXD	0x98(%RBX),%R10

(252) 0x41f781 LEA	(%R9,%R8,8),%R11

(252) 0x41f785 MOV	0x18(%R11),%R12

(252) 0x41f789 TEST	%R10D,%R10D

(252) 0x41f78c MOV	%R12,-0x190(%RBP)

(252) 0x41f793 VMOVSD	-0x70(%RBP),%XMM7

(252) 0x41f798 JLE	420400

(252) 0x41f79e MOV	$0x2,%EDX

(252) 0x41f7a3 MOV	$0x1,%R8D

(252) 0x41f7a9 MOVQ	$0,-0x48(%RBP)

(252) 0x41f7b1 MOV	%R14,-0x1b0(%RBP)

(252) 0x41f7b8 VPBROADCASTD	%R8D,%YMM6

(252) 0x41f7be VPBROADCASTD	%EDX,%YMM1

(252) 0x41f7c4 MOV	0x1c8(%RBX),%R13

(252) 0x41f7cb MOV	%R15,-0x1a8(%RBP)

(252) 0x41f7d2 LEA	(,%R10,4),%R12

(252) 0x41f7da XOR	%ESI,%ESI

(252) 0x41f7dc VMOVDQA	%YMM6,-0xf0(%RBP)

(252) 0x41f7e4 VMOVDQA	%YMM1,-0x110(%RBP)

(252) 0x41f7ec VMOVQ	%XMM7,%R15

(252) 0x41f7f1 KXNORB	%K1,%K1,%K1

(252) 0x41f7f5 NOPL	(%RAX)

  (254) 0x41f7f8 MOV	(%R13,%RSI,2),%RCX

  (254) 0x41f7fd TEST	%RCX,%RCX

  (254) 0x41f800 JE	42038e

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  (254) 0x41f81f MOVSXD	(%R10,%RSI,1),%RAX

  (254) 0x41f823 MOV	0x4(%R10,%RSI,1),%R14D

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  (254) 0x41f82b CMP	%EAX,%R14D

  (254) 0x41f82e JLE	42038e

  (254) 0x41f834 MOV	-0x190(%RBP),%RDX

  (254) 0x41f83b MOV	%R14D,%R9D

  (254) 0x41f83e SUB	%EAX,%R9D

  (254) 0x41f841 LEA	(%RDX,%RAX,8),%R8

  (254) 0x41f845 VMOVSD	0x8(%RCX),%XMM9

  (254) 0x41f84a MOV	%EAX,%R10D

  (254) 0x41f84d XOR	%EDX,%EDX

  (254) 0x41f84f AND	$0x7,%R9D

  (254) 0x41f853 JE	41f989

  (254) 0x41f859 CMP	$0x1,%R9D

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  (254) 0x41f877 CMP	$0x4,%R9D

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  (254) 0x41f889 VMOVSD	(%R8),%XMM10

  (254) 0x41f88e VCOMISD	%XMM10,%XMM9

  (254) 0x41f893 JBE	41f8a3

  (254) 0x41f895 CMP	$-0x1,%EAX

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  (254) 0x41f89a VMOVSD	%XMM10,(%RDI)

  (254) 0x41f89e MOV	$0x1,%EDX

  (254) 0x41f8a3 ADD	$0x8,%R8

  (254) 0x41f8a7 LEA	0x1(%R11),%R10D

  (254) 0x41f8ab VMOVSD	(%R8),%XMM11

  (254) 0x41f8b0 VCOMISD	%XMM11,%XMM9

  (254) 0x41f8b5 JBE	41f8c7

  (254) 0x41f8b7 CMP	$-0x1,%R10D

  (254) 0x41f8bb JE	41f8c7

  (254) 0x41f8bd MOVSXD	%EDX,%RAX

  (254) 0x41f8c0 VMOVSD	%XMM11,(%RDI,%RAX,8)

  (254) 0x41f8c5 INC	%EDX

  (254) 0x41f8c7 ADD	$0x8,%R8

  (254) 0x41f8cb INC	%R10D

  (254) 0x41f8ce VMOVSD	(%R8),%XMM12

  (254) 0x41f8d3 VCOMISD	%XMM12,%XMM9

  (254) 0x41f8d8 JBE	41f8eb

  (254) 0x41f8da CMP	$-0x1,%R10D

  (254) 0x41f8de JE	41f8eb

  (254) 0x41f8e0 MOVSXD	%EDX,%R11

  (254) 0x41f8e3 VMOVSD	%XMM12,(%RDI,%R11,8)

  (254) 0x41f8e9 INC	%EDX

  (254) 0x41f8eb ADD	$0x8,%R8

  (254) 0x41f8ef INC	%R10D

  (254) 0x41f8f2 VMOVSD	(%R8),%XMM13

  (254) 0x41f8f7 VCOMISD	%XMM13,%XMM9

  (254) 0x41f8fc JBE	41f90f

  (254) 0x41f8fe CMP	$-0x1,%R10D

  (254) 0x41f902 JE	41f90f

  (254) 0x41f904 MOVSXD	%EDX,%R9

  (254) 0x41f907 VMOVSD	%XMM13,(%RDI,%R9,8)

  (254) 0x41f90d INC	%EDX

  (254) 0x41f90f ADD	$0x8,%R8

  (254) 0x41f913 INC	%R10D

  (254) 0x41f916 VMOVSD	(%R8),%XMM14

  (254) 0x41f91b VCOMISD	%XMM14,%XMM9

  (254) 0x41f920 JBE	41f932

  (254) 0x41f922 CMP	$-0x1,%R10D

  (254) 0x41f926 JE	41f932

  (254) 0x41f928 MOVSXD	%EDX,%RAX

  (254) 0x41f92b VMOVSD	%XMM14,(%RDI,%RAX,8)

  (254) 0x41f930 INC	%EDX

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  (254) 0x41f936 INC	%R10D

  (254) 0x41f939 VMOVSD	(%R8),%XMM15

  (254) 0x41f93e VCOMISD	%XMM15,%XMM9

  (254) 0x41f943 JBE	41f956

  (254) 0x41f945 CMP	$-0x1,%R10D

  (254) 0x41f949 JE	41f956

  (254) 0x41f94b MOVSXD	%EDX,%R11

  (254) 0x41f94e VMOVSD	%XMM15,(%RDI,%R11,8)

  (254) 0x41f954 INC	%EDX

  (254) 0x41f956 ADD	$0x8,%R8

  (254) 0x41f95a INC	%R10D

  (254) 0x41f95d VMOVSD	(%R8),%XMM5

  (254) 0x41f962 VCOMISD	%XMM5,%XMM9

  (254) 0x41f966 JBE	41f979

  (254) 0x41f968 CMP	$-0x1,%R10D

  (254) 0x41f96c JE	41f979

  (254) 0x41f96e MOVSXD	%EDX,%R9

  (254) 0x41f971 VMOVSD	%XMM5,(%RDI,%R9,8)

  (254) 0x41f977 INC	%EDX

  (254) 0x41f979 INC	%R10D

  (254) 0x41f97c ADD	$0x8,%R8

  (254) 0x41f980 CMP	%R10D,%R14D

  (254) 0x41f983 JE	41fa9c

    (255) 0x41f989 VMOVSD	(%R8),%XMM2

    (255) 0x41f98e VCOMISD	%XMM2,%XMM9

    (255) 0x41f992 JBE	41f9a4

    (255) 0x41f994 CMP	$-0x1,%R10D

    (255) 0x41f998 JE	41f9a4

    (255) 0x41f99a MOVSXD	%EDX,%RAX

    (255) 0x41f99d VMOVSD	%XMM2,(%RDI,%RAX,8)

    (255) 0x41f9a2 INC	%EDX

    (255) 0x41f9a4 VMOVSD	0x8(%R8),%XMM4

    (255) 0x41f9aa INC	%R10D

    (255) 0x41f9ad VCOMISD	%XMM4,%XMM9

    (255) 0x41f9b1 LEA	0x8(%R8),%R11

    (255) 0x41f9b5 JBE	41f9c8

    (255) 0x41f9b7 CMP	$-0x1,%R10D

    (255) 0x41f9bb JE	41f9c8

    (255) 0x41f9bd MOVSXD	%EDX,%R8

    (255) 0x41f9c0 VMOVSD	%XMM4,(%RDI,%R8,8)

    (255) 0x41f9c6 INC	%EDX

    (255) 0x41f9c8 VMOVSD	0x8(%R11),%XMM3

    (255) 0x41f9ce LEA	0x1(%R10),%R9D

    (255) 0x41f9d2 VCOMISD	%XMM3,%XMM9

    (255) 0x41f9d6 JBE	41f9e8

    (255) 0x41f9d8 CMP	$-0x1,%R9D

    (255) 0x41f9dc JE	41f9e8

    (255) 0x41f9de MOVSXD	%EDX,%RAX

    (255) 0x41f9e1 VMOVSD	%XMM3,(%RDI,%RAX,8)

    (255) 0x41f9e6 INC	%EDX

    (255) 0x41f9e8 VMOVSD	0x10(%R11),%XMM0

    (255) 0x41f9ee LEA	0x2(%R10),%R8D

    (255) 0x41f9f2 VCOMISD	%XMM0,%XMM9

    (255) 0x41f9f6 JBE	41fa09

    (255) 0x41f9f8 CMP	$-0x1,%R8D

    (255) 0x41f9fc JE	41fa09

    (255) 0x41f9fe MOVSXD	%EDX,%R9

    (255) 0x41fa01 VMOVSD	%XMM0,(%RDI,%R9,8)

    (255) 0x41fa07 INC	%EDX

    (255) 0x41fa09 VMOVSD	0x18(%R11),%XMM8

    (255) 0x41fa0f LEA	0x3(%R10),%EAX

    (255) 0x41fa13 VCOMISD	%XMM8,%XMM9

    (255) 0x41fa18 JBE	41fa2a

    (255) 0x41fa1a CMP	$-0x1,%EAX

    (255) 0x41fa1d JE	41fa2a

    (255) 0x41fa1f MOVSXD	%EDX,%R8

    (255) 0x41fa22 VMOVSD	%XMM8,(%RDI,%R8,8)

    (255) 0x41fa28 INC	%EDX

    (255) 0x41fa2a VMOVSD	0x20(%R11),%XMM7

    (255) 0x41fa30 LEA	0x4(%R10),%R9D

    (255) 0x41fa34 VCOMISD	%XMM7,%XMM9

    (255) 0x41fa38 JBE	41fa4a

    (255) 0x41fa3a CMP	$-0x1,%R9D

    (255) 0x41fa3e JE	41fa4a

    (255) 0x41fa40 MOVSXD	%EDX,%RAX

    (255) 0x41fa43 VMOVSD	%XMM7,(%RDI,%RAX,8)

    (255) 0x41fa48 INC	%EDX

    (255) 0x41fa4a VMOVSD	0x28(%R11),%XMM6

    (255) 0x41fa50 LEA	0x5(%R10),%R8D

    (255) 0x41fa54 VCOMISD	%XMM6,%XMM9

    (255) 0x41fa58 JBE	41fa6b

    (255) 0x41fa5a CMP	$-0x1,%R8D

    (255) 0x41fa5e JE	41fa6b

    (255) 0x41fa60 MOVSXD	%EDX,%R9

    (255) 0x41fa63 VMOVSD	%XMM6,(%RDI,%R9,8)

    (255) 0x41fa69 INC	%EDX

    (255) 0x41fa6b VMOVSD	0x30(%R11),%XMM1

    (255) 0x41fa71 LEA	0x6(%R10),%EAX

    (255) 0x41fa75 VCOMISD	%XMM1,%XMM9

    (255) 0x41fa79 JBE	41fa8b

    (255) 0x41fa7b CMP	$-0x1,%EAX

    (255) 0x41fa7e JE	41fa8b

    (255) 0x41fa80 MOVSXD	%EDX,%R8

    (255) 0x41fa83 VMOVSD	%XMM1,(%RDI,%R8,8)

    (255) 0x41fa89 INC	%EDX

    (255) 0x41fa8b ADD	$0x7,%R10D

    (255) 0x41fa8f LEA	0x38(%R11),%R8

    (255) 0x41fa93 CMP	%R10D,%R14D

    (255) 0x41fa96 JNE	41f989

  (254) 0x41fa9c TEST	%EDX,%EDX

  (254) 0x41fa9e JE	42038e

  (254) 0x41faa4 VMOVSD	0x30(%RCX),%XMM2

  (254) 0x41faa9 VMOVSD	0x50(%RCX),%XMM7

  (254) 0x41faae VMOVSD	0x58(%RCX),%XMM1

  (254) 0x41fab3 VMOVSD	0x68(%RCX),%XMM14

  (254) 0x41fab8 VMOVSD	0x70(%RCX),%XMM15

  (254) 0x41fabd VMOVSD	0x78(%RCX),%XMM12

  (254) 0x41fac2 VMOVSD	0x80(%RCX),%XMM13

  (254) 0x41faca VMOVSD	0x88(%RCX),%XMM11

  (254) 0x41fad2 MOV	0x238(%RCX),%R9

  (254) 0x41fad9 MOV	0x218(%RCX),%RAX

  (254) 0x41fae0 VMOVSD	0x18(%RCX),%XMM6

  (254) 0x41fae5 VMOVSD	0x20(%RCX),%XMM4

  (254) 0x41faea VMOVSD	0x28(%RCX),%XMM5

  (254) 0x41faef VMOVSD	0x38(%RCX),%XMM0

  (254) 0x41faf4 VMOVSD	0x40(%RCX),%XMM10

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  (254) 0x41fafe VMOVSD	0x60(%RCX),%XMM8

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  (254) 0x41fb0b LEA	-0x1(%RDX),%ECX

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  (254) 0x41fb4b CMP	$0x6,%ECX

  (254) 0x41fb4e JBE	4207e1

  (254) 0x41fb54 MOV	%EDX,%R10D

  (254) 0x41fb57 SHR	$0x3,%R10D

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  (254) 0x41fb61 VBROADCASTSD	%XMM2,%YMM24

  (254) 0x41fb67 VBROADCASTSD	%XMM1,%YMM30

  (254) 0x41fb6d VBROADCASTSD	%XMM7,%YMM2

  (254) 0x41fb72 VBROADCASTSD	%XMM14,%YMM1

  (254) 0x41fb77 VBROADCASTSD	%XMM8,%YMM7

  (254) 0x41fb7c VBROADCASTSD	%XMM9,%YMM14

  (254) 0x41fb81 VBROADCASTSD	%XMM15,%YMM20

  (254) 0x41fb87 SAL	$0x6,%R10

  (254) 0x41fb8b VXORPD	%XMM15,%XMM15,%XMM15

  (254) 0x41fb90 VMOVAPD	%YMM14,-0xd0(%RBP)

  (254) 0x41fb98 VBROADCASTSD	%XMM29,%YMM28

  (254) 0x41fb9e VBROADCASTSD	%XMM6,%YMM27

  (254) 0x41fba4 VBROADCASTSD	%XMM4,%YMM26

  (254) 0x41fbaa VBROADCASTSD	%XMM5,%YMM25

  (254) 0x41fbb0 VBROADCASTSD	%XMM0,%YMM23

  (254) 0x41fbb6 VBROADCASTSD	%XMM10,%YMM22

  (254) 0x41fbbc VBROADCASTSD	%XMM3,%YMM21

  (254) 0x41fbc2 VMOVAPD	%YMM2,-0x70(%RBP)

  (254) 0x41fbc7 VMOVAPD	%YMM7,-0x90(%RBP)

  (254) 0x41fbcf VMOVAPD	%YMM1,-0xb0(%RBP)

  (254) 0x41fbd7 VBROADCASTSD	%XMM12,%YMM19

  (254) 0x41fbdd VBROADCASTSD	%XMM13,%YMM18

  (254) 0x41fbe3 VBROADCASTSD	%XMM11,%YMM17

  (254) 0x41fbe9 MOV	%RDI,%R14

  (254) 0x41fbec ADD	%RDI,%R10

  (254) 0x41fbef VMOVAPD	%YMM15,%YMM14

  (254) 0x41fbf4 VMOVSD	%XMM6,-0x150(%RBP)

  (254) 0x41fbfc VMOVSD	%XMM4,-0x158(%RBP)

  (254) 0x41fc04 VMOVSD	%XMM5,-0x160(%RBP)

  (254) 0x41fc0c VMOVSD	%XMM0,-0x168(%RBP)

  (254) 0x41fc14 VMOVSD	%XMM10,-0x170(%RBP)

  (254) 0x41fc1c VMOVSD	%XMM3,-0x178(%RBP)

  (254) 0x41fc24 VMOVSD	%XMM8,-0x180(%RBP)

  (254) 0x41fc2c VMOVSD	%XMM9,-0x188(%RBP)

  (254) 0x41fc34 NOPL	(%RAX)

    (256) 0x41fc38 VMULPD	(%R14),%YMM28,%YMM6

    (256) 0x41fc3e VMULPD	0x20(%R14),%YMM28,%YMM10

    (256) 0x41fc45 VMOVAPD	%YMM25,%YMM7

    (256) 0x41fc4b KMOVB	%K1,%K2

    (256) 0x41fc4f KMOVB	%K1,%K3

    (256) 0x41fc53 VRNDSCALEPD	$0xb,%YMM6,%YMM0

    (256) 0x41fc5a VRNDSCALEPD	$0xb,%YMM10,%YMM3

    (256) 0x41fc61 VCVTTPD2DQ	%YMM6,%XMM4

    (256) 0x41fc65 VCVTTPD2DQ	%YMM10,%XMM5

    (256) 0x41fc6a VINSERTI32X4	$0x1,%XMM5,%YMM4,%YMM1

    (256) 0x41fc71 VPERM2I128	$0x11,%YMM1,%YMM1,%YMM8

    (256) 0x41fc77 VSUBPD	%YMM0,%YMM6,%YMM0

    (256) 0x41fc7b VSUBPD	%YMM3,%YMM10,%YMM2

    (256) 0x41fc7f VMOVAPD	%YMM25,%YMM6

    (256) 0x41fc85 VMULPD	%YMM0,%YMM0,%YMM5

    (256) 0x41fc89 VMULPD	%YMM2,%YMM2,%YMM3

    (256) 0x41fc8d VFMADD132PD	%YMM0,%YMM24,%YMM7

    (256) 0x41fc93 VFMADD132PD	%YMM2,%YMM24,%YMM6

    (256) 0x41fc99 VGATHERDPD	(%RAX,%XMM4,8),%YMM16{%K2}

    (256) 0x41fca0 VMULPD	%YMM0,%YMM5,%YMM10

    (256) 0x41fca4 VMULPD	%YMM5,%YMM26,%YMM12

    (256) 0x41fcaa VMULPD	%YMM2,%YMM3,%YMM9

    (256) 0x41fcae VMULPD	%YMM3,%YMM26,%YMM11

    (256) 0x41fcb4 VPADDD	-0xf0(%RBP),%YMM1,%YMM4

    (256) 0x41fcbc VGATHERDPD	(%RAX,%XMM8,8),%YMM13{%K3}

    (256) 0x41fcc3 VFMADD231PD	%YMM10,%YMM27,%YMM12

    (256) 0x41fcc9 KMOVB	%K1,%K5

    (256) 0x41fccd VFMADD231PD	%YMM9,%YMM27,%YMM11

    (256) 0x41fcd3 KMOVB	%K1,%K4

    (256) 0x41fcd7 VGATHERDPD	(%RAX,%XMM4,8),%YMM29{%K4}

    (256) 0x41fcde VADDPD	%YMM7,%YMM12,%YMM8

    (256) 0x41fce2 VMULPD	%YMM22,%YMM3,%YMM12

    (256) 0x41fce8 VADDPD	%YMM6,%YMM11,%YMM7

    (256) 0x41fcec VPERM2I128	$0x11,%YMM4,%YMM4,%YMM11

    (256) 0x41fcf2 VGATHERDPD	(%RAX,%XMM11,8),%YMM6{%K5}

    (256) 0x41fcf9 VMOVAPD	-0x70(%RBP),%YMM11

    (256) 0x41fcfe VMULPD	%YMM22,%YMM5,%YMM4

    (256) 0x41fd04 VFMADD231PD	%YMM23,%YMM9,%YMM12

    (256) 0x41fd0a VMOVAPD	%YMM11,%YMM31

    (256) 0x41fd10 VFMADD231PD	%YMM21,%YMM2,%YMM11

    (256) 0x41fd16 VFMADD231PD	%YMM21,%YMM0,%YMM31

    (256) 0x41fd1c VFMADD231PD	%YMM23,%YMM10,%YMM4

    (256) 0x41fd22 KMOVB	%K1,%K6

    (256) 0x41fd26 KMOVB	%K1,%K7

    (256) 0x41fd2a VADDPD	%YMM12,%YMM11,%YMM12

    (256) 0x41fd2f KMOVB	%K1,%K2

    (256) 0x41fd33 VADDPD	%YMM31,%YMM4,%YMM4

    (256) 0x41fd39 VMULPD	%YMM12,%YMM6,%YMM6

    (256) 0x41fd3e KMOVB	%K1,%K3

    (256) 0x41fd42 VMULPD	%YMM29,%YMM4,%YMM4

    (256) 0x41fd48 ADD	$0x40,%R14

    (256) 0x41fd4c VFMADD231PD	%YMM7,%YMM13,%YMM6

    (256) 0x41fd51 VPADDD	-0x110(%RBP),%YMM1,%YMM13

    (256) 0x41fd59 VFMADD231PD	%YMM8,%YMM16,%YMM4

    (256) 0x41fd5f VPERM2I128	$0x11,%YMM13,%YMM13,%YMM11

    (256) 0x41fd65 VGATHERDPD	(%RAX,%XMM13,8),%YMM7{%K6}

    (256) 0x41fd6c VMOVAPD	-0x90(%RBP),%YMM13

    (256) 0x41fd74 VGATHERDPD	(%RAX,%XMM11,8),%YMM12{%K7}

    (256) 0x41fd7b VMULPD	%YMM13,%YMM5,%YMM8

    (256) 0x41fd80 VMULPD	%YMM18,%YMM5,%YMM5

    (256) 0x41fd86 VMULPD	%YMM13,%YMM3,%YMM13

    (256) 0x41fd8b VMULPD	%YMM18,%YMM3,%YMM3

    (256) 0x41fd91 VMOVAPD	-0xb0(%RBP),%YMM11

    (256) 0x41fd99 VFMADD231PD	%YMM30,%YMM10,%YMM8

    (256) 0x41fd9f VFMADD231PD	%YMM19,%YMM10,%YMM5

    (256) 0x41fda5 VMOVAPD	-0xd0(%RBP),%YMM10

    (256) 0x41fdad VMOVAPD	%YMM11,%YMM16

    (256) 0x41fdb3 VFMADD132PD	%YMM0,%YMM20,%YMM16

    (256) 0x41fdb9 VFMADD132PD	%YMM2,%YMM20,%YMM11

    (256) 0x41fdbf VFMADD231PD	%YMM19,%YMM9,%YMM3

    (256) 0x41fdc5 VFMADD132PD	%YMM17,%YMM10,%YMM0

    (256) 0x41fdcb VFMADD132PD	%YMM17,%YMM10,%YMM2

    (256) 0x41fdd1 VFMADD231PD	%YMM30,%YMM9,%YMM13

    (256) 0x41fdd7 VPADDD	0x196ee1(%RIP),%YMM1,%YMM1

    (256) 0x41fddf VADDPD	%YMM16,%YMM8,%YMM8

    (256) 0x41fde5 VADDPD	%YMM5,%YMM0,%YMM0

    (256) 0x41fde9 VADDPD	%YMM2,%YMM3,%YMM2

    (256) 0x41fded VADDPD	%YMM13,%YMM11,%YMM11

    (256) 0x41fdf2 VGATHERDPD	(%RAX,%XMM1,8),%YMM13{%K2}

    (256) 0x41fdf9 VPERM2I128	$0x11,%YMM1,%YMM1,%YMM1

    (256) 0x41fdff VGATHERDPD	(%RAX,%XMM1,8),%YMM31{%K3}

    (256) 0x41fe06 VMULPD	%YMM13,%YMM0,%YMM9

    (256) 0x41fe0b VMULPD	%YMM2,%YMM31,%YMM16

    (256) 0x41fe11 VFMADD132PD	%YMM8,%YMM9,%YMM7

    (256) 0x41fe16 VFMADD231PD	%YMM11,%YMM12,%YMM16

    (256) 0x41fe1c VADDPD	%YMM4,%YMM7,%YMM4

    (256) 0x41fe20 VADDPD	%YMM16,%YMM6,%YMM6

    (256) 0x41fe26 VADDPD	%YMM4,%YMM14,%YMM14

    (256) 0x41fe2a VADDPD	%YMM6,%YMM15,%YMM15

    (256) 0x41fe2e CMP	%R14,%R10

    (256) 0x41fe31 JNE	41fc38

  (254) 0x41fe37 VADDPD	%YMM15,%YMM14,%YMM12

  (254) 0x41fe3c MOV	%EDX,%R8D

  (254) 0x41fe3f AND	$-0x8,%R8D

  (254) 0x41fe43 VEXTRACTF64X2	$0x1,%YMM12,%XMM7

  (254) 0x41fe4a VADDPD	%XMM12,%XMM7,%XMM13

  (254) 0x41fe4f VMOVSD	-0x150(%RBP),%XMM6

  (254) 0x41fe57 VMOVSD	-0x158(%RBP),%XMM4

  (254) 0x41fe5f VUNPCKHPD	%XMM13,%XMM13,%XMM11

  (254) 0x41fe64 VADDPD	%XMM13,%XMM11,%XMM2

  (254) 0x41fe69 VMOVSD	-0x160(%RBP),%XMM5

  (254) 0x41fe71 VMOVSD	-0x168(%RBP),%XMM0

  (254) 0x41fe79 VMOVSD	-0x170(%RBP),%XMM10

  (254) 0x41fe81 VMOVSD	-0x178(%RBP),%XMM3

  (254) 0x41fe89 VMOVSD	-0x180(%RBP),%XMM8

  (254) 0x41fe91 VMOVSD	-0x188(%RBP),%XMM9

  (254) 0x41fe99 VMOVAPD	%XMM2,%XMM29

  (254) 0x41fe9f MOV	%R8D,%R11D

  (254) 0x41fea2 CMP	%EDX,%R8D

  (254) 0x41fea5 JE	420382

  (254) 0x41feab MOV	%EDX,%ECX

  (254) 0x41fead SUB	%R11D,%ECX

  (254) 0x41feb0 LEA	-0x1(%RCX),%R14D

  (254) 0x41feb4 CMP	$0x2,%R14D

  (254) 0x41feb8 JBE	420125

  (254) 0x41febe VMOVQ	%R9,%XMM1

  (254) 0x41fec3 VMOVDDUP	%XMM1,%XMM15

  (254) 0x41fec7 LEA	(%RDI,%R11,8),%R11

  (254) 0x41fecb VMULPD	(%R11),%XMM15,%XMM13

  (254) 0x41fed0 VMULPD	0x10(%R11),%XMM15,%XMM7

  (254) 0x41fed6 VMOVDDUP	%XMM4,%XMM12

  (254) 0x41feda VMOVDDUP	-0x50(%RBP),%XMM27

  (254) 0x41fee1 VMOVDDUP	%XMM6,%XMM30

  (254) 0x41fee7 VRNDSCALEPD	$0xb,%XMM13,%XMM28

  (254) 0x41feee VRNDSCALEPD	$0xb,%XMM7,%XMM22

  (254) 0x41fef5 VINSERTF64X2	$0x1,%XMM7,%YMM13,%YMM2

  (254) 0x41fefc VMOVDDUP	%XMM5,%XMM19

  (254) 0x41ff02 VCVTTPD2DQ	%YMM2,%XMM15

  (254) 0x41ff06 VPSHUFD	$-0x12,%XMM15,%XMM31

  (254) 0x41ff0d VSUBPD	%XMM28,%XMM13,%XMM13

  (254) 0x41ff13 VSUBPD	%XMM22,%XMM7,%XMM7

  (254) 0x41ff19 KMOVB	%K1,%K5

  (254) 0x41ff1d VMULPD	%XMM13,%XMM13,%XMM16

  (254) 0x41ff23 VMULPD	%XMM7,%XMM7,%XMM20

  (254) 0x41ff29 VGATHERDPD	(%RAX,%XMM31,8),%XMM2{%K5}

  (254) 0x41ff30 VMOVDDUP	%XMM10,%XMM11

  (254) 0x41ff35 KMOVB	%K1,%K4

  (254) 0x41ff39 VMULPD	%XMM16,%XMM13,%XMM22

  (254) 0x41ff3f VMULPD	%XMM20,%XMM7,%XMM21

  (254) 0x41ff45 VMULPD	%XMM12,%XMM16,%XMM28

  (254) 0x41ff4b VMULPD	%XMM12,%XMM20,%XMM12

  (254) 0x41ff51 VGATHERDPD	(%RAX,%XMM15,8),%XMM1{%K4}

  (254) 0x41ff58 VMOVDDUP	-0x118(%RBP),%XMM25

  (254) 0x41ff5f VMOVDDUP	%XMM0,%XMM26

  (254) 0x41ff65 VFMADD231PD	%XMM30,%XMM22,%XMM28

  (254) 0x41ff6b VFMADD231PD	%XMM30,%XMM21,%XMM12

  (254) 0x41ff71 VMOVAPD	%XMM13,%XMM30

  (254) 0x41ff77 VFMADD132PD	%XMM19,%XMM27,%XMM30

  (254) 0x41ff7d VFMADD132PD	%XMM7,%XMM27,%XMM19

  (254) 0x41ff83 VMOVDDUP	%XMM3,%XMM18

  (254) 0x41ff89 VPADDD	-0x1a0(%RBP),%XMM15,%XMM31

  (254) 0x41ff90 VMOVDDUP	%XMM8,%XMM14

  (254) 0x41ff95 VADDPD	%XMM28,%XMM30,%XMM27

  (254) 0x41ff9b VADDPD	%XMM19,%XMM12,%XMM12

  (254) 0x41ffa1 VPSHUFD	$-0x12,%XMM31,%XMM28

  (254) 0x41ffa8 KMOVB	%K1,%K7

  (254) 0x41ffac VMULPD	%XMM2,%XMM12,%XMM2

  (254) 0x41ffb0 VGATHERDPD	(%RAX,%XMM28,8),%XMM30{%K7}

  (254) 0x41ffb7 VMOVDDUP	-0x120(%RBP),%XMM24

  (254) 0x41ffbe VMOVDDUP	-0x130(%RBP),%XMM23

  (254) 0x41ffc5 VMOVDDUP	-0x128(%RBP),%XMM17

  (254) 0x41ffcc VFMADD231PD	%XMM27,%XMM1,%XMM2

  (254) 0x41ffd2 VMULPD	%XMM11,%XMM16,%XMM27

  (254) 0x41ffd8 VMULPD	%XMM11,%XMM20,%XMM11

  (254) 0x41ffde KMOVB	%K1,%K6

  (254) 0x41ffe2 KMOVB	%K1,%K2

  (254) 0x41ffe6 VGATHERDPD	(%RAX,%XMM31,8),%XMM19{%K6}

  (254) 0x41ffed VFMADD231PD	%XMM26,%XMM22,%XMM27

  (254) 0x41fff3 VFMADD231PD	%XMM26,%XMM21,%XMM11

  (254) 0x41fff9 VMOVAPD	%XMM13,%XMM26

  (254) 0x41ffff VFMADD132PD	%XMM18,%XMM25,%XMM26

  (254) 0x420005 VFMADD132PD	%XMM7,%XMM25,%XMM18

  (254) 0x42000b KMOVB	%K1,%K4

  (254) 0x42000f KMOVB	%K1,%K3

  (254) 0x420013 KMOVB	%K1,%K5

  (254) 0x420017 VADDPD	%XMM26,%XMM27,%XMM25

  (254) 0x42001d VADDPD	%XMM18,%XMM11,%XMM1

  (254) 0x420023 VPADDD	0x196c73(%RIP),%XMM15,%XMM18

  (254) 0x42002d VPADDD	0x196c8b(%RIP),%XMM15,%XMM15

  (254) 0x420035 VMULPD	%XMM30,%XMM1,%XMM12

  (254) 0x42003b VMULPD	%XMM14,%XMM16,%XMM30

  (254) 0x420041 VMULPD	%XMM14,%XMM20,%XMM14

  (254) 0x420047 VGATHERDPD	(%RAX,%XMM18,8),%XMM31{%K2}

  (254) 0x42004e VPSHUFD	$-0x12,%XMM15,%XMM11

  (254) 0x420054 VFMADD231PD	%XMM25,%XMM19,%XMM12

  (254) 0x42005a VFMADD231PD	%XMM24,%XMM22,%XMM30

  (254) 0x420060 VFMADD231PD	%XMM24,%XMM21,%XMM14

  (254) 0x420066 VMOVAPD	%XMM13,%XMM24

  (254) 0x42006c VFMADD132PD	%XMM17,%XMM23,%XMM24

  (254) 0x420072 VFMADD132PD	%XMM7,%XMM23,%XMM17

  (254) 0x420078 VPSHUFD	$-0x12,%XMM18,%XMM19

  (254) 0x42007f VGATHERDPD	(%RAX,%XMM19,8),%XMM28{%K3}

  (254) 0x420086 VADDPD	%XMM24,%XMM30,%XMM23

  (254) 0x42008c VADDPD	%XMM17,%XMM14,%XMM1

  (254) 0x420092 VMOVDDUP	-0x140(%RBP),%XMM14

  (254) 0x42009a VFMADD132PD	%XMM31,%XMM2,%XMM23

  (254) 0x4200a0 VMULPD	%XMM14,%XMM16,%XMM16

  (254) 0x4200a6 VGATHERDPD	(%RAX,%XMM15,8),%XMM2{%K4}

  (254) 0x4200ad VMULPD	%XMM14,%XMM20,%XMM15

  (254) 0x4200b3 VMOVDDUP	-0x138(%RBP),%XMM17

  (254) 0x4200ba VMOVDDUP	-0x148(%RBP),%XMM20

  (254) 0x4200c1 VFMADD231PD	%XMM17,%XMM22,%XMM16

  (254) 0x4200c7 VMOVDDUP	%XMM9,%XMM22

  (254) 0x4200cd VFMADD231PD	%XMM17,%XMM21,%XMM15

  (254) 0x4200d3 VFMADD132PD	%XMM20,%XMM22,%XMM13

  (254) 0x4200d9 VFMADD132PD	%XMM20,%XMM22,%XMM7

  (254) 0x4200df VFMADD132PD	%XMM28,%XMM12,%XMM1

  (254) 0x4200e5 VGATHERDPD	(%RAX,%XMM11,8),%XMM12{%K5}

  (254) 0x4200ec VADDPD	%XMM13,%XMM16,%XMM21

  (254) 0x4200f2 VADDPD	%XMM7,%XMM15,%XMM7

  (254) 0x4200f6 VFMADD132PD	%XMM21,%XMM23,%XMM2

  (254) 0x4200fc VFMADD132PD	%XMM7,%XMM1,%XMM12

  (254) 0x420101 VADDPD	%XMM12,%XMM2,%XMM13

  (254) 0x420106 VUNPCKHPD	%XMM13,%XMM13,%XMM1

  (254) 0x42010b VADDPD	%XMM13,%XMM1,%XMM2

  (254) 0x420110 VADDSD	%XMM2,%XMM29,%XMM29

  (254) 0x420116 TEST	$0x3,%CL

  (254) 0x420119 JE	420382

  (254) 0x42011f AND	$-0x4,%ECX

  (254) 0x420122 ADD	%ECX,%R8D

  (254) 0x420125 MOVSXD	%R8D,%R10

  (254) 0x420128 VMOVQ	%R9,%XMM11

  (254) 0x42012d VMULSD	(%RDI,%R10,8),%XMM11,%XMM12

  (254) 0x420133 VMOVSD	-0x50(%RBP),%XMM2

  (254) 0x420138 VMOVSD	-0x118(%RBP),%XMM26

  (254) 0x42013f VMOVAPD	%XMM2,%XMM1

  (254) 0x420143 VMOVSD	-0x120(%RBP),%XMM25

  (254) 0x42014a VRNDSCALESD	$0xb,%XMM12,%XMM12,%XMM14

  (254) 0x420151 VSUBSD	%XMM14,%XMM12,%XMM7

  (254) 0x420156 VCVTTSD2SI	%XMM12,%R14D

  (254) 0x42015b VMOVSD	-0x130(%RBP),%XMM18

  (254) 0x420162 VMULSD	%XMM7,%XMM7,%XMM13

  (254) 0x420166 VFMADD231SD	%XMM5,%XMM7,%XMM1

  (254) 0x42016b MOVSXD	%R14D,%R11

  (254) 0x42016e VMOVSD	-0x140(%RBP),%XMM27

  (254) 0x420175 VMOVSD	-0x138(%RBP),%XMM31

  (254) 0x42017c VMULSD	%XMM13,%XMM7,%XMM14

  (254) 0x420181 VMULSD	%XMM4,%XMM13,%XMM15

  (254) 0x420185 VMULSD	%XMM10,%XMM13,%XMM11

  (254) 0x42018a VMOVSD	-0x148(%RBP),%XMM19

  (254) 0x420191 LEA	(,%R10,8),%RCX

  (254) 0x420199 LEA	0x1(%R8),%R10D

  (254) 0x42019d VFMADD231SD	%XMM14,%XMM6,%XMM15

  (254) 0x4201a2 VFMADD231SD	%XMM14,%XMM0,%XMM11

  (254) 0x4201a7 VADDSD	%XMM1,%XMM15,%XMM12

  (254) 0x4201ab VMOVAPD	%XMM26,%XMM15

  (254) 0x4201b1 VFMADD231SD	%XMM3,%XMM7,%XMM15

  (254) 0x4201b6 VFMADD132SD	(%RAX,%R11,8),%XMM29,%XMM12

  (254) 0x4201bd VMULSD	%XMM8,%XMM13,%XMM29

  (254) 0x4201c3 VMOVSD	-0x128(%RBP),%XMM1

  (254) 0x4201cb VMULSD	%XMM27,%XMM13,%XMM13

  (254) 0x4201d1 VADDSD	%XMM15,%XMM11,%XMM11

  (254) 0x4201d6 VMOVAPD	%XMM1,%XMM15

  (254) 0x4201da VFMADD231SD	%XMM25,%XMM14,%XMM29

  (254) 0x4201e0 VFMADD132SD	%XMM7,%XMM18,%XMM15

  (254) 0x4201e6 VFMADD132SD	%XMM31,%XMM13,%XMM14

  (254) 0x4201ec VFMADD132SD	%XMM19,%XMM9,%XMM7

  (254) 0x4201f2 VADDSD	%XMM29,%XMM15,%XMM15

  (254) 0x4201f8 VADDSD	%XMM14,%XMM7,%XMM7

  (254) 0x4201fd VMULSD	0x10(%RAX,%R11,8),%XMM15,%XMM15

  (254) 0x420204 VFMADD132SD	0x18(%RAX,%R11,8),%XMM12,%XMM7

  (254) 0x42020b VFMADD132SD	0x8(%RAX,%R11,8),%XMM15,%XMM11

  (254) 0x420212 VADDSD	%XMM7,%XMM11,%XMM29

  (254) 0x420218 CMP	%EDX,%R10D

  (254) 0x42021b JGE	420382

  (254) 0x420221 VMOVQ	%R9,%XMM14

  (254) 0x420226 VMULSD	0x8(%RDI,%RCX,1),%XMM14,%XMM15

  (254) 0x42022c VMOVAPD	%XMM2,%XMM14

  (254) 0x420230 ADD	$0x2,%R8D

  (254) 0x420234 VRNDSCALESD	$0xb,%XMM15,%XMM15,%XMM12

  (254) 0x42023b VSUBSD	%XMM12,%XMM15,%XMM7

  (254) 0x420240 VCVTTSD2SI	%XMM15,%R14D

  (254) 0x420245 VMULSD	%XMM7,%XMM7,%XMM11

  (254) 0x420249 VFMADD231SD	%XMM7,%XMM5,%XMM14

  (254) 0x42024e MOVSXD	%R14D,%R11

  (254) 0x420251 VMULSD	%XMM7,%XMM11,%XMM12

  (254) 0x420255 VMULSD	%XMM11,%XMM4,%XMM13

  (254) 0x42025a VMULSD	%XMM11,%XMM10,%XMM15

  (254) 0x42025f VMULSD	%XMM11,%XMM8,%XMM28

  (254) 0x420265 VMULSD	%XMM27,%XMM11,%XMM11

  (254) 0x42026b VFMADD231SD	%XMM12,%XMM6,%XMM13

  (254) 0x420270 VFMADD231SD	%XMM12,%XMM0,%XMM15

  (254) 0x420275 VFMADD231SD	%XMM25,%XMM12,%XMM28

  (254) 0x42027b VFMADD132SD	%XMM31,%XMM11,%XMM12

  (254) 0x420281 VADDSD	%XMM13,%XMM14,%XMM14

  (254) 0x420286 VMOVAPD	%XMM26,%XMM13

  (254) 0x42028c VFMADD231SD	%XMM7,%XMM3,%XMM13

  (254) 0x420291 VFMADD132SD	(%RAX,%R11,8),%XMM29,%XMM14

  (254) 0x420298 VADDSD	%XMM15,%XMM13,%XMM13

  (254) 0x42029d VMOVAPD	%XMM1,%XMM15

  (254) 0x4202a1 VFMADD132SD	%XMM7,%XMM18,%XMM15

  (254) 0x4202a7 VFMADD132SD	%XMM19,%XMM9,%XMM7

  (254) 0x4202ad VADDSD	%XMM28,%XMM15,%XMM15

  (254) 0x4202b3 VADDSD	%XMM12,%XMM7,%XMM7

  (254) 0x4202b8 VMULSD	0x10(%RAX,%R11,8),%XMM15,%XMM15

  (254) 0x4202bf VFMADD132SD	0x18(%RAX,%R11,8),%XMM14,%XMM7

  (254) 0x4202c6 VFMADD132SD	0x8(%RAX,%R11,8),%XMM15,%XMM13

  (254) 0x4202cd VADDSD	%XMM7,%XMM13,%XMM29

  (254) 0x4202d3 CMP	%EDX,%R8D

  (254) 0x4202d6 JGE	420382

  (254) 0x4202dc VMOVQ	%R9,%XMM12

  (254) 0x4202e1 VMULSD	0x10(%RDI,%RCX,1),%XMM12,%XMM14

  (254) 0x4202e7 VMOVAPD	%XMM19,%XMM12

  (254) 0x4202ed VRNDSCALESD	$0xb,%XMM14,%XMM14,%XMM13

  (254) 0x4202f4 VSUBSD	%XMM13,%XMM14,%XMM15

  (254) 0x4202f9 VCVTTSD2SI	%XMM14,%EDI

  (254) 0x4202fe VMULSD	%XMM15,%XMM15,%XMM11

  (254) 0x420303 VFMADD132SD	%XMM15,%XMM26,%XMM3

  (254) 0x420309 VFMADD132SD	%XMM15,%XMM2,%XMM5

  (254) 0x42030e VFMADD132SD	%XMM15,%XMM18,%XMM1

  (254) 0x420314 VFMADD132SD	%XMM15,%XMM9,%XMM12

  (254) 0x420319 VMULSD	%XMM11,%XMM15,%XMM7

  (254) 0x42031e VMULSD	%XMM11,%XMM10,%XMM10

  (254) 0x420323 VMULSD	%XMM11,%XMM4,%XMM4

  (254) 0x420328 VMULSD	%XMM11,%XMM8,%XMM8

  (254) 0x42032d MOVSXD	%EDI,%RDX

  (254) 0x420330 VFMADD132SD	%XMM7,%XMM10,%XMM0

  (254) 0x420335 VFMADD132SD	%XMM7,%XMM4,%XMM6

  (254) 0x42033a VADDSD	%XMM3,%XMM0,%XMM3

  (254) 0x42033e VMOVAPD	%XMM25,%XMM0

  (254) 0x420344 VFMADD132SD	%XMM7,%XMM8,%XMM0

  (254) 0x420349 VADDSD	%XMM6,%XMM5,%XMM5

  (254) 0x42034d VFMADD132SD	(%RAX,%RDX,8),%XMM29,%XMM5

  (254) 0x420354 VADDSD	%XMM0,%XMM1,%XMM6

  (254) 0x420358 VMULSD	%XMM27,%XMM11,%XMM1

  (254) 0x42035e VMULSD	0x10(%RAX,%RDX,8),%XMM6,%XMM2

  (254) 0x420364 VFMADD132SD	%XMM31,%XMM1,%XMM7

  (254) 0x42036a VFMADD132SD	0x8(%RAX,%RDX,8),%XMM2,%XMM3

  (254) 0x420371 VADDSD	%XMM7,%XMM12,%XMM9

  (254) 0x420375 VFMADD132SD	0x18(%RAX,%RDX,8),%XMM5,%XMM9

  (254) 0x42037c VADDSD	%XMM3,%XMM9,%XMM29

  (254) 0x420382 VADDSD	-0x48(%RBP),%XMM29,%XMM14

  (254) 0x420389 VMOVSD	%XMM14,-0x48(%RBP)

  (254) 0x42038e ADD	$0x4,%RSI

  (254) 0x420392 CMP	%RSI,%R12

  (254) 0x420395 JNE	41f7f8

(252) 0x42039b VMOVQ	%R15,%XMM13

(252) 0x4203a0 VSUBSD	-0x48(%RBP),%XMM13,%XMM7

(252) 0x4203a5 MOV	-0x1a8(%RBP),%R15

(252) 0x4203ac MOV	-0x1b0(%RBP),%R14

(252) 0x4203b3 VZEROUPPER

(252) 0x4203b6 VMOVAPD	%XMM7,%XMM0

(252) 0x4203ba CALL	4040b0 <exp@plt>

(252) 0x4203bf MOV	(%R14),%RSI

(252) 0x4203c2 MOV	0x8(%R14),%R12

(252) 0x4203c6 VMOVSD	%XMM0,(%RSI,%R15,8)

(252) 0x4203cc SUB	%RSI,%R12

(252) 0x4203cf INC	%R15

(252) 0x4203d2 SAR	$0x3,%R12

(252) 0x4203d6 CMP	%R12,%R15

(252) 0x4203d9 JB	41f748

0x4203df ADD	$0x1a0,%RSP

0x4203e6 POP	%RBX

0x4203e7 POP	%R9

0x4203e9 POP	%R12

0x4203eb POP	%R13

0x4203ed POP	%R14

0x4203ef POP	%R15

0x4203f1 POP	%RBP

0x4203f2 LEA	-0x8(%R9),%RSP

0x4203f6 RET

0x4203f7 NOPW	(%RAX,%RAX,1)

(252) 0x420400 MOV	0x90(%RBX),%R13D

(252) 0x420407 TEST	%R13D,%R13D

(252) 0x42040a JLE	4203b6

(252) 0x42040c MOV	0xa0(%RBX),%RAX

(252) 0x420413 MOVSXD	%R13D,%RDI

(252) 0x420416 MOV	0x18(%RAX),%R10

(252) 0x42041a MOV	0x1c8(%RBX),%RCX

(252) 0x420421 LEA	(%R10,%RDI,4),%R11

(252) 0x420425 AND	$0x1,%EDI

(252) 0x420428 MOV	-0x190(%RBP),%RAX

(252) 0x42042f VXORPD	%XMM8,%XMM8,%XMM8

(252) 0x420434 LEA	-0x38(%RBP),%R12

(252) 0x420438 JE	420584

(252) 0x42043e MOVSXD	(%R10),%RDX

(252) 0x420441 MOV	(%RCX,%RDX,8),%R13

(252) 0x420445 TEST	%R13,%R13

(252) 0x420448 JE	42056c

(252) 0x42044e MOV	-0x190(%RBP),%R8

(252) 0x420455 VMOVSD	(%R8),%XMM0

(252) 0x42045a VCOMISD	0x8(%R13),%XMM0

(252) 0x420460 JAE	42056c

(252) 0x420466 VMULSD	0x238(%R13),%XMM0,%XMM0

(252) 0x42046f MOV	%R12,%RDI

(252) 0x420472 MOV	%R11,-0xf0(%RBP)

(252) 0x420479 MOV	%R10,-0xb0(%RBP)

(252) 0x420480 MOV	%RCX,-0x90(%RBP)

(252) 0x420487 VMOVSD	%XMM7,-0xd0(%RBP)

(252) 0x42048f VMOVSD	%XMM8,-0x70(%RBP)

(252) 0x420494 CALL	404340 <modf@plt>

(252) 0x420499 VMULSD	%XMM0,%XMM0,%XMM4

(252) 0x42049d VMOVSD	0x28(%R13),%XMM1

(252) 0x4204a3 VMOVSD	0x68(%R13),%XMM13

(252) 0x4204a9 VFMADD213SD	0x30(%R13),%XMM0,%XMM1

(252) 0x4204af VFMADD213SD	0x70(%R13),%XMM0,%XMM13

(252) 0x4204b5 VMULSD	%XMM0,%XMM4,%XMM6

(252) 0x4204b9 VMULSD	0x20(%R13),%XMM4,%XMM3

(252) 0x4204bf VMULSD	0x60(%R13),%XMM4,%XMM12

(252) 0x4204c5 VMULSD	0x40(%R13),%XMM4,%XMM9

(252) 0x4204cb VMULSD	0x80(%R13),%XMM4,%XMM5

(252) 0x4204d4 VCVTTSD2SI	-0x38(%RBP),%ESI

(252) 0x4204d9 VFMADD231SD	0x18(%R13),%XMM6,%XMM3

(252) 0x4204df VFMADD231SD	0x58(%R13),%XMM6,%XMM12

(252) 0x4204e5 VMOVSD	0x48(%R13),%XMM10

(252) 0x4204eb VMOVSD	0x90(%R13),%XMM2

(252) 0x4204f4 VFMADD231SD	0x38(%R13),%XMM6,%XMM9

(252) 0x4204fa VFMADD213SD	0x50(%R13),%XMM0,%XMM10

(252) 0x420500 VFMADD132SD	0x78(%R13),%XMM5,%XMM6

(252) 0x420506 VFMADD132SD	0x88(%R13),%XMM2,%XMM0

(252) 0x42050f VADDSD	%XMM1,%XMM3,%XMM8

(252) 0x420513 VADDSD	%XMM13,%XMM12,%XMM14

(252) 0x420518 MOV	0x218(%R13),%RCX

(252) 0x42051f VMOVSD	-0x70(%RBP),%XMM7

(252) 0x420524 MOVSXD	%ESI,%R9

(252) 0x420527 VFMADD132SD	(%RCX,%R9,8),%XMM7,%XMM8

(252) 0x42052d VMULSD	0x10(%RCX,%R9,8),%XMM14,%XMM15

(252) 0x420534 VADDSD	%XMM10,%XMM9,%XMM11

(252) 0x420539 VADDSD	%XMM6,%XMM0,%XMM0

(252) 0x42053d MOV	-0xf0(%RBP),%R11

(252) 0x420544 VMOVSD	-0xd0(%RBP),%XMM7

(252) 0x42054c VFMADD132SD	0x8(%RCX,%R9,8),%XMM15,%XMM11

(252) 0x420553 VFMADD132SD	0x18(%RCX,%R9,8),%XMM8,%XMM0

(252) 0x42055a MOV	-0xb0(%RBP),%R10

(252) 0x420561 MOV	-0x90(%RBP),%RCX

(252) 0x420568 VADDSD	%XMM0,%XMM11,%XMM8

(252) 0x42056c MOV	-0x190(%RBP),%RAX

(252) 0x420573 ADD	$0x4,%R10

(252) 0x420577 ADD	$0x8,%RAX

(252) 0x42057b CMP	%R11,%R10

(252) 0x42057e JE	4207d7

(252) 0x420584 MOV	%R15,-0xd0(%RBP)

(252) 0x42058b MOV	%RBX,-0x110(%RBP)

(252) 0x420592 MOV	%R14,-0x48(%RBP)

(252) 0x420596 MOV	%R10,%R15

(252) 0x420599 VMOVSD	%XMM7,-0xf0(%RBP)

(252) 0x4205a1 MOV	%R11,%R13

(252) 0x4205a4 MOV	%RAX,%RBX

(252) 0x4205a7 MOV	%RCX,%R14

  (253) 0x4205aa MOVSXD	(%R15),%RDI

  (253) 0x4205ad MOV	(%R14,%RDI,8),%RDX

  (253) 0x4205b1 TEST	%RDX,%RDX

  (253) 0x4205b4 JE	42069b

  (253) 0x4205ba VMOVSD	(%RBX),%XMM4

  (253) 0x4205be VCOMISD	0x8(%RDX),%XMM4

  (253) 0x4205c3 JAE	42069b

  (253) 0x4205c9 VMULSD	0x238(%RDX),%XMM4,%XMM0

  (253) 0x4205d1 MOV	%R12,%RDI

  (253) 0x4205d4 VMOVSD	%XMM8,-0x90(%RBP)

  (253) 0x4205dc MOV	%RDX,-0x70(%RBP)

  (253) 0x4205e0 CALL	404340 <modf@plt>

  (253) 0x4205e5 VMULSD	%XMM0,%XMM0,%XMM3

  (253) 0x4205e9 MOV	-0x70(%RBP),%RSI

  (253) 0x4205ed VCVTTSD2SI	-0x38(%RBP),%R9D

  (253) 0x4205f2 VMOVSD	0x28(%RSI),%XMM1

  (253) 0x4205f7 VMOVSD	0x68(%RSI),%XMM14

  (253) 0x4205fc VMULSD	%XMM0,%XMM3,%XMM8

  (253) 0x420600 VMULSD	0x20(%RSI),%XMM3,%XMM6

  (253) 0x420605 VMULSD	0x60(%RSI),%XMM3,%XMM13

  (253) 0x42060a VFMADD213SD	0x30(%RSI),%XMM0,%XMM1

  (253) 0x420610 VFMADD213SD	0x70(%RSI),%XMM0,%XMM14

  (253) 0x420616 VMULSD	0x40(%RSI),%XMM3,%XMM10

  (253) 0x42061b VFMADD231SD	0x18(%RSI),%XMM8,%XMM6

  (253) 0x420621 VFMADD231SD	0x58(%RSI),%XMM8,%XMM13

  (253) 0x420627 VMULSD	0x80(%RSI),%XMM3,%XMM2

  (253) 0x42062f VMOVSD	0x48(%RSI),%XMM11

  (253) 0x420634 VMOVSD	0x90(%RSI),%XMM4

  (253) 0x42063c VFMADD231SD	0x38(%RSI),%XMM8,%XMM10

  (253) 0x420642 VFMADD213SD	0x50(%RSI),%XMM0,%XMM11

  (253) 0x420648 VFMADD132SD	0x78(%RSI),%XMM2,%XMM8

  (253) 0x42064e VFMADD132SD	0x88(%RSI),%XMM4,%XMM0

  (253) 0x420657 VADDSD	%XMM1,%XMM6,%XMM7

  (253) 0x42065b VADDSD	%XMM14,%XMM13,%XMM15

  (253) 0x420660 MOV	0x218(%RSI),%R8

  (253) 0x420667 VMOVSD	-0x90(%RBP),%XMM9

  (253) 0x42066f MOVSXD	%R9D,%R11

  (253) 0x420672 VFMADD132SD	(%R8,%R11,8),%XMM9,%XMM7

  (253) 0x420678 VMULSD	0x10(%R8,%R11,8),%XMM15,%XMM5

  (253) 0x42067f VADDSD	%XMM8,%XMM0,%XMM0

  (253) 0x420684 VADDSD	%XMM11,%XMM10,%XMM12

  (253) 0x420689 VFMADD132SD	0x18(%R8,%R11,8),%XMM7,%XMM0

  (253) 0x420690 VFMADD132SD	0x8(%R8,%R11,8),%XMM5,%XMM12

  (253) 0x420697 VADDSD	%XMM0,%XMM12,%XMM8

  (253) 0x42069b LEA	0x4(%R15),%RDI

  (253) 0x42069f MOVSXD	0x4(%R15),%R15

  (253) 0x4206a3 LEA	0x8(%RBX),%RAX

  (253) 0x4206a7 MOV	(%R14,%R15,8),%R15

  (253) 0x4206ab TEST	%R15,%R15

  (253) 0x4206ae JE	4207ac

  (253) 0x4206b4 VMOVSD	0x8(%RBX),%XMM3

  (253) 0x4206b9 VCOMISD	0x8(%R15),%XMM3

  (253) 0x4206bf JAE	4207ac

  (253) 0x4206c5 VMULSD	0x238(%R15),%XMM3,%XMM0

  (253) 0x4206ce MOV	%RDI,-0x70(%RBP)

  (253) 0x4206d2 MOV	%R12,%RDI

  (253) 0x4206d5 MOV	%RAX,-0x90(%RBP)

  (253) 0x4206dc VMOVSD	%XMM8,-0xb0(%RBP)

  (253) 0x4206e4 CALL	404340 <modf@plt>

  (253) 0x4206e9 VMULSD	%XMM0,%XMM0,%XMM8

  (253) 0x4206ed VMOVSD	0x28(%R15),%XMM1

  (253) 0x4206f3 VMOVSD	0x68(%R15),%XMM15

  (253) 0x4206f9 VFMADD213SD	0x30(%R15),%XMM0,%XMM1

  (253) 0x4206ff VFMADD213SD	0x70(%R15),%XMM0,%XMM15

  (253) 0x420705 VMULSD	%XMM0,%XMM8,%XMM7

  (253) 0x420709 VMULSD	0x20(%R15),%XMM8,%XMM6

  (253) 0x42070f VMULSD	0x60(%R15),%XMM8,%XMM14

  (253) 0x420715 VMULSD	0x40(%R15),%XMM8,%XMM11

  (253) 0x42071b VMULSD	0x80(%R15),%XMM8,%XMM4

  (253) 0x420724 VCVTTSD2SI	-0x38(%RBP),%R10D

  (253) 0x420729 VFMADD231SD	0x18(%R15),%XMM7,%XMM6

  (253) 0x42072f VFMADD231SD	0x58(%R15),%XMM7,%XMM14

  (253) 0x420735 VMOVSD	0x48(%R15),%XMM12

  (253) 0x42073b VMOVSD	0x90(%R15),%XMM3

  (253) 0x420744 VFMADD231SD	0x38(%R15),%XMM7,%XMM11

  (253) 0x42074a VFMADD213SD	0x50(%R15),%XMM0,%XMM12

  (253) 0x420750 VFMADD132SD	0x78(%R15),%XMM4,%XMM7

  (253) 0x420756 VFMADD132SD	0x88(%R15),%XMM3,%XMM0

  (253) 0x42075f VADDSD	%XMM1,%XMM6,%XMM9

  (253) 0x420763 VADDSD	%XMM15,%XMM14,%XMM5

  (253) 0x420768 MOV	0x218(%R15),%RBX

  (253) 0x42076f VMOVSD	-0xb0(%RBP),%XMM10

  (253) 0x420777 MOVSXD	%R10D,%RCX

  (253) 0x42077a VFMADD132SD	(%RBX,%RCX,8),%XMM10,%XMM9

  (253) 0x420780 VMULSD	0x10(%RBX,%RCX,8),%XMM5,%XMM2

  (253) 0x420786 VADDSD	%XMM12,%XMM11,%XMM13

  (253) 0x42078b VADDSD	%XMM7,%XMM0,%XMM0

  (253) 0x42078f MOV	-0x90(%RBP),%RAX

  (253) 0x420796 MOV	-0x70(%RBP),%RDI

  (253) 0x42079a VFMADD132SD	0x8(%RBX,%RCX,8),%XMM2,%XMM13

  (253) 0x4207a1 VFMADD132SD	0x18(%RBX,%RCX,8),%XMM9,%XMM0

  (253) 0x4207a8 VADDSD	%XMM0,%XMM13,%XMM8

  (253) 0x4207ac LEA	0x4(%RDI),%R15

  (253) 0x4207b0 LEA	0x8(%RAX),%RBX

  (253) 0x4207b4 CMP	%R13,%R15

  (253) 0x4207b7 JNE	4205aa

(252) 0x4207bd MOV	-0xd0(%RBP),%R15

(252) 0x4207c4 VMOVSD	-0xf0(%RBP),%XMM7

(252) 0x4207cc MOV	-0x110(%RBP),%RBX

(252) 0x4207d3 MOV	-0x48(%RBP),%R14

(252) 0x4207d7 VSUBSD	%XMM8,%XMM7,%XMM7

(252) 0x4207dc JMP	4203b6

  (254) 0x4207e1 XOR	%R11D,%R11D

  (254) 0x4207e4 VXORPD	%XMM29,%XMM29,%XMM29

  (254) 0x4207ea XOR	%R8D,%R8D

  (254) 0x4207ed JMP	41feab

0x4207f2 NOPW	%CS:(%RAX,%RAX,1)

0x4207fc NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►96.64+	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:992	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►2.49+	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:992	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	OneBodyJastrowRef.h:132-155
Module	exec

The function is defined in:

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:993,1128-1131,1147-1150
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/shared_ptr_base.h:1667
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/OneBodyJastrowRef.h:132-155
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:166-173,179-182,231-260
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229,249
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.17 to 1.17 cycles (5.29x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 6.17 to 0.45 cycles (13.71x speedup).

Details

12% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

PUSH: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/OneBodyJastrowRef.h:132

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 24 bytes.

General properties

nb instructions	36
nb uops	37
loop length	135
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.17 cycles
front end	6.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.60	1.60	3.67	3.67	5.00	1.60	1.60	5.00	5.00	5.00	1.60	3.67
cycles	1.60	1.60	3.67	3.67	5.00	1.60	1.60	5.00	5.00	5.00	1.60	3.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.17
Dispatch	5.00
Overall L1	6.17

Vectorization ratios

all	12%
load	0%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.17 cycles. At this rate:

2% of peak load performance is reached (3.89 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (3.89 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.17 to 5.00 cycles (1.23x speedup).

ASM code

In the binary file, the address of the function is: 41f6f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LEA 0x8(%RSP),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
PUSHQ -0x8(%R10)	2	0	0	0.33	0.33	0.50	0	0	0.50	0.50	0.50	0	0.33	5-12	0.62	N/A
MOV $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VPBROADCASTD %EAX,%XMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R10	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x1a0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x8(%RDX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RSI,-0x1b8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVDQA %XMM5,-0x1a0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
CMP %RCX,(%RDX)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 4203df <_ZN16miniqmcreference17OneBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0xcef>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x1a0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
LEA -0x8(%R9),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	OneBodyJastrowRef.h:132-155
Module	exec

The function is defined in:

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:993,1128-1131,1147-1150
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/shared_ptr_base.h:1667
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/OneBodyJastrowRef.h:132-155
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:166-173,179-182,231-260
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229,249
/home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.17 to 1.17 cycles (5.29x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

12% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

PUSH: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-773-5521/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/OneBodyJastrowRef.h:132

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 24 bytes.

General properties

nb instructions	36
nb uops	37
loop length	135
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.17 cycles
front end	6.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.60	1.60	3.67	3.67	5.00	1.60	1.60	5.00	5.00	5.00	1.60	3.67
cycles	1.60	1.60	3.67	3.67	5.00	1.60	1.60	5.00	5.00	5.00	1.60	3.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.17
Dispatch	5.00
Overall L1	6.17

Vectorization ratios

all	12%
load	0%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.17 cycles. At this rate:

2% of peak load performance is reached (3.89 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (3.89 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 41f6f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LEA 0x8(%RSP),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
PUSHQ -0x8(%R10)	2	0	0	0.33	0.33	0.50	0	0	0.50	0.50	0.50	0	0.33	5-12	0.62	N/A
MOV $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VPBROADCASTD %EAX,%XMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R10	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x1a0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x8(%RDX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RSI,-0x1b8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVDQA %XMM5,-0x1a0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
CMP %RCX,(%RDX)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 4203df <_ZN16miniqmcreference17OneBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0xcef>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x1a0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
LEA -0x8(%R9),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::OneBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)–	0.04	0.03
▼Loop 252 - OneBodyJastrowRef.h:134-155 - exec–	0.00	0.01
▼Loop 254 - OneBodyJastrowRef.h:143-146 - exec–	0.00	0.01
○Loop 255 - BsplineFunctor.h:236-241 - exec	0.03	0.03
○Loop 256 - BsplineFunctor.h:246-260 - exec	0.00	0.00
○Loop 253 - OneBodyJastrowRef.h:151-155 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code