	*************************************************
	*                                               *
	*          ONE-View report generation           *
	*                                               *
	*************************************************

[MAQAO] Info: Experiment configuration summary is available adding -dbg=1 in command line

* [MAQAO] Warning: Experiment directory /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/run/oneview_runs/compilers/aocc_6/oneview_results_1786695043 already exists and is reused.
           It can be replaced using --replace in the command line.
[MAQAO] Info: 
[MAQAO] Info: START THE APPLICATION PROFILING
[MAQAO] Info: -> RUNNING THE PROFILER...
[MAQAO] Info:   LPROF has already been run
[MAQAO] Info: STOP THE APPLICATION PROFILING
[MAQAO] Info: 
[MAQAO] Info: START FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: STOP FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: 
[MAQAO] Info: START THE REPORT GENERATION
[MAQAO] Info: -> ONE-VIEW EXPERIMENT DIRECTORY: /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/run/oneview_runs/compilers/aocc_6/oneview_results_1786695043


+====================================================================================================================+
+                                                    1  -  GLOBAL                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             1.1  -  Experiment Summary                                             +
+--------------------------------------------------------------------------------------------------------------------+

  Application:			/beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/run/binaries/aocc_6/exec
  Timestamp:			2026-08-14 10:10:43
  Universal Timestamp:		1786695043
  Experiment Type:		MPI; OpenMP; Throughput; 
  Machine:			gmz12.benchmarkcenter.megware.com
  Architecture:			x86_64
  Micro Architecture:		ZEN_V5
  Model Name:			AMD EPYC 9655 96-Core Processor
  Cache Size:			1024 KB
  Number of Cores:		96
  OS Version:			Linux 5.14.0-687.29.1.el9_8.x86_64 #1 SMP PREEMPT_DYNAMIC Thu Jul 23 16:18:48 EDT 2026
  Compilation Options:		
		exec: AMD clang version 17.0.6 (CLANG: AOCC_5.1.0-Build#1994 2025_12_23) /cluster/comp/aocc/5.1.0/bin/clang-17 --driver-mode=g++ -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/src -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/aocc_6/kripke-build/include -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/tpl/raja/include -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/aocc_6/kripke-build/raja/include -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/tpl/raja/tpl/camp/include -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/aocc_6/kripke-build/raja/tpl/camp/include -O3 -O2 -march=znver5 -ffast-math -g -fno-omit-frame-pointer -fcf-protection=none -nopie -grecord-command-line -O3 -D NDEBUG -std=c++17 -fPIC -fopenmp=libomp -MD -MT CMakeFiles/kripke.dir/beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp.o -MF CMakeFiles/kripke.dir/beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp.o.d -o CMakeFiles/kripke.dir/beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp.o -c /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp -I /cluster/hpcx/2.23/ompi5-aocc-mt/include -I /cluster/hpcx/2.23/ompi5-aocc-mt/include/openmpi 
  Number of processes observed:	1
  Number of threads observed:	191
  MAQAO version:		2026.1.0
  MAQAO build:			6d1be1d51c1e63266254997eb301734a7264775d::20260810-150026




+--------------------------------------------------------------------------------------------------------------------+
+                                               1.2  -  Global Metrics                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Total Time:				55.98 s
  Max (Thread Active Time):		55.63 s
  Average Active Time:			55.47 s
  Activity Ratio:			99.7 %
  Average number of active threads:	189.267
  Affinity Stability:			99.9 %
  Time spent in analyzed loops:		71.0 %
  Time spent in analyzed innermost loops: 44.3 %
  Time spent in user code:		71.0 %
  Compilation Options Score:		100
  Array Access Efficiency:		74.7 %

   Potential Speedups
  ----------------------------------------------------
  Perfect Flow Complexity:		1.00
  Perfect OpenMP/MPI/Pthread/TBB:	1.07
  Perfect OpenMP/MPI/Pthread/TBB + Load Distribution:	1.39
  If No Scalar Integer:
      Potential Speedup:		1.16
      Nb Loops to get 80%:		1
  If FP Vectorized:
      Potential Speedup:		1.33
      Nb Loops to get 80%:		2
  If Fully Vectorized:
      Potential Speedup:		1.80
      Nb Loops to get 80%:		3
  If Only FP Arithmetic:
      Potential Speedup:		1.38
      Nb Loops to get 80%:		2




+--------------------------------------------------------------------------------------------------------------------+
+                                             1.3  -  Potential Speedups                                             +
+--------------------------------------------------------------------------------------------------------------------+

  If No Scalar Integer:
      Number of loops   | 1      | 2      | 4      | 5      | 8      | 
      Cumulated Speedup | 1.1572 | 1.1574 | 1.1574 | 1.1574 | 1.1574 | 
  Top 5 loops:
    exec - 812:	1.1572
    exec - 1013:	1.1574
    exec - 1356:	1.1574
    exec - 1135:	1.1574
    exec - 814:	1.1574

  If FP Vectorized:
      Number of loops   | 1      | 2      | 4      | 5      | 8      | 
      Cumulated Speedup | 1.2154 | 1.3088 | 1.3258 | 1.3258 | 1.3258 | 
  Top 5 loops:
    exec - 812:	1.2154
    exec - 814:	1.3088
    exec - 1356:	1.3258
    exec - 1135:	1.3258
    exec - 1014:	1.3258

  If Fully Vectorized:
      Number of loops   | 1      | 2      | 4      | 5      | 8      | 
      Cumulated Speedup | 1.2963 | 1.5530 | 1.7942 | 1.7948 | 1.7951 | 
  Top 5 loops:
    exec - 812:	1.2963
    exec - 679:	1.553
    exec - 814:	1.7493
    exec - 1356:	1.7942
    exec - 1013:	1.7948

  If Only FP Arithmetic:
      Number of loops   | 1      | 2      | 4      | 5      | 8      | 
      Cumulated Speedup | 1.2188 | 1.3810 | 1.3814 | 1.3814 | 1.3814 | 
  Top 5 loops:
    exec - 812:	1.2188
    exec - 1014:	1.381
    exec - 1013:	1.3813
    exec - 811:	1.3814
    exec - 1356:	1.3814



+====================================================================================================================+
+                                                   2  -  SUMMARY                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             2.1  -  EXPERIMENT QUALITY                                             +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Application profile is long enough (55.63 s)
To have good quality measurements, it is advised that the application profiling time is greater than 10 seconds.

  [3 / 3] Most of time spent in analyzed modules comes from functions with source/debug info
-g option gives access to debugging informations, such are source locations.

  [3 / 3] Most of time spent in analyzed modules (100.00%) comes from functions compiled with architecture specialization option
-march=znver5


  [3 / 3] Most of time spent in analyzed modules comes from functions with compilation options informations and
-fno-omit-frame-pointer is present
-fno-omit-frame-pointer improves the accuracy of callchains found during the application profiling.

  [3 / 3] Optimization level option is correctly used


  [3 / 3] Host configuration allows retrieval of all necessary metrics.


  [2 / 2] Application is correctly profiled ("Others" category represents 0.00 % of the execution time)
To have a representative profiling, it is advised that the category "Others" represents less than 20% of the execution
time in order to analyze as much as possible of the user code

  [1 / 1] Lstopo present. The Topology lstopo report will be generated.



+--------------------------------------------------------------------------------------------------------------------+
+                                                2.2  -  CODE QUALITY                                                +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Enough time of the experiment time spent in analyzed loops (71.03%)
If the time spent in analyzed loops is less than 30%, standard loop optimizations will have a limited impact on
application performances.

  [4 / 4] Threads activity is good
On average, more than 99.09% of observed threads are actually active 

  [4 / 4] CPU activity is good
CPU cores are active 99.67% of time

  [4 / 4] Loop profile is not flat
At least one loop coverage is greater than 4% (26.69%), representing an hotspot for the application

  [4 / 4] Enough time of the experiment time spent in analyzed innermost loops (44.30%)
If the time spent in analyzed innermost loops is less than 15%, standard innermost loop optimizations such as
vectorisation will have a limited impact on application performances.

  [4 / 4] Affinity is good (99.91%)
Threads are not migrating to CPU cores: probably successfully pinned

  [3 / 3] Less than 10% (0.00%) is spend in BLAS1 operations
It could be more efficient to inline by hand BLAS1 operations

  [0 / 3] Too many functions do not use all threads
Functions running on a reduced number of threads (typically sequential code) cover at least 10% of application
walltime (54.27%). Check both "Max Inclusive Time Over Threads" and "Nb Threads" in Functions or Loops tabs and
consider parallelizing sequential regions or improving parallelization of regions running on a reduced number of
threads

  [3 / 3] Cumulative Outermost/In between loops coverage (26.73%) lower than cumulative innermost loop coverage (44.30%)
Having cumulative Outermost/In between loops coverage greater than cumulative innermost loop coverage will make loop
optimization more complex

  [2 / 2] Less than 10% (0.00%) is spend in BLAS2 operations
BLAS2 calls usually could make a poor cache usage and could benefit from inlining.

  [2 / 2] Less than 10% (0.00%) is spend in Libm/SVML (special functions)



+--------------------------------------------------------------------------------------------------------------------+
+                                               2.3  -  LOOPS OVERVIEW                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Top 5 loops:
   + exec - 812 :
     analysis: Execution Time: 26 % - Vectorization Ratio: 34.76 % - Vector Length Use: 18.63 %
     Loop Computation Issues: 2
        [2] [SA] Presence of a large number of scalar integer instructions - Simplify loop structure, perform loop
            splitting or perform unroll and jam. This issue costs 2 points.
     Control Flow Issues: 6
        [4] [SA] Several paths (4 paths) - Simplify control structure or force the compiler to use masked
            instructions. There are 4 issues ( = paths) costing 1 point each.
        [2] [SA] Non innermost loop (InBetween) - Collapse loop with innermost ones. This issue costs 2 points.
     Data Access Issues: 4
        [2] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, SHUFFLE/PERM, BROADCAST)
            - Simplify data access and try to get stride 1 access. There are 2 issues (= instructions) costing 1
            point each.
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.
     Vectorization Roadblocks: 6
        [4] [SA] Several paths (4 paths) - Simplify control structure or force the compiler to use masked
            instructions. There are 4 issues ( = paths) costing 1 point each.
        [2] [SA] Non innermost loop (InBetween) - Collapse loop with innermost ones. This issue costs 2 points.
     Inefficient Vectorization: 2
        [2] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, SHUFFLE/PERM, BROADCAST)
            - Simplify data access and try to get stride 1 access. There are 2 issues (= instructions) costing 1
            point each.

   + exec - 1014:
     analysis: Execution Time: 19 % - Vectorization Ratio: 100.00 % - Vector Length Use: 100.00 %
     Data Access Issues: 0
        [0] [SA] Inefficient vectorization: more than 10% of the vector loads instructions are unaligned - When
            allocating arrays, don’t forget to align them. There are 0 issues ( = arrays) costing 2 points each

   + exec - 679 :
     analysis: Execution Time: 14 % - Vectorization Ratio: 0.00 % - Vector Length Use: 12.50 %
     Loop Computation Issues: 5
        [5] [SA] Peel/tail loop, considered having a low iteration count - Perform full unroll. Force compiler to use
            masked instructions. This issue costs 5 points.
     Control Flow Issues: 5
        [5] [SA] Peel/tail loop, considered having a low iteration count - Perform full unroll. Force compiler to use
            masked instructions. This issue costs 5 points.

   + exec - 814 :
     analysis: Execution Time: 8 % - Vectorization Ratio: 0.00 % - Vector Length Use: 12.50 %
     Loop Computation Issues: 5
        [5] [SA] Peel/tail loop, considered having a low iteration count - Perform full unroll. Force compiler to use
            masked instructions. This issue costs 5 points.
     Control Flow Issues: 5
        [5] [SA] Peel/tail loop, considered having a low iteration count - Perform full unroll. Force compiler to use
            masked instructions. This issue costs 5 points.
     Data Access Issues: 2
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.
     Vectorization Roadblocks: 2
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.

   + exec - 1356:
     analysis: Execution Time: 1 % - Vectorization Ratio: 16.13 % - Vector Length Use: 14.52 %
     Loop Computation Issues: 12
        [12] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 3
            issues (= instructions) costing 4 points each.
     Data Access Issues: 37
        [18] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 9 issues ( = data accesses) costing 2 point
            each.
        [12] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 3 issues ( = indirect data accesses) costing 4 point each.
        [5] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, SHUFFLE/PERM) - Simplify
            data access and try to get stride 1 access. There are 5 issues (= instructions) costing 1 point each.
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.
     Vectorization Roadblocks: 30
        [18] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 9 issues ( = data accesses) costing 2 point
            each.
        [12] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 3 issues ( = indirect data accesses) costing 4 point each.
     Inefficient Vectorization: 5
        [5] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, SHUFFLE/PERM) - Simplify
            data access and try to get stride 1 access. There are 5 issues (= instructions) costing 1 point each.



+====================================================================================================================+
+                                                 3  -  APPLICATION                                                  +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                               3.1  -  Categorization                                               +
+--------------------------------------------------------------------------------------------------------------------+

   Category | IO     | Exe    | System  | Others  | Memory | String | MPI   | TBB   | OMP   | Pthread | Math  |
  ----------+--------+--------+---------+---------+--------+--------+-------+-------+-------+---------+-------+
   Time (%) | 0.00   | 71.05  | 0.99    | 0.00    | 0.00   | 0.02   | 0.00  | 0.00  | 27.93 | 0.00    | 0.00  |




+--------------------------------------------------------------------------------------------------------------------+
+                                          3.2  -  Function Based Profiling                                          +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Functions              | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 5                         | 96.51                     | 96.51                     |
   4% to 8%                   | 0                         | 0.00                      | 96.51                     |
   2% to 4%                   | 0                         | 0.00                      | 96.51                     |
   1% to 2%                   | 1                         | 1.72                      | 98.23                     |
   0.5% to 1%                 | 1                         | 0.88                      | 99.11                     |
   0.25% to 0.5%              | 1                         | 0.49                      | 99.61                     |
   0.125% to 0.25%            | 1                         | 0.25                      | 99.86                     |
   < 0.125%                   | 8                         | 0.14                      | 99.99                     |




+--------------------------------------------------------------------------------------------------------------------+
+                                            3.3  -  Loop Based Profiling                                            +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Loops                  | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 3                         | 42.10                     | 42.10                     |
   4% to 8%                   | 0                         | 0.00                      | 42.10                     |
   2% to 4%                   | 0                         | 0.00                      | 42.10                     |
   1% to 2%                   | 1                         | 1.71                      | 43.81                     |
   0.5% to 1%                 | 0                         | 0.00                      | 43.81                     |
   0.25% to 0.5%              | 1                         | 0.49                      | 44.30                     |
   0.125% to 0.25%            | 0                         | 0.00                      | 44.30                     |
   < 0.125%                   | 0                         | 0.00                      | 44.30                     |


+====================================================================================================================+
+                                                  4  -  FUNCTIONS                                                   +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                              4.1  -  Top 10 Functions                                              +
+--------------------------------------------------------------------------------------------------------------------+

   Function                                               | Module              | Coverage (%)   | Time (s)       |
  --------------------------------------------------------+---------------------+----------------+----------------+
   std::enable_if<all_of<camp::concepts::metalib::nega... | exec                | 34.97          | 19.40          |
   std::enable_if<all_of<camp::concepts::metalib::nega... | exec                | 19.29          | 10.70          |
   __kmp_hardware_timestamp                               | libomp.so           | 15.24          | 8.45           |
   std::enable_if<all_of<camp::concepts::metalib::nega... | exec                | 14.58          | 8.09           |
   __kmp_hyper_barrier_release(barrier_type, kmp_info*... | libomp.so           | 12.44          | 6.94           |
   std::enable_if<all_of<camp::concepts::metalib::nega... | exec                | 1.72           | 0.95           |
   unknown_kernel_region                                  | kernel              | 0.88           | 0.49           |
   std::enable_if<all_of<camp::concepts::metalib::nega... | exec                | 0.49           | 0.27           |
   __kmp_hyper_barrier_gather(barrier_type, kmp_info*,... | libomp.so           | 0.25           | 0.55           |
   __GI___sched_yield                                     | libc.so.6           | 0.11           | 0.07           |


+====================================================================================================================+
+                                                    5  -  LOOPS                                                     +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                5.1  -  Top 10 Loops                                                +
+--------------------------------------------------------------------------------------------------------------------+

   Loop Id        | Module              | Source Location                                        | Coverage (%)   |
  ----------------+---------------------+--------------------------------------------------------+----------------+
   812            | exec                | For.hpp:142-142,Operators.hpp:369-369,Iterators.hpp... | 26.69          |
   1014           | exec                | For.hpp:142-142,LPlusTimes.cpp:57-57                   | 19.27          |
   679            | exec                | For.hpp:142-142,LTimes.cpp:62-62                       | 14.57          |
   814            | exec                | Operators.hpp:369-369,Layout.hpp:191-191,Scattering... | 8.26           |
   1356           | exec                | For.hpp:142-142,SweepSubdomain.cpp:88-90,SweepSubdo... | 1.71           |
   1135           | exec                | For.hpp:142-142,Operators.hpp:369-369,Population.cp... | 0.49           |
   1013           | exec                | For.hpp:142-142                                        | 0.02           |
   811            | exec                | For.hpp:142-142,Collapse.hpp:131-131                   | 0.01           |
   681            | exec                | For.hpp:142-142                                        | 0.00           |
   1355           | exec                | For.hpp:142-142                                        | 0.00           |





+====================================================================================================================+
+                                                     6  -  CQA                                                      +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                   6.1  -  Loops                                                    +
+--------------------------------------------------------------------------------------------------------------------+





      6.1.1  -  Loop 812 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:142
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:369
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:191
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/TypedViewBase.hpp:216
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp:291
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/src/Kripke/Kernel/Scattering.cpp:88-97
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/IndexValue.hpp:87,221


Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.1.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

2% of peak computational performance is used (1.00 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 2.00 to 1.25 cycles (1.60x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.1.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is probably not vectorized.
Only 15% of vector register length is used (average across all SSE/AVX instructions).
By vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.25 cycles (8.00x speedup).

Details
Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.1.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by:
 - reading data from caches/RAM (load units are a bottleneck)
 - writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 2.00 to 1.75 cycles (1.14x speedup).


Workaround
 - Read less array elements
 - Write less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop





      6.1.1.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 1 FMA (fused multiply-add) operations.




      6.1.1.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).



      6.1.1.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 2 FP arithmetical operations:
 - 1: addition or subtraction (all inside FMA instructions)
 - 1: multiply (all inside FMA instructions)
The binary loop is loading 52 bytes (6 double precision FP elements).
The binary loop is storing 8 bytes (1 double precision FP elements).


      6.1.1.1.7  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.




      6.1.1.2  -  Path 2
  ----------------------------------------------------------------------------------------------------------

1% of peak computational performance is used (0.48 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.2.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 4.13 to 1.50 cycles (2.75x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.1.2.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is probably not vectorized.
Only 14% of vector register length is used (average across all SSE/AVX instructions).
By vectorizing your loop, you can lower the cost of an iteration from 4.13 to 0.52 cycles (8.00x speedup).

Details
Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.1.2.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.1.2.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 1 FMA (fused multiply-add) operations.




      6.1.1.2.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - CMOVG: 1 occurrences<<list_path_2_complex_1>>



      6.1.1.2.6  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 3 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.1.2.7  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).



      6.1.1.2.8  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 2 FP arithmetical operations:
 - 1: addition or subtraction (all inside FMA instructions)
 - 1: multiply (all inside FMA instructions)
The binary loop is loading 108 bytes (13 double precision FP elements).
The binary loop is storing 8 bytes (1 double precision FP elements).


      6.1.1.2.9  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.




      6.1.1.3  -  Path 3
  ----------------------------------------------------------------------------------------------------------

4% of peak computational performance is used (2.27 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.3.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 7.50 to 3.75 cycles (2.00x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.1.3.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
Only 22% of vector register length is used (average across all SSE/AVX instructions).


Details
52% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 0% of SSE/AVX loads are used in vector version.
 - 0% of SSE/AVX stores are used in vector version.
 - 80% of SSE/AVX addition or subtraction instructions are used in vector version.
 - 0% of SSE/AVX fused multiply-add instructions are used in vector version.
 - 58% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.1.3.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.1.3.4  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512


      6.1.1.3.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 1 FMA (fused multiply-add) operations.




      6.1.1.3.6  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - CMOVG: 1 occurrences<<list_path_3_complex_1>>
 - VPBROADCASTQ: 1 occurrences<<list_path_3_complex_2>>



      6.1.1.3.7  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 5 occurrence(s)
 - Irregular (variable stride) or indirect: 1 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.1.3.8  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 1 suboptimal vector unaligned load/store instructions.


Details
 - VEXTRACTF128: 1 occurrences<<list_path_3_vec_align_1>>


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.1.3.9  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).
3 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.1.3.10  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 17 FP arithmetical operations:
 - 16: addition or subtraction (1 inside FMA instructions)
 - 1: multiply (all inside FMA instructions)
The binary loop is loading 156 bytes (19 double precision FP elements).
The binary loop is storing 8 bytes (1 double precision FP elements).


      6.1.1.3.11  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.




      6.1.1.4  -  Path 4
  ----------------------------------------------------------------------------------------------------------

4% of peak computational performance is used (2.34 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.4.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 7.25 to 3.75 cycles (1.93x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.1.4.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
Only 22% of vector register length is used (average across all SSE/AVX instructions).


Details
52% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 0% of SSE/AVX loads are used in vector version.
 - 0% of SSE/AVX stores are used in vector version.
 - 80% of SSE/AVX addition or subtraction instructions are used in vector version.
 - 0% of SSE/AVX fused multiply-add instructions are used in vector version.
 - 58% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.1.4.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.1.4.4  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512


      6.1.1.4.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 1 FMA (fused multiply-add) operations.




      6.1.1.4.6  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - CMOVG: 1 occurrences<<list_path_4_complex_1>>
 - VPBROADCASTQ: 1 occurrences<<list_path_4_complex_2>>



      6.1.1.4.7  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 2 occurrence(s)
 - Irregular (variable stride) or indirect: 1 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.1.4.8  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 1 suboptimal vector unaligned load/store instructions.


Details
 - VEXTRACTF128: 1 occurrences<<list_path_4_vec_align_1>>


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.1.4.9  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).
3 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.1.4.10  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 17 FP arithmetical operations:
 - 16: addition or subtraction (1 inside FMA instructions)
 - 1: multiply (all inside FMA instructions)
The binary loop is loading 156 bytes (19 double precision FP elements).
The binary loop is storing 8 bytes (1 double precision FP elements).


      6.1.1.4.11  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.







      6.1.2  -  Loop 1014 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:142
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp:57


It is main loop of related source loop which is unrolled by 32 (including vectorization).

      6.1.2.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

33% of peak computational performance is used (16.00 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.2.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is fully vectorized, using full register length.


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).



      6.1.2.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.2.1.3  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 32 FMA (fused multiply-add) operations.




      6.1.2.1.4  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VMOVUPD: 4 occurrences<<list_path_1_complex_1>>



      6.1.2.1.5  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 8 optimal vector unaligned load/store instructions.


Details
 - VMOVUPD: 8 occurrences<<list_path_1_vec_align_1>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.2.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

4 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.2.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 64 FP arithmetical operations:
 - 32: addition or subtraction (all inside FMA instructions)
 - 32: multiply (all inside FMA instructions)
The binary loop is loading 512 bytes (64 double precision FP elements).
The binary loop is storing 256 bytes (32 double precision FP elements).


      6.1.2.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.3  -  Loop 679 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:142
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/src/Kripke/Kernel/LTimes.cpp:62


It is peel/tail loop of related source loop which is unrolled by 32 (including vectorization).

      6.1.3.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

4% of peak computational performance is used (2.00 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.3.1.1  -  Unrolling/vectorization cost
  ----------------------------------------------------------------------------------------------------------

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details
The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround
 - recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
 - hardcode most frequent values of loop bounds by adding specialized paths.:
  *  For instance, replace for (i=0; i<n; i++) foo(i) with:
switch (n) {
  case (4): for (i=0; i<4; i++) foo(i); break;
  case (6): for (i=0; i<6; i++) foo(i); break;
  default : for (i=0; i<n; i++) foo(i); break;
}



      6.1.3.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
8 data elements could be processed at once in vector registers.
<<image_1x64_512>>

Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).



      6.1.3.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by:
 - reading data from caches/RAM (load units are a bottleneck)
 - writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 1.00 to 0.75 cycles (1.33x speedup).


Workaround
 - Read less array elements
 - Write less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop





      6.1.3.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 1 FMA (fused multiply-add) operations.




      6.1.3.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).



      6.1.3.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 2 FP arithmetical operations:
 - 1: addition or subtraction (all inside FMA instructions)
 - 1: multiply (all inside FMA instructions)
The binary loop is loading 24 bytes (3 double precision FP elements).
The binary loop is storing 8 bytes (1 double precision FP elements).


      6.1.3.1.7  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.







      6.1.4  -  Loop 814 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:369
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:191
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/src/Kripke/Kernel/Scattering.cpp:91-95
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/IndexValue.hpp:87,221


It is peel/tail loop of related source loop which is unrolled by 16 (including vectorization).

      6.1.4.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

1% of peak computational performance is used (0.50 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.4.1.1  -  Unrolling/vectorization cost
  ----------------------------------------------------------------------------------------------------------

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details
The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround
 - recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
 - hardcode most frequent values of loop bounds by adding specialized paths.:
  *  For instance, replace for (i=0; i<n; i++) foo(i) with:
switch (n) {
  case (4): for (i=0; i<4; i++) foo(i); break;
  case (6): for (i=0; i<6; i++) foo(i); break;
  default : for (i=0; i<n; i++) foo(i); break;
}



      6.1.4.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
8 data elements could be processed at once in vector registers.
<<image_1x64_512>>

Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).



      6.1.4.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.4.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 1 FMA (fused multiply-add) operations.




      6.1.4.1.5  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 1 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.4.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).



      6.1.4.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 2 FP arithmetical operations:
 - 1: addition or subtraction (all inside FMA instructions)
 - 1: multiply (all inside FMA instructions)
The binary loop is loading 24 bytes (3 double precision FP elements).


      6.1.4.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.5  -  Loop 1356 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:142
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp:88-90,96-106


The related source loop is multi-versionned.

      6.1.5.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

3% of peak computational performance is used (1.67 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.5.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
Only 14% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 12.00 to 2.00 cycles (6.00x speedup).

Details
16% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 0% of SSE/AVX loads are used in vector version.
 - 0% of SSE/AVX stores are used in vector version.
 - 9% of SSE/AVX addition or subtraction instructions are used in vector version.
 - 0% of SSE/AVX fused multiply-add instructions are used in vector version.
 - 33% of SSE/AVX divide and square root instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.5.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 8.00 cycles (1.50x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.5.1.3  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 7.75 cycles (1.55x speedup).


      6.1.5.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 1 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.5.1.5  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 9 occurrence(s)
 - Irregular (variable stride) or indirect: 3 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.5.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

13 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).



      6.1.5.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 20 FP arithmetical operations:
 - 13: addition or subtraction (1 inside FMA instructions)
 - 3: multiply (1 inside FMA instructions)
 - 4: divide
The binary loop is loading 216 bytes (27 double precision FP elements).
The binary loop is storing 40 bytes (5 double precision FP elements).


      6.1.5.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.


      6.1.5.1.9  -  Unroll opportunity
  ----------------------------------------------------------------------------------------------------------

Loop is potentially data access bound.

Workaround
Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)







      6.1.6  -  Loop 1135 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:142
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:369
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/src/Kripke/Kernel/Population.cpp:58


It is main loop of related source loop which is unrolled by 32 (including vectorization).

      6.1.6.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

50% of peak computational performance is used (24.00 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.6.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is fully vectorized, using full register length.


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).



      6.1.6.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 4.00 to 2.00 cycles (2.00x speedup).


Workaround
Reduce the number of FP multiply/FMA instructions




      6.1.6.1.3  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 32 FMA (fused multiply-add) operations.




      6.1.6.1.4  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.6.1.5  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 96 FP arithmetical operations:
 - 32: addition or subtraction (all inside FMA instructions)
 - 64: multiply (32 inside FMA instructions)
The binary loop is loading 512 bytes (64 double precision FP elements).


      6.1.6.1.6  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.







      6.1.7  -  Loop 1013 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:142
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp:57


Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:142.

Warnings:
 - Non-innermost loop: analyzing only self part (ignoring child loops).
 - Ignoring paths for analysis
 - Too many paths. Rerun with max-paths=9
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 9 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.7.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.00 out of 96.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.7.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 10.25 to 2.67 cycles (3.84x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.7.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
8 data elements could be processed at once in vector registers.
By vectorizing your loop, you can lower the cost of an iteration from 10.25 to 1.28 cycles (8.00x speedup).

Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.7.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.



No data for this section



      6.1.7.1.4  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.


      6.1.7.1.5  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is loading 176 bytes.







      6.1.8  -  Loop 811 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:142
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:369
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:131
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:191
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/TypedViewBase.hpp:216
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp:291
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/src/Kripke/Kernel/Scattering.cpp:88-97
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/IndexValue.hpp:87,221


Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.8.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

Warnings:
This path is accessible from 4 CFG paths (including child blocks)

0% of peak computational performance is used (0.00 out of 96.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.8.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
Only 11% of vector register length is used (average across all SSE/AVX instructions).
By vectorizing your loop, you can lower the cost of an iteration from 2.25 to 0.22 cycles (10.29x speedup).

Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.8.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by:
 - reading data from caches/RAM (load units are a bottleneck)
 - writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 2.25 to 1.88 cycles (1.20x speedup).


Workaround
 - Read less array elements
 - Write less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop




No data for this section



      6.1.8.1.3  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.


      6.1.8.1.4  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is loading 48 bytes.
The binary loop is storing 24 bytes.





[MAQAO] Info: STOP THE REPORT GENERATION
[MAQAO] Info: 
[MAQAO] Info: If your application produces files, they can be found in directory "/beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9338/intel/Kripke/run/oneview_runs/compilers/aocc_6/oneview_run_1786695043"
[MAQAO] Info: 
