| Loop Id: 2422 | Module: exec | Source: For.hpp:137-137 [...] | Coverage: 1.39% |
|---|
| Loop Id: 2422 | Module: exec | Source: For.hpp:137-137 [...] | Coverage: 1.39% |
|---|
0x4cec9f MOV -0x48(%RBP),%R10 [11] |
0x4ceca3 VMOVSD (%R8),%XMM14 [15] |
0x4ceca8 VMOVSD (%R15),%XMM11 [5] |
0x4cecad VMOVSD (%RBX),%XMM24 [6] |
0x4cecb3 VMOVSD (%R14),%XMM1 [4] |
0x4cecb8 VADDSD %XMM11,%XMM11,%XMM2 |
0x4cecbd VADDSD %XMM24,%XMM24,%XMM23 |
0x4cecc3 VDIVSD (%R9),%XMM2,%XMM0 [17] |
0x4cecc8 VDIVSD (%R11),%XMM23,%XMM29 [9] |
0x4cecce VADDSD (%RDI),%XMM0,%XMM11 [8] |
0x4cecd2 VADDSD %XMM1,%XMM1,%XMM4 |
0x4cecd6 ADD %R12,%R9 |
0x4cecd9 ADD %R13,%R8 |
0x4cecdc ADD %R13,%RDI |
0x4cecdf VDIVSD (%R10),%XMM4,%XMM8 [1] |
0x4cece4 VMULSD (%RAX),%XMM8,%XMM5 [3] |
0x4cece8 VADDSD %XMM8,%XMM29,%XMM30 |
0x4cecee VFMADD231SD (%RSI),%XMM0,%XMM5 [12] |
0x4cecf3 VFMADD132SD (%RDX),%XMM14,%XMM29 [19] |
0x4cecf9 VADDSD %XMM30,%XMM11,%XMM2 |
0x4cecff VADDSD %XMM29,%XMM5,%XMM6 |
0x4ced05 VDIVSD %XMM2,%XMM6,%XMM0 |
0x4ced09 VMOVSD %XMM0,(%RCX) [14] |
0x4ced0d VMOVAPD %XMM0,%XMM1 |
0x4ced11 VMOVAPD %XMM0,%XMM4 |
0x4ced15 VFMSUB213SD (%RSI),%XMM3,%XMM1 [12] |
0x4ced1a ADD %R13,%RCX |
0x4ced1d VMOVSD %XMM1,(%RSI) [12] |
0x4ced21 VFMSUB213SD (%RDX),%XMM3,%XMM4 [19] |
0x4ced26 VMOVSD %XMM4,(%RDX) [19] |
0x4ced2a ADD %R12,%RDX |
0x4ced2d VFMSUB213SD (%RAX),%XMM3,%XMM0 [3] |
0x4ced32 VMOVSD %XMM0,(%RAX) [3] |
0x4ced36 ADD %R12,%RAX |
0x4ced39 VMOVSD (%R15),%XMM8 [5] |
0x4ced3e VMOVSD (%R14),%XMM6 [4] |
0x4ced43 VMOVSD (%R8),%XMM0 [10] |
0x4ced48 VADDSD %XMM8,%XMM8,%XMM14 |
0x4ced4d VMOVSD (%RBX),%XMM24 [6] |
0x4ced53 VDIVSD (%R9),%XMM14,%XMM5 [16] |
0x4ced58 VADDSD %XMM6,%XMM6,%XMM11 |
0x4ced5c VADDSD (%RDI),%XMM5,%XMM8 [7] |
0x4ced60 VDIVSD (%R10),%XMM11,%XMM2 [1] |
0x4ced65 VADDSD %XMM24,%XMM24,%XMM23 |
0x4ced6b VMULSD (%RAX),%XMM2,%XMM1 [2] |
0x4ced6f VDIVSD (%R11),%XMM23,%XMM29 [9] |
0x4ced75 VFMADD231SD (%RSI),%XMM5,%XMM1 [12] |
0x4ced7a VADDSD %XMM2,%XMM29,%XMM30 |
0x4ced80 VFMADD132SD (%RDX),%XMM0,%XMM29 [18] |
0x4ced86 VADDSD %XMM30,%XMM8,%XMM14 |
0x4ced8c VADDSD %XMM29,%XMM1,%XMM4 |
0x4ced92 VDIVSD %XMM14,%XMM4,%XMM5 |
0x4ced97 VMOVSD %XMM5,(%RCX) [13] |
0x4ced9b VMOVAPD %XMM5,%XMM6 |
0x4ced9f VFMSUB213SD (%RSI),%XMM3,%XMM6 [12] |
0x4ceda4 VMOVSD %XMM6,(%RSI) [12] |
0x4ceda8 ADDQ $0x2,-0x38(%RBP) [11] |
0x4cedad MOV -0x38(%RBP),%R10 [11] |
0x4cedb1 VMOVAPD %XMM5,%XMM11 |
0x4cedb5 ADD %R12,%R9 |
0x4cedb8 VFMSUB213SD (%RDX),%XMM3,%XMM11 [18] |
0x4cedbd ADD %R13,%R8 |
0x4cedc0 VMOVSD %XMM11,(%RDX) [18] |
0x4cedc4 ADD %R13,%RDI |
0x4cedc7 VFMSUB213SD (%RAX),%XMM3,%XMM5 [2] |
0x4cedcc ADD %R12,%RDX |
0x4cedcf VMOVSD %XMM5,(%RAX) [2] |
0x4cedd3 ADD %R13,%RCX |
0x4cedd6 ADD %R12,%RAX |
0x4cedd9 CMP %R10,-0x40(%RBP) [11] |
0x4ceddd JG 4cec9f |
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp: 137 - 137 |
-------------------------------------------------------------------------------- |
137: for (decltype(distance_it) i = 0; i < distance_it; ++i) { |
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp: 88 - 106 |
-------------------------------------------------------------------------------- |
88: double xcos_dxi = 2.0 * xcos(d) / dx(i); |
89: double ycos_dyj = 2.0 * ycos(d) / dy(j); |
90: double zcos_dzk = 2.0 * zcos(d) / dz(k); |
91: |
92: Zone z(zone_layout(*k, *j, *i)); |
93: |
94: /* Calculate new zonal flux */ |
95: double psi_d_g_z = (rhs(d,g,z) |
96: + psi_lf(d, g, j, k) * xcos_dxi |
97: + psi_fr(d, g, i, k) * ycos_dyj |
98: + psi_bo(d, g, i, j) * zcos_dzk) |
99: / (xcos_dxi + ycos_dyj + zcos_dzk + sigt(g, z)); |
100: |
101: psi(d, g, z) = psi_d_g_z; |
102: |
103: /* Apply diamond-difference relationships */ |
104: psi_lf(d, g, j, k) = 2.0 * psi_d_g_z - psi_lf(d, g, j, k); |
105: psi_fr(d, g, i, k) = 2.0 * psi_d_g_z - psi_fr(d, g, i, k); |
106: psi_bo(d, g, i, j) = 2.0 * psi_d_g_z - psi_bo(d, g, i, j); |
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/TypedViewBase.hpp: 188 - 188 |
-------------------------------------------------------------------------------- |
188: return_type make_return(LayoutType const &layout, PointerType const &data, Args const &... args){ |
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp: 331 - 331 |
-------------------------------------------------------------------------------- |
331: RAJA_HOST_DEVICE constexpr Ret operator()(const Arg1& lhs, |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►97.36+ | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
| ○ | start_thread | libc.so.6 | |
| ○ | __GI___clone3 | libc.so.6 | |
| ►2.35+ | GOMP_parallel | libgomp.h:982 | libgomp.so.1.0.0 |
| ○ | void Kripke::DispatchHelper<Kr[...] | plugins.hpp:71 | exec |
| ○ | Kripke::Kernel::sweepSubdomain[...] | ArchLayout.h:155 | exec |
| ○ | Kripke::SweepSolver(Kripke::Co[...] | SweepSolver.cpp:78 | exec |
| ○ | Kripke::SteadyStateSolver(Krip[...] | alloc_traits.h:941 | exec |
| ○ | main | new_allocator.h:88 | exec |
| ○ | __libc_start_call_main | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | _start | kripke.cpp:129 | exec |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 3.42 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 3.20 |
| Bottlenecks | P10, P11, |
| Function | void RAJA::internal::StatementExecutor |
| Source | For.hpp:137-137,SweepSubdomain.cpp:88-106,TypedViewBase.hpp:188-188,Operators.hpp:331-331 |
| Source loop unroll info | multi-versionned |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 32.00 |
| CQA cycles if no scalar integer | 32.00 |
| CQA cycles if FP arith vectorized | 9.34 |
| CQA cycles if fully vectorized | 4.00 |
| Front-end cycles | 8.75 |
| P0 cycles | 2.33 |
| P1 cycles | 2.33 |
| P2 cycles | 2.33 |
| P3 cycles | 2.33 |
| P4 cycles | 2.33 |
| P5 cycles | 2.33 |
| P6 cycles | 10.00 |
| P7 cycles | 10.00 |
| P8 cycles | 10.00 |
| P9 cycles | 10.00 |
| P10 cycles | 10.00 |
| P11 cycles | 10.00 |
| P12 cycles | 7.00 |
| P13 cycles | 7.00 |
| P14 cycles | 4.00 |
| P15 cycles | 4.00 |
| DIV/SQRT cycles | 32.00 |
| Inter-iter dependencies cycles | 2 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 71.00 |
| Nb uops | 70.00 |
| Nb loads | 32.00 |
| Nb stores | 9.00 |
| Nb stack references | 3.00 |
| FLOP/cycle | 1.38 |
| Nb FLOP add-sub | 14.00 |
| Nb FLOP mul | 2.00 |
| Nb FLOP fma | 10.00 |
| Nb FLOP div | 8.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 10.25 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 256.00 |
| Bytes stored | 72.00 |
| Stride 0 | 6.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 13.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 7.27 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 100.00 |
| Vector-efficiency ratio all | 13.41 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | 12.50 |
| Vector-efficiency ratio div_sqrt | 12.50 |
| Vector-efficiency ratio other | 25.00 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 3.42 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 3.20 |
| Bottlenecks | P10, P11, |
| Function | void RAJA::internal::StatementExecutor |
| Source | For.hpp:137-137,SweepSubdomain.cpp:88-106,TypedViewBase.hpp:188-188,Operators.hpp:331-331 |
| Source loop unroll info | multi-versionned |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 32.00 |
| CQA cycles if no scalar integer | 32.00 |
| CQA cycles if FP arith vectorized | 9.34 |
| CQA cycles if fully vectorized | 4.00 |
| Front-end cycles | 8.75 |
| P0 cycles | 2.33 |
| P1 cycles | 2.33 |
| P2 cycles | 2.33 |
| P3 cycles | 2.33 |
| P4 cycles | 2.33 |
| P5 cycles | 2.33 |
| P6 cycles | 10.00 |
| P7 cycles | 10.00 |
| P8 cycles | 10.00 |
| P9 cycles | 10.00 |
| P10 cycles | 10.00 |
| P11 cycles | 10.00 |
| P12 cycles | 7.00 |
| P13 cycles | 7.00 |
| P14 cycles | 4.00 |
| P15 cycles | 4.00 |
| DIV/SQRT cycles | 32.00 |
| Inter-iter dependencies cycles | 2 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 71.00 |
| Nb uops | 70.00 |
| Nb loads | 32.00 |
| Nb stores | 9.00 |
| Nb stack references | 3.00 |
| FLOP/cycle | 1.38 |
| Nb FLOP add-sub | 14.00 |
| Nb FLOP mul | 2.00 |
| Nb FLOP fma | 10.00 |
| Nb FLOP div | 8.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 10.25 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 256.00 |
| Bytes stored | 72.00 |
| Stride 0 | 6.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 13.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 7.27 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 100.00 |
| Vector-efficiency ratio all | 13.41 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | 12.50 |
| Vector-efficiency ratio div_sqrt | 12.50 |
| Vector-efficiency ratio other | 25.00 |
| Path / |
 |
| nb instructions | 71 |
| nb uops | 70 |
| loop length | 324 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 14 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 3 |
| ADD-SUB / MUL ratio | 7.00 |
| micro-operation queue | 8.75 cycles |
| front end | 8.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 2.33 | 2.33 | 2.33 | 2.33 | 2.33 | 2.33 | 10.00 | 10.00 | 10.00 | 10.00 | 10.00 | 10.00 | 7.00 | 7.00 | 4.00 | 4.00 |
| cycles | 2.33 | 2.33 | 2.33 | 2.33 | 2.33 | 2.33 | 10.00 | 10.00 | 10.00 | 10.00 | 10.00 | 10.00 | 7.00 | 7.00 | 4.00 | 4.00 |
| Cycles executing div or sqrt instructions | 32.00 |
| Longest recurrence chain latency (RecMII) | 2.00 |
| Front-end | 8.75 |
| Dispatch | 10.00 |
| DIV/SQRT | 32.00 |
| Data deps. | 2.00 |
| Overall L1 | 32.00 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 7% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | 100% |
| all | 7% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | 100% |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 13% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | 12% |
| div/sqrt | 12% |
| other | 25% |
| all | 13% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | 12% |
| div/sqrt | 12% |
| other | 25% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV -0x48(%RBP),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| VMOVSD (%R8),%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMOVSD (%R15),%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMOVSD (%RBX),%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMOVSD (%R14),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VADDSD %XMM11,%XMM11,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VADDSD %XMM24,%XMM24,%XMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VDIVSD (%R9),%XMM2,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| VDIVSD (%R11),%XMM23,%XMM29 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| VADDSD (%RDI),%XMM0,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VADDSD %XMM1,%XMM1,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| ADD %R12,%R9 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD %R13,%R8 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD %R13,%RDI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VDIVSD (%R10),%XMM4,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| VMULSD (%RAX),%XMM8,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VADDSD %XMM8,%XMM29,%XMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VFMADD231SD (%RSI),%XMM0,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VFMADD132SD (%RDX),%XMM14,%XMM29 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VADDSD %XMM30,%XMM11,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VADDSD %XMM29,%XMM5,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VDIVSD %XMM2,%XMM6,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| VMOVSD %XMM0,(%RCX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| VMOVAPD %XMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| VMOVAPD %XMM0,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| VFMSUB213SD (%RSI),%XMM3,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| ADD %R13,%RCX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMOVSD %XMM1,(%RSI) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| VFMSUB213SD (%RDX),%XMM3,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VMOVSD %XMM4,(%RDX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| ADD %R12,%RDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VFMSUB213SD (%RAX),%XMM3,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VMOVSD %XMM0,(%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| ADD %R12,%RAX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMOVSD (%R15),%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMOVSD (%R14),%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMOVSD (%R8),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VADDSD %XMM8,%XMM8,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VMOVSD (%RBX),%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VDIVSD (%R9),%XMM14,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| VADDSD %XMM6,%XMM6,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VADDSD (%RDI),%XMM5,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VDIVSD (%R10),%XMM11,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| VADDSD %XMM24,%XMM24,%XMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VMULSD (%RAX),%XMM2,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VDIVSD (%R11),%XMM23,%XMM29 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| VFMADD231SD (%RSI),%XMM5,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VADDSD %XMM2,%XMM29,%XMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VFMADD132SD (%RDX),%XMM0,%XMM29 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VADDSD %XMM30,%XMM8,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VADDSD %XMM29,%XMM1,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VDIVSD %XMM14,%XMM4,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| VMOVSD %XMM5,(%RCX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| VMOVAPD %XMM5,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| VFMSUB213SD (%RSI),%XMM3,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VMOVSD %XMM6,(%RSI) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| ADDQ $0x2,-0x38(%RBP) | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV -0x38(%RBP),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| VMOVAPD %XMM5,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| ADD %R12,%R9 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VFMSUB213SD (%RDX),%XMM3,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| ADD %R13,%R8 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMOVSD %XMM11,(%RDX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| ADD %R13,%RDI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VFMSUB213SD (%RAX),%XMM3,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| ADD %R12,%RDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMOVSD %XMM5,(%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| ADD %R13,%RCX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD %R12,%RAX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CMP %R10,-0x40(%RBP) | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| JG 4cec9f <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEEvOS1Q_._omp_fn.0+0xb3f> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
|
| nb instructions | 71 |
| nb uops | 70 |
| loop length | 324 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 14 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 3 |
| ADD-SUB / MUL ratio | 7.00 |
| micro-operation queue | 8.75 cycles |
| front end | 8.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 2.33 | 2.33 | 2.33 | 2.33 | 2.33 | 2.33 | 10.00 | 10.00 | 10.00 | 10.00 | 10.00 | 10.00 | 7.00 | 7.00 | 4.00 | 4.00 |
| cycles | 2.33 | 2.33 | 2.33 | 2.33 | 2.33 | 2.33 | 10.00 | 10.00 | 10.00 | 10.00 | 10.00 | 10.00 | 7.00 | 7.00 | 4.00 | 4.00 |
| Cycles executing div or sqrt instructions | 32.00 |
| Longest recurrence chain latency (RecMII) | 2.00 |
| Front-end | 8.75 |
| Dispatch | 10.00 |
| DIV/SQRT | 32.00 |
| Data deps. | 2.00 |
| Overall L1 | 32.00 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 7% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | 100% |
| all | 7% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | 100% |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 13% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | 12% |
| div/sqrt | 12% |
| other | 25% |
| all | 13% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | 12% |
| div/sqrt | 12% |
| other | 25% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV -0x48(%RBP),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| VMOVSD (%R8),%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMOVSD (%R15),%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMOVSD (%RBX),%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMOVSD (%R14),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VADDSD %XMM11,%XMM11,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VADDSD %XMM24,%XMM24,%XMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VDIVSD (%R9),%XMM2,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| VDIVSD (%R11),%XMM23,%XMM29 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| VADDSD (%RDI),%XMM0,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VADDSD %XMM1,%XMM1,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| ADD %R12,%R9 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD %R13,%R8 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD %R13,%RDI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VDIVSD (%R10),%XMM4,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| VMULSD (%RAX),%XMM8,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VADDSD %XMM8,%XMM29,%XMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VFMADD231SD (%RSI),%XMM0,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VFMADD132SD (%RDX),%XMM14,%XMM29 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VADDSD %XMM30,%XMM11,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VADDSD %XMM29,%XMM5,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VDIVSD %XMM2,%XMM6,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| VMOVSD %XMM0,(%RCX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| VMOVAPD %XMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| VMOVAPD %XMM0,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| VFMSUB213SD (%RSI),%XMM3,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| ADD %R13,%RCX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMOVSD %XMM1,(%RSI) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| VFMSUB213SD (%RDX),%XMM3,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VMOVSD %XMM4,(%RDX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| ADD %R12,%RDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VFMSUB213SD (%RAX),%XMM3,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VMOVSD %XMM0,(%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| ADD %R12,%RAX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMOVSD (%R15),%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMOVSD (%R14),%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMOVSD (%R8),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VADDSD %XMM8,%XMM8,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VMOVSD (%RBX),%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VDIVSD (%R9),%XMM14,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| VADDSD %XMM6,%XMM6,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VADDSD (%RDI),%XMM5,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VDIVSD (%R10),%XMM11,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| VADDSD %XMM24,%XMM24,%XMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VMULSD (%RAX),%XMM2,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VDIVSD (%R11),%XMM23,%XMM29 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| VFMADD231SD (%RSI),%XMM5,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VADDSD %XMM2,%XMM29,%XMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VFMADD132SD (%RDX),%XMM0,%XMM29 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VADDSD %XMM30,%XMM8,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VADDSD %XMM29,%XMM1,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VDIVSD %XMM14,%XMM4,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| VMOVSD %XMM5,(%RCX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| VMOVAPD %XMM5,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| VFMSUB213SD (%RSI),%XMM3,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VMOVSD %XMM6,(%RSI) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| ADDQ $0x2,-0x38(%RBP) | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV -0x38(%RBP),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| VMOVAPD %XMM5,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| ADD %R12,%R9 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VFMSUB213SD (%RDX),%XMM3,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| ADD %R13,%R8 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMOVSD %XMM11,(%RDX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| ADD %R13,%RDI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VFMSUB213SD (%RAX),%XMM3,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| ADD %R12,%RDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMOVSD %XMM5,(%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| ADD %R13,%RCX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD %R12,%RAX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CMP %R10,-0x40(%RBP) | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| JG 4cec9f <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEEvOS1Q_._omp_fn.0+0xb3f> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |