| Loop Id: 2107 | Module: exec | Source: For.hpp:137-137 [...] | Coverage: 0.38% |
|---|
| Loop Id: 2107 | Module: exec | Source: For.hpp:137-137 [...] | Coverage: 0.38% |
|---|
0x4b3708 VMOVSD (%RDI,%RCX,8),%XMM12 [1] |
0x4b370d VMULSD (%RSI,%RCX,8),%XMM12,%XMM13 [2] |
0x4b3712 VFMADD132SD %XMM2,%XMM0,%XMM13 |
0x4b3717 VMOVSD 0x8(%RDI,%RCX,8),%XMM0 [1] |
0x4b371d VMULSD 0x8(%RSI,%RCX,8),%XMM0,%XMM14 [2] |
0x4b3723 VMOVSD 0x10(%RDI,%RCX,8),%XMM15 [1] |
0x4b3729 VMULSD 0x10(%RSI,%RCX,8),%XMM15,%XMM1 [2] |
0x4b372f VMOVSD 0x18(%RDI,%RCX,8),%XMM7 [1] |
0x4b3735 VMULSD 0x18(%RSI,%RCX,8),%XMM7,%XMM8 [2] |
0x4b373b VMOVSD 0x20(%RDI,%RCX,8),%XMM9 [1] |
0x4b3741 VMULSD 0x20(%RSI,%RCX,8),%XMM9,%XMM10 [2] |
0x4b3747 VMOVSD 0x28(%RDI,%RCX,8),%XMM11 [1] |
0x4b374d VMULSD 0x28(%RSI,%RCX,8),%XMM11,%XMM12 [2] |
0x4b3753 VMOVSD 0x38(%RDI,%RCX,8),%XMM0 [1] |
0x4b3759 VMULSD 0x38(%RSI,%RCX,8),%XMM0,%XMM0 [2] |
0x4b375f VFMADD132SD %XMM2,%XMM13,%XMM14 |
0x4b3764 VMOVSD 0x30(%RDI,%RCX,8),%XMM13 [1] |
0x4b376a VFMADD132SD %XMM2,%XMM14,%XMM1 |
0x4b376f VMULSD 0x30(%RSI,%RCX,8),%XMM13,%XMM14 [2] |
0x4b3775 ADD $0x8,%RCX |
0x4b3779 VFMADD132SD %XMM2,%XMM1,%XMM8 |
0x4b377e VFMADD132SD %XMM2,%XMM8,%XMM10 |
0x4b3783 VFMADD132SD %XMM2,%XMM10,%XMM12 |
0x4b3788 VFMADD132SD %XMM2,%XMM12,%XMM14 |
0x4b378d VFMADD132SD %XMM2,%XMM14,%XMM0 |
0x4b3792 CMP %R8,%RCX |
0x4b3795 JL 4b3708 |
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp: 137 - 137 |
-------------------------------------------------------------------------------- |
137: for (decltype(distance_it) i = 0; i < distance_it; ++i) { |
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp: 334 - 334 |
-------------------------------------------------------------------------------- |
334: return Ret{lhs} + rhs; |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►96.76+ | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
| ○ | start_thread | libc.so.6 | |
| ○ | __GI___clone3 | libc.so.6 | |
| ►2.90+ | GOMP_parallel | libgomp.h:982 | libgomp.so.1.0.0 |
| ○ | void PopulationSdom::operator([...] | privatizer.hpp:49 | exec |
| ○ | Kripke::Kernel::population(Kri[...] | ArchLayout.h:160 | exec |
| ○ | Kripke::SteadyStateSolver(Krip[...] | Comm.h:102 | exec |
| ○ | main | new_allocator.h:88 | exec |
| ○ | __libc_start_call_main | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | _start | kripke.cpp:129 | exec |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.95 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 4.00 |
| Bottlenecks | |
| Function | void RAJA::internal::StatementExecutor |
| Source | For.hpp:137-137,Operators.hpp:334-334 |
| Source loop unroll info | multi-versionned |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 32.00 |
| CQA cycles if no scalar integer | 32.00 |
| CQA cycles if FP arith vectorized | 16.44 |
| CQA cycles if fully vectorized | 4.00 |
| Front-end cycles | 3.25 |
| P0 cycles | 0.33 |
| P1 cycles | 0.33 |
| P2 cycles | 0.33 |
| P3 cycles | 0.33 |
| P4 cycles | 0.33 |
| P5 cycles | 0.33 |
| P6 cycles | 4.00 |
| P7 cycles | 4.00 |
| P8 cycles | 4.00 |
| P9 cycles | 4.00 |
| P10 cycles | 8.00 |
| P11 cycles | 8.00 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| P15 cycles | 0.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 32 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 27.00 |
| Nb uops | 26.00 |
| Nb loads | 16.00 |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.75 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 8.00 |
| Nb FLOP fma | 8.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 4.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 128.00 |
| Bytes stored | 0.00 |
| Stride 0 | 0.00 |
| Stride 1 | 2.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 12.50 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | 12.50 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.95 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 4.00 |
| Bottlenecks | |
| Function | void RAJA::internal::StatementExecutor |
| Source | For.hpp:137-137,Operators.hpp:334-334 |
| Source loop unroll info | multi-versionned |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 32.00 |
| CQA cycles if no scalar integer | 32.00 |
| CQA cycles if FP arith vectorized | 16.44 |
| CQA cycles if fully vectorized | 4.00 |
| Front-end cycles | 3.25 |
| P0 cycles | 0.33 |
| P1 cycles | 0.33 |
| P2 cycles | 0.33 |
| P3 cycles | 0.33 |
| P4 cycles | 0.33 |
| P5 cycles | 0.33 |
| P6 cycles | 4.00 |
| P7 cycles | 4.00 |
| P8 cycles | 4.00 |
| P9 cycles | 4.00 |
| P10 cycles | 8.00 |
| P11 cycles | 8.00 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| P15 cycles | 0.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 32 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 27.00 |
| Nb uops | 26.00 |
| Nb loads | 16.00 |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.75 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 8.00 |
| Nb FLOP fma | 8.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 4.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 128.00 |
| Bytes stored | 0.00 |
| Stride 0 | 0.00 |
| Stride 1 | 2.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 12.50 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | 12.50 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
 |
 |
| nb instructions | 27 |
| nb uops | 26 |
| loop length | 147 |
| used x86 registers | 4 |
| used mmx registers | 0 |
| used xmm registers | 12 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 3.25 cycles |
| front end | 3.25 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.33 | 0.33 | 0.33 | 0.33 | 0.33 | 0.33 | 4.00 | 4.00 | 4.00 | 4.00 | 8.00 | 8.00 | 0.00 | 0.00 | 0.00 | 0.00 |
| cycles | 0.33 | 0.33 | 0.33 | 0.33 | 0.33 | 0.33 | 4.00 | 4.00 | 4.00 | 4.00 | 8.00 | 8.00 | 0.00 | 0.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 32.00 |
| Front-end | 3.25 |
| Dispatch | 8.00 |
| Data deps. | 32.00 |
| Overall L1 | 32.00 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 12% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 12% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 12% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVSD (%RDI,%RCX,8),%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMULSD (%RSI,%RCX,8),%XMM12,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VFMADD132SD %XMM2,%XMM0,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VMOVSD 0x8(%RDI,%RCX,8),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMULSD 0x8(%RSI,%RCX,8),%XMM0,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VMOVSD 0x10(%RDI,%RCX,8),%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMULSD 0x10(%RSI,%RCX,8),%XMM15,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VMOVSD 0x18(%RDI,%RCX,8),%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMULSD 0x18(%RSI,%RCX,8),%XMM7,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VMOVSD 0x20(%RDI,%RCX,8),%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMULSD 0x20(%RSI,%RCX,8),%XMM9,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VMOVSD 0x28(%RDI,%RCX,8),%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMULSD 0x28(%RSI,%RCX,8),%XMM11,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VMOVSD 0x38(%RDI,%RCX,8),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMULSD 0x38(%RSI,%RCX,8),%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VFMADD132SD %XMM2,%XMM13,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VMOVSD 0x30(%RDI,%RCX,8),%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VFMADD132SD %XMM2,%XMM14,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VMULSD 0x30(%RSI,%RCX,8),%XMM13,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| ADD $0x8,%RCX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VFMADD132SD %XMM2,%XMM1,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VFMADD132SD %XMM2,%XMM8,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VFMADD132SD %XMM2,%XMM10,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VFMADD132SD %XMM2,%XMM12,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VFMADD132SD %XMM2,%XMM14,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| CMP %R8,%RCX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| JL 4b3708 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEEvOS1F_._omp_fn.0+0x3e8> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
|
|
| nb instructions | 27 |
| nb uops | 26 |
| loop length | 147 |
| used x86 registers | 4 |
| used mmx registers | 0 |
| used xmm registers | 12 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 3.25 cycles |
| front end | 3.25 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.33 | 0.33 | 0.33 | 0.33 | 0.33 | 0.33 | 4.00 | 4.00 | 4.00 | 4.00 | 8.00 | 8.00 | 0.00 | 0.00 | 0.00 | 0.00 |
| cycles | 0.33 | 0.33 | 0.33 | 0.33 | 0.33 | 0.33 | 4.00 | 4.00 | 4.00 | 4.00 | 8.00 | 8.00 | 0.00 | 0.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 32.00 |
| Front-end | 3.25 |
| Dispatch | 8.00 |
| Data deps. | 32.00 |
| Overall L1 | 32.00 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 12% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 12% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 12% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVSD (%RDI,%RCX,8),%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMULSD (%RSI,%RCX,8),%XMM12,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VFMADD132SD %XMM2,%XMM0,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VMOVSD 0x8(%RDI,%RCX,8),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMULSD 0x8(%RSI,%RCX,8),%XMM0,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VMOVSD 0x10(%RDI,%RCX,8),%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMULSD 0x10(%RSI,%RCX,8),%XMM15,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VMOVSD 0x18(%RDI,%RCX,8),%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMULSD 0x18(%RSI,%RCX,8),%XMM7,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VMOVSD 0x20(%RDI,%RCX,8),%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMULSD 0x20(%RSI,%RCX,8),%XMM9,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VMOVSD 0x28(%RDI,%RCX,8),%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMULSD 0x28(%RSI,%RCX,8),%XMM11,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VMOVSD 0x38(%RDI,%RCX,8),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMULSD 0x38(%RSI,%RCX,8),%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VFMADD132SD %XMM2,%XMM13,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VMOVSD 0x30(%RDI,%RCX,8),%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VFMADD132SD %XMM2,%XMM14,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VMULSD 0x30(%RSI,%RCX,8),%XMM13,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| ADD $0x8,%RCX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VFMADD132SD %XMM2,%XMM1,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VFMADD132SD %XMM2,%XMM8,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VFMADD132SD %XMM2,%XMM10,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VFMADD132SD %XMM2,%XMM12,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VFMADD132SD %XMM2,%XMM14,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| CMP %R8,%RCX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| JL 4b3708 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEEvOS1F_._omp_fn.0+0x3e8> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |