OV - exec - Function Kripke::ParallelComm::testRecieves()

	Function: Kripke::ParallelComm::testRecieves()	Module: exec	Source: ParallelComm.cpp:214-251 [...]	Coverage (incl. loops): 0.01% \| (excl. loops): 0.01%

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_construct.h: 119 - 119

--------------------------------------------------------------------------------

119:       ::new((void*)__p) _Tp(std::forward<_Args>(__args)...);

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_uninitialized.h: 667 - 667

--------------------------------------------------------------------------------

667: 	      ++__first;

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h: 385 - 1719

--------------------------------------------------------------------------------

385:       _M_deallocate(pointer __p, size_t __n)

[...]

398: 	this->_M_impl._M_start = this->_M_allocate(__n);

399: 	this->_M_impl._M_finish = this->_M_impl._M_start;

400: 	this->_M_impl._M_end_of_storage = this->_M_impl._M_start + __n;

[...]

738:       }

[...]

992:       size() const _GLIBCXX_NOEXCEPT

993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1131: 	return *(this->_M_impl._M_start + __n);

[...]

1719: 	this->_M_impl._M_finish =

/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp: 214 - 251

--------------------------------------------------------------------------------

214: void ParallelComm::testRecieves(void){

215: #ifdef KRIPKE_USE_MPI

216:   // Check for any recv requests that have completed

217:   int num_requests = recv_requests.size();

218:   bool done = false;

219:   while(!done && num_requests > 0){

[...]

226:     MPI_Testany(num_requests, &recv_requests[0], &index, &complete_flag, &recv_status[0]);

227:

228:     if(complete_flag != 0){

229:

230:       // get subdomain that this completed for

231:       int sdom_id = recv_subdomains[index];

[...]

239:       for(size_t i = 0;i < queue_sdom_ids.size();++ i){

240:         if(queue_sdom_ids[i] == sdom_id){

241:           queue_depends[i] --;

[...]

251: }

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/new_allocator.h: 126 - 172

--------------------------------------------------------------------------------

126:       allocate(size_type __n, const void* = static_cast<const void*>(0))

[...]

151: 	return static_cast<_Tp*>(_GLIBCXX_OPERATOR_NEW(__n * sizeof(_Tp)));

[...]

172: 	_GLIBCXX_OPERATOR_DELETE(_GLIBCXX_SIZED_DEALLOC(__p, __n));

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h: 438 - 1146

--------------------------------------------------------------------------------

438: 	{ *__to = std::move(*__from); }

[...]

450: 	  const ptrdiff_t _Num = __last - __first;

451: 	  if (__builtin_expect(_Num > 1, true))

452: 	    __builtin_memmove(__result, __first, sizeof(_Tp) * _Num);

453: 	  else if (_Num == 1)

[...]

939:       for (; __first != __last; ++__first)

940: 	*__first = __value;

[...]

1146:       if (__n <= 0)

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_iterator.h: 1068 - 1139

--------------------------------------------------------------------------------

1068:       : _M_current(__i) { }

[...]

1139:       { return __normal_iterator(_M_current + __n); }

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/vector.tcc: 184 - 186

--------------------------------------------------------------------------------

184:       if (__position + 1 != end())

185: 	_GLIBCXX_MOVE3(__position + 1, end(), __position);

186:       --this->_M_impl._M_finish;

0x4f1340 PUSH	%RBP

0x4f1341 MOV	%RSP,%RBP

0x4f1344 PUSH	%R15

0x4f1346 PUSH	%R14

0x4f1348 PUSH	%R13

0x4f134a PUSH	%R12

0x4f134c PUSH	%RBX

0x4f134d LEA	-0x58(%RBP),%RDX

0x4f1351 LEA	-0x54(%RBP),%RBX

0x4f1355 SUB	$0x48,%RSP

0x4f1359 MOV	0x30(%RDI),%RAX

0x4f135d MOV	%RBX,-0x70(%RBP)

0x4f1361 MOV	%RDX,-0x68(%RBP)

0x4f1365 SUB	0x28(%RDI),%RAX

0x4f1369 SAR	$0x2,%RAX

0x4f136d TEST	%EAX,%EAX

0x4f136f JLE	4f15cf

0x4f1375 MOV	%RDI,%R13

0x4f1378 MOVSXD	%EAX,%R12

(2563) 0x4f137b LEA	(%R12,%R12,4),%RBX

(2563) 0x4f137f MOV	%R12D,%R14D

(2563) 0x4f1382 SAL	$0x2,%RBX

(2563) 0x4f1386 MOV	%RBX,%RDI

(2563) 0x4f1389 CALL	403240 <_Znwm@plt>

(2563) 0x4f138e VPXOR	%XMM1,%XMM1,%XMM1

(2563) 0x4f1392 LEA	(%RAX,%RBX,1),%RSI

(2563) 0x4f1396 MOV	%RAX,%R15

(2563) 0x4f1399 VMOVDQU	%XMM1,(%RAX)

(2563) 0x4f139d LEA	0x14(%RAX),%RCX

(2563) 0x4f13a1 MOV	%RAX,-0x50(%RBP)

(2563) 0x4f13a5 MOV	%RSI,-0x40(%RBP)

(2563) 0x4f13a9 MOVL	$0,0x10(%RAX)

(2563) 0x4f13b0 CMP	$0x1,%R12

(2563) 0x4f13b4 JE	4f15a0

(2563) 0x4f13ba MOV	%RSI,%R8

(2563) 0x4f13bd MOV	$0xccccccccccccccd,%RDI

(2563) 0x4f13c7 MOV	%RCX,%R10

(2563) 0x4f13ca SUB	%RCX,%R8

(2563) 0x4f13cd SUB	$0x14,%R8

(2563) 0x4f13d1 SHR	$0x2,%R8

(2563) 0x4f13d5 IMUL	%RDI,%R8

(2563) 0x4f13d9 INC	%R8

(2563) 0x4f13dc AND	$0x7,%R8D

(2563) 0x4f13e0 JE	4f14ba

(2563) 0x4f13e6 CMP	$0x1,%R8

(2563) 0x4f13ea JE	4f149a

(2563) 0x4f13f0 CMP	$0x2,%R8

(2563) 0x4f13f4 JE	4f1483

(2563) 0x4f13fa CMP	$0x3,%R8

(2563) 0x4f13fe JE	4f146c

(2563) 0x4f1400 CMP	$0x4,%R8

(2563) 0x4f1404 JE	4f1455

(2563) 0x4f1406 CMP	$0x5,%R8

(2563) 0x4f140a JE	4f143e

(2563) 0x4f140c CMP	$0x6,%R8

(2563) 0x4f1410 JE	4f1427

(2563) 0x4f1412 VMOVDQU	(%RAX),%XMM0

(2563) 0x4f1416 MOV	0x10(%RAX),%R9D

(2563) 0x4f141a LEA	0x28(%RAX),%R10

(2563) 0x4f141e VMOVDQU	%XMM0,0x14(%RAX)

(2563) 0x4f1423 MOV	%R9D,0x10(%RCX)

(2563) 0x4f1427 VMOVDQU	(%R15),%XMM2

(2563) 0x4f142c ADD	$0x14,%R10

(2563) 0x4f1430 VMOVDQU	%XMM2,-0x14(%R10)

(2563) 0x4f1436 MOV	0x10(%R15),%R11D

(2563) 0x4f143a MOV	%R11D,-0x4(%R10)

(2563) 0x4f143e VMOVDQU	(%R15),%XMM3

(2563) 0x4f1443 ADD	$0x14,%R10

(2563) 0x4f1447 VMOVDQU	%XMM3,-0x14(%R10)

(2563) 0x4f144d MOV	0x10(%R15),%EAX

(2563) 0x4f1451 MOV	%EAX,-0x4(%R10)

(2563) 0x4f1455 VMOVDQU	(%R15),%XMM4

(2563) 0x4f145a ADD	$0x14,%R10

(2563) 0x4f145e VMOVDQU	%XMM4,-0x14(%R10)

(2563) 0x4f1464 MOV	0x10(%R15),%EDX

(2563) 0x4f1468 MOV	%EDX,-0x4(%R10)

(2563) 0x4f146c VMOVDQU	(%R15),%XMM5

(2563) 0x4f1471 ADD	$0x14,%R10

(2563) 0x4f1475 VMOVDQU	%XMM5,-0x14(%R10)

(2563) 0x4f147b MOV	0x10(%R15),%R8D

(2563) 0x4f147f MOV	%R8D,-0x4(%R10)

(2563) 0x4f1483 VMOVDQU	(%R15),%XMM6

(2563) 0x4f1488 ADD	$0x14,%R10

(2563) 0x4f148c VMOVDQU	%XMM6,-0x14(%R10)

(2563) 0x4f1492 MOV	0x10(%R15),%EDI

(2563) 0x4f1496 MOV	%EDI,-0x4(%R10)

(2563) 0x4f149a VMOVDQU	(%R15),%XMM7

(2563) 0x4f149f ADD	$0x14,%R10

(2563) 0x4f14a3 VMOVDQU	%XMM7,-0x14(%R10)

(2563) 0x4f14a9 MOV	0x10(%R15),%R9D

(2563) 0x4f14ad MOV	%R9D,-0x4(%R10)

(2563) 0x4f14b1 CMP	%R10,%RSI

(2563) 0x4f14b4 JE	4f156b

  (2565) 0x4f14ba VMOVDQU	(%R15),%XMM8

  (2565) 0x4f14bf ADD	$0xa0,%R10

  (2565) 0x4f14c6 VMOVDQU	%XMM8,-0xa0(%R10)

  (2565) 0x4f14cf MOV	0x10(%R15),%R11D

  (2565) 0x4f14d3 MOV	%R11D,-0x90(%R10)

  (2565) 0x4f14da VMOVDQU	(%R15),%XMM9

  (2565) 0x4f14df VMOVDQU	%XMM9,-0x8c(%R10)

  (2565) 0x4f14e8 MOV	0x10(%R15),%EAX

  (2565) 0x4f14ec MOV	%EAX,-0x7c(%R10)

  (2565) 0x4f14f0 VMOVDQU	(%R15),%XMM10

  (2565) 0x4f14f5 VMOVDQU	%XMM10,-0x78(%R10)

  (2565) 0x4f14fb MOV	0x10(%R15),%EDX

  (2565) 0x4f14ff MOV	%EDX,-0x68(%R10)

  (2565) 0x4f1503 VMOVDQU	(%R15),%XMM11

  (2565) 0x4f1508 VMOVDQU	%XMM11,-0x64(%R10)

  (2565) 0x4f150e MOV	0x10(%R15),%R8D

  (2565) 0x4f1512 MOV	%R8D,-0x54(%R10)

  (2565) 0x4f1516 VMOVDQU	(%R15),%XMM12

  (2565) 0x4f151b VMOVDQU	%XMM12,-0x50(%R10)

  (2565) 0x4f1521 MOV	0x10(%R15),%EDI

  (2565) 0x4f1525 MOV	%EDI,-0x40(%R10)

  (2565) 0x4f1529 VMOVDQU	(%R15),%XMM13

  (2565) 0x4f152e VMOVDQU	%XMM13,-0x3c(%R10)

  (2565) 0x4f1534 MOV	0x10(%R15),%R9D

  (2565) 0x4f1538 MOV	%R9D,-0x2c(%R10)

  (2565) 0x4f153c VMOVDQU	(%R15),%XMM14

  (2565) 0x4f1541 VMOVDQU	%XMM14,-0x28(%R10)

  (2565) 0x4f1547 MOV	0x10(%R15),%R11D

  (2565) 0x4f154b MOV	%R11D,-0x18(%R10)

  (2565) 0x4f154f VMOVDQU	(%R15),%XMM15

  (2565) 0x4f1554 VMOVDQU	%XMM15,-0x14(%R10)

  (2565) 0x4f155a MOV	0x10(%R15),%EAX

  (2565) 0x4f155e MOV	%EAX,-0x4(%R10)

  (2565) 0x4f1562 CMP	%R10,%RSI

  (2565) 0x4f1565 JNE	4f14ba

(2563) 0x4f156b MOV	$-0x28,%R10

(2563) 0x4f1572 MOV	$0x3fffffffffffffff,%RDX

(2563) 0x4f157c SUB	%R15,%R10

(2563) 0x4f157f ADD	%RSI,%R10

(2563) 0x4f1582 MOV	$0xccccccccccccccd,%RSI

(2563) 0x4f158c SHR	$0x2,%R10

(2563) 0x4f1590 IMUL	%RSI,%R10

(2563) 0x4f1594 AND	%RDX,%R10

(2563) 0x4f1597 LEA	(%R10,%R10,4),%R8

(2563) 0x4f159b LEA	0x14(%RCX,%R8,4),%RCX

(2563) 0x4f15a0 MOV	%RCX,-0x48(%RBP)

(2563) 0x4f15a4 MOV	0x28(%R13),%RSI

(2563) 0x4f15a8 MOV	-0x70(%RBP),%RCX

(2563) 0x4f15ac MOV	-0x68(%RBP),%RDX

(2563) 0x4f15b0 MOV	%R15,%R8

(2563) 0x4f15b3 MOV	%R14D,%EDI

(2563) 0x4f15b6 CALL	403390 <MPI_Testany@plt>

(2563) 0x4f15bb MOV	-0x54(%RBP),%R14D

(2563) 0x4f15bf TEST	%R14D,%R14D

(2563) 0x4f15c2 JNE	4f15e0

0x4f15c4 MOV	%RBX,%RSI

0x4f15c7 MOV	%R15,%RDI

0x4f15ca CALL	403250 <_ZdlPvm@plt>

0x4f15cf ADD	$0x48,%RSP

0x4f15d3 POP	%RBX

0x4f15d4 POP	%R12

0x4f15d6 POP	%R13

0x4f15d8 POP	%R14

0x4f15da POP	%R15

0x4f15dc POP	%RBP

0x4f15dd RET

0x4f15de XCHG	%AX,%AX

(2563) 0x4f15e0 MOVSXD	-0x58(%RBP),%RDI

(2563) 0x4f15e4 MOV	0x40(%R13),%RDX

(2563) 0x4f15e8 MOV	0x30(%R13),%RAX

(2563) 0x4f15ec MOV	%RDI,%R10

(2563) 0x4f15ef SAL	$0x2,%RDI

(2563) 0x4f15f3 MOV	(%RDX,%RDI,1),%R14D

(2563) 0x4f15f7 ADD	0x28(%R13),%RDI

(2563) 0x4f15fb LEA	0x4(%RDI),%RSI

(2563) 0x4f15ff CMP	%RSI,%RAX

(2563) 0x4f1602 JE	4f1628

(2563) 0x4f1604 MOV	%RAX,%R9

(2563) 0x4f1607 SUB	%RSI,%R9

(2563) 0x4f160a CMP	$0x4,%R9

(2563) 0x4f160e JLE	4f17b8

(2563) 0x4f1614 MOV	%R9,%RDX

(2563) 0x4f1617 CALL	403460 <memmove@plt>

(2563) 0x4f161c MOV	0x40(%R13),%RDX

(2563) 0x4f1620 MOV	0x30(%R13),%RAX

(2563) 0x4f1624 MOVSXD	-0x58(%RBP),%R10

(2563) 0x4f1628 MOV	0x48(%R13),%R8

(2563) 0x4f162c LEA	(%RDX,%R10,4),%RDI

(2563) 0x4f1630 SUB	$0x4,%RAX

(2563) 0x4f1634 LEA	0x4(%RDI),%RSI

(2563) 0x4f1638 MOV	%RAX,0x30(%R13)

(2563) 0x4f163c CMP	%RSI,%R8

(2563) 0x4f163f JE	4f165a

(2563) 0x4f1641 MOV	%R8,%RDX

(2563) 0x4f1644 SUB	%RSI,%RDX

(2563) 0x4f1647 CMP	$0x4,%RDX

(2563) 0x4f164b JLE	4f17ce

(2563) 0x4f1651 CALL	403460 <memmove@plt>

(2563) 0x4f1656 MOV	0x48(%R13),%R8

(2563) 0x4f165a MOV	0x60(%R13),%RDI

(2563) 0x4f165e MOV	0x58(%R13),%R9

(2563) 0x4f1662 SUB	$0x4,%R8

(2563) 0x4f1666 MOV	%R8,0x48(%R13)

(2563) 0x4f166a MOV	%RDI,%R11

(2563) 0x4f166d SUB	%R9,%R11

(2563) 0x4f1670 SAR	$0x2,%R11

(2563) 0x4f1674 CMP	%R9,%RDI

(2563) 0x4f1677 JE	4f1780

(2563) 0x4f167d LEA	-0x1(%R11),%RCX

(2563) 0x4f1681 XOR	%EAX,%EAX

(2563) 0x4f1683 AND	$0x7,%ECX

(2563) 0x4f1686 CMP	%R14D,(%R9)

(2563) 0x4f1689 JE	4f17a0

(2563) 0x4f168f MOV	$0x1,%EAX

(2563) 0x4f1694 CMP	%R11,%RAX

(2563) 0x4f1697 JAE	4f1780

(2563) 0x4f169d TEST	%RCX,%RCX

(2563) 0x4f16a0 JE	4f171d

(2563) 0x4f16a2 CMP	$0x1,%RCX

(2563) 0x4f16a6 JE	4f170b

(2563) 0x4f16a8 CMP	$0x2,%RCX

(2563) 0x4f16ac JE	4f16fe

(2563) 0x4f16ae CMP	$0x3,%RCX

(2563) 0x4f16b2 JE	4f16f1

(2563) 0x4f16b4 CMP	$0x4,%RCX

(2563) 0x4f16b8 JE	4f16e4

(2563) 0x4f16ba CMP	$0x5,%RCX

(2563) 0x4f16be JE	4f16d7

(2563) 0x4f16c0 CMP	$0x6,%RCX

(2563) 0x4f16c4 JNE	4f17aa

(2563) 0x4f16ca CMP	%R14D,(%R9,%RAX,4)

(2563) 0x4f16ce JE	4f17a0

(2563) 0x4f16d4 INC	%RAX

(2563) 0x4f16d7 CMP	%R14D,(%R9,%RAX,4)

(2563) 0x4f16db JE	4f17a0

(2563) 0x4f16e1 INC	%RAX

(2563) 0x4f16e4 CMP	%R14D,(%R9,%RAX,4)

(2563) 0x4f16e8 JE	4f17a0

(2563) 0x4f16ee INC	%RAX

(2563) 0x4f16f1 CMP	%R14D,(%R9,%RAX,4)

(2563) 0x4f16f5 JE	4f17a0

(2563) 0x4f16fb INC	%RAX

(2563) 0x4f16fe CMP	%R14D,(%R9,%RAX,4)

(2563) 0x4f1702 JE	4f17a0

(2563) 0x4f1708 INC	%RAX

(2563) 0x4f170b CMP	%R14D,(%R9,%RAX,4)

(2563) 0x4f170f JE	4f17a0

(2563) 0x4f1715 INC	%RAX

(2563) 0x4f1718 CMP	%R11,%RAX

(2563) 0x4f171b JAE	4f1780

  (2564) 0x4f171d CMP	%R14D,(%R9,%RAX,4)

  (2564) 0x4f1721 JE	4f17a0

  (2564) 0x4f1723 LEA	0x1(%RAX),%R10

  (2564) 0x4f1727 MOV	%R10,%RAX

  (2564) 0x4f172a CMP	%R14D,(%R9,%R10,4)

  (2564) 0x4f172e JE	4f17a0

  (2564) 0x4f1730 INC	%RAX

  (2564) 0x4f1733 CMP	%R14D,(%R9,%RAX,4)

  (2564) 0x4f1737 JE	4f17a0

  (2564) 0x4f1739 LEA	0x2(%R10),%RAX

  (2564) 0x4f173d CMP	%R14D,0x8(%R9,%R10,4)

  (2564) 0x4f1742 JE	4f17a0

  (2564) 0x4f1744 LEA	0x3(%R10),%RAX

  (2564) 0x4f1748 CMP	%R14D,0xc(%R9,%R10,4)

  (2564) 0x4f174d JE	4f17a0

  (2564) 0x4f174f LEA	0x4(%R10),%RAX

  (2564) 0x4f1753 CMP	%R14D,0x10(%R9,%R10,4)

  (2564) 0x4f1758 JE	4f17a0

  (2564) 0x4f175a LEA	0x5(%R10),%RAX

  (2564) 0x4f175e CMP	%R14D,0x14(%R9,%R10,4)

  (2564) 0x4f1763 JE	4f17a0

  (2564) 0x4f1765 LEA	0x6(%R10),%RAX

  (2564) 0x4f1769 CMP	%R14D,0x18(%R9,%R10,4)

  (2564) 0x4f176e JE	4f17a0

  (2564) 0x4f1770 LEA	0x7(%R10),%RAX

  (2564) 0x4f1774 CMP	%R11,%RAX

  (2564) 0x4f1777 JB	4f171d

(2563) 0x4f1779 NOPL	(%RAX)

(2563) 0x4f1780 MOV	%RBX,%RSI

(2563) 0x4f1783 MOV	%R15,%RDI

(2563) 0x4f1786 DEC	%R12

(2563) 0x4f1789 CALL	403250 <_ZdlPvm@plt>

(2563) 0x4f178e TEST	%R12D,%R12D

(2563) 0x4f1791 JG	4f137b

0x4f1797 JMP	4f15cf

0x4f179c NOPL	(%RAX)

(2563) 0x4f17a0 MOV	0x70(%R13),%R14

(2563) 0x4f17a4 DECL	(%R14,%RAX,4)

(2563) 0x4f17a8 JMP	4f1780

(2563) 0x4f17aa CMP	%R14D,0x4(%R9)

(2563) 0x4f17ae JE	4f17a0

(2563) 0x4f17b0 INC	%RAX

(2563) 0x4f17b3 JMP	4f16ca

(2563) 0x4f17b8 JNE	4f1628

(2563) 0x4f17be MOV	0x4(%RDI),%R11D

(2563) 0x4f17c2 MOV	%R11D,(%RDI)

(2563) 0x4f17c5 MOVSXD	-0x58(%RBP),%R10

(2563) 0x4f17c9 JMP	4f1628

(2563) 0x4f17ce JNE	4f165a

(2563) 0x4f17d4 MOV	0x4(%RDI),%ESI

(2563) 0x4f17d7 MOV	%ESI,(%RDI)

(2563) 0x4f17d9 JMP	4f165a

0x4f17de MOV	%RAX,%RBX

0x4f17e1 JMP	415498

0x4f17e6 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►92.00+	Kripke::SweepComm::readySubdom[...]	SweepComm.cpp:65	exec
○	Kripke::SweepSolver(Kripke::Co[...]	stl_vector.h:992	exec
○	Kripke::SteadyStateSolver(Krip[...]	alloc_traits.h:941	exec
○	main	new_allocator.h:88	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	kripke.cpp:129	exec
►8.00+	Kripke::SweepComm::readySubdom[...]	SweepComm.cpp:65	exec
○	Kripke::SweepSolver(Kripke::Co[...]	stl_vector.h:992	exec
○	Kripke::SteadyStateSolver(Krip[...]	alloc_traits.h:941	exec
○	main	new_allocator.h:88	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_9

Source file and lines	ParallelComm.cpp:214-251
Module	exec

The function is defined in:

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_construct.h:119
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_uninitialized.h:667
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:385,398-400,738,992-993,1131,1719
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp:214-219,226-231,239-241,251
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/new_allocator.h:126,151,172
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h:438,450-453,939-940,1146
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_iterator.h:1068,1139
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/vector.tcc:184-186

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 4.25 to 0.28 cycles (15.16x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

operator delete(void*, unsigned long): 1 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 16 bytes.

General properties

nb instructions	36
nb uops	34
loop length	114
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.17	2.17	2.17	2.17	2.17	2.17	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.17	2.17	2.17	2.17	2.17	2.17	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.25
Dispatch	2.17
Overall L1	4.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.25 cycles. At this rate:

1% of peak load performance is reached (3.76 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.76 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.25 to 2.17 cycles (1.96x speedup).

ASM code

In the binary file, the address of the function is: 4f1340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LEA -0x58(%RBP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x54(%RBP),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x30(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RBX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RDX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SUB 0x28(%RDI),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
SAR $0x2,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 4f15cf <_ZN6Kripke12ParallelComm12testRecievesEv+0x28f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOVSXD %EAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 403250 <_ZdlPvm@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 4f15cf <_ZN6Kripke12ParallelComm12testRecievesEv+0x28f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
JMP 415498 <_ZN6Kripke12ParallelComm12testRecievesEv.cold>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_9

Source file and lines	ParallelComm.cpp:214-251
Module	exec

The function is defined in:

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_construct.h:119
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_uninitialized.h:667
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:385,398-400,738,992-993,1131,1719
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp:214-219,226-231,239-241,251
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/new_allocator.h:126,151,172
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h:438,450-453,939-940,1146
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_iterator.h:1068,1139
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/vector.tcc:184-186

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

operator delete(void*, unsigned long): 1 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 16 bytes.

General properties

nb instructions	36
nb uops	34
loop length	114
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.17	2.17	2.17	2.17	2.17	2.17	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.17	2.17	2.17	2.17	2.17	2.17	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.25
Dispatch	2.17
Overall L1	4.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.25 cycles. At this rate:

1% of peak load performance is reached (3.76 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.76 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4f1340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LEA -0x58(%RBP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x54(%RBP),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x30(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RBX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RDX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SUB 0x28(%RDI),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
SAR $0x2,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 4f15cf <_ZN6Kripke12ParallelComm12testRecievesEv+0x28f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOVSXD %EAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 403250 <_ZdlPvm@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 4f15cf <_ZN6Kripke12ParallelComm12testRecievesEv+0x28f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
JMP 415498 <_ZN6Kripke12ParallelComm12testRecievesEv.cold>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼Kripke::ParallelComm::testRecieves()–	0.01	0.00
▼Loop 2563 - stl_algobase.h:438-1146 - exec–	0.01	0.03
○Loop 2565 - stl_algobase.h:939-940 - exec	0.00	0.01
○Loop 2564 - ParallelComm.cpp:239-240 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code