OV - exec - Function Kripke::ParallelComm::getReadyList()

	Function: Kripke::ParallelComm::getReadyList()	Module: exec	Source: ParallelComm.cpp:254-263 [...]	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_uninitialized.h: 1101 - 1102

--------------------------------------------------------------------------------

1101:       _ForwardIterator __cur = __result;

1102:       for (; __first != __last; ++__first, (void)++__cur)

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h: 99 - 1912

--------------------------------------------------------------------------------

99: 	: _M_start(), _M_finish(), _M_end_of_storage()

[...]

993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1908: 	if (max_size() - size() < __n)

1909: 	  __throw_length_error(__N(__s));

1910:

1911: 	const size_type __len = size() + (std::max)(size(), __n);

1912: 	return (__len < size() || __len > max_size()) ? max_size() : __len;

/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp: 254 - 263

--------------------------------------------------------------------------------

254: std::vector<SdomId> ParallelComm::getReadyList(void){

255:   // build up a list of ready subdomains

256:   std::vector<SdomId> ready;

257:   for(size_t i = 0;i < queue_depends.size();++ i){

258:     if(queue_depends[i] == 0){

259:       ready.push_back(SdomId(queue_sdom_ids[i]));

260:     }

261:   }

262:   return ready;

263: }

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/new_allocator.h: 126 - 191

--------------------------------------------------------------------------------

126:       allocate(size_type __n, const void* = static_cast<const void*>(0))

[...]

151: 	return static_cast<_Tp*>(_GLIBCXX_OPERATOR_NEW(__n * sizeof(_Tp)));

152:       }

153:

154:       // __p is not permitted to be a null pointer.

155:       void

156:       deallocate(_Tp* __p, size_type __n __attribute__ ((__unused__)))

[...]

172: 	_GLIBCXX_OPERATOR_DELETE(_GLIBCXX_SIZED_DEALLOC(__p, __n));

[...]

191: 	{ ::new((void *)__p) _Up(std::forward<_Args>(__args)...); }

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h: 262 - 262

--------------------------------------------------------------------------------

262:       if (__a < __b)

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/vector.tcc: 114 - 695

--------------------------------------------------------------------------------

114: 	if (this->_M_impl._M_finish != this->_M_impl._M_end_of_storage)

115: 	  {

116: 	    _GLIBCXX_ASAN_ANNOTATE_GROW(1);

117: 	    _Alloc_traits::construct(this->_M_impl, this->_M_impl._M_finish,

118: 				     std::forward<_Args>(__args)...);

119: 	    ++this->_M_impl._M_finish;

[...]

581:       vector<_Tp, _Alloc>::

[...]

614: 	  if (_M_storage)

[...]

649: 	    ++__new_finish;

[...]

687: 	__guard._M_len = this->_M_impl._M_end_of_storage - __old_start;

688:       }

689:       // deallocate should be called before assignments to _M_impl,

690:       // to avoid call-clobbering

691:

692:       this->_M_impl._M_start = __new_start;

693:       this->_M_impl._M_finish = __new_finish;

694:       this->_M_impl._M_end_of_storage = __new_start + __len;

695:     }

0x4f0dc0 PUSH	%RBP

0x4f0dc1 MOV	%RSP,%RBP

0x4f0dc4 PUSH	%R15

0x4f0dc6 PUSH	%R14

0x4f0dc8 PUSH	%R13

0x4f0dca PUSH	%R12

0x4f0dcc PUSH	%RBX

0x4f0dcd MOV	%RDI,%R13

0x4f0dd0 SUB	$0x28,%RSP

0x4f0dd4 MOV	0x70(%RSI),%R15

0x4f0dd8 MOVQ	$0,(%RDI)

0x4f0ddf MOVQ	$0,0x8(%RDI)

0x4f0de7 MOVQ	$0,0x10(%RDI)

0x4f0def CMP	0x78(%RSI),%R15

0x4f0df3 JE	4f0e50

0x4f0df5 MOV	%RSI,%R14

0x4f0df8 XOR	%EBX,%EBX

0x4f0dfa JMP	4f0e13

0x4f0dfc NOPL	(%RAX)

(2560) 0x4f0e00 MOV	0x78(%R14),%R12

(2560) 0x4f0e04 INC	%RBX

(2560) 0x4f0e07 SUB	%R15,%R12

(2560) 0x4f0e0a SAR	$0x2,%R12

(2560) 0x4f0e0e CMP	%R12,%RBX

(2560) 0x4f0e11 JAE	4f0e50

(2560) 0x4f0e13 MOV	(%R15,%RBX,4),%ECX

(2560) 0x4f0e17 LEA	(,%RBX,4),%RAX

(2560) 0x4f0e1f TEST	%ECX,%ECX

(2560) 0x4f0e21 JNE	4f0e00

(2560) 0x4f0e23 MOV	0x58(%R14),%RSI

(2560) 0x4f0e27 MOV	0x8(%R13),%R12

(2560) 0x4f0e2b MOVSXD	(%RSI,%RAX,1),%RDI

(2560) 0x4f0e2f CMP	0x10(%R13),%R12

(2560) 0x4f0e33 JE	4f0e70

(2560) 0x4f0e35 MOV	%RDI,(%R12)

(2560) 0x4f0e39 ADD	$0x8,%R12

(2560) 0x4f0e3d MOV	%R12,0x8(%R13)

(2560) 0x4f0e41 JMP	4f0e00

0x4f0e43 NOPW	%CS:(%RAX,%RAX,1)

0x4f0e4e XCHG	%AX,%AX

0x4f0e50 ADD	$0x28,%RSP

0x4f0e54 MOV	%R13,%RAX

0x4f0e57 POP	%RBX

0x4f0e58 POP	%R12

0x4f0e5a POP	%R13

0x4f0e5c POP	%R14

0x4f0e5e POP	%R15

0x4f0e60 POP	%RBP

0x4f0e61 RET

0x4f0e62 NOPW	%CS:(%RAX,%RAX,1)

0x4f0e6d NOPL	(%RAX)

(2560) 0x4f0e70 MOV	(%R13),%RDX

(2560) 0x4f0e74 MOV	%R12,%R8

(2560) 0x4f0e77 MOV	$0xfffffffffffffff,%R9

(2560) 0x4f0e81 SUB	%RDX,%R8

(2560) 0x4f0e84 MOV	%R8,%R15

(2560) 0x4f0e87 SAR	$0x3,%R15

(2560) 0x4f0e8b CMP	%R9,%R15

(2560) 0x4f0e8e JE	415450

(2560) 0x4f0e94 TEST	%R15,%R15

(2560) 0x4f0e97 MOV	$0x1,%R10D

(2560) 0x4f0e9d CMOVNE	%R15,%R10

(2560) 0x4f0ea1 ADD	%R10,%R15

(2560) 0x4f0ea4 JB	4f1041

(2560) 0x4f0eaa MOV	$0xfffffffffffffff,%R11

(2560) 0x4f0eb4 CMP	%R11,%R15

(2560) 0x4f0eb7 CMOVA	%R11,%R15

(2560) 0x4f0ebb SAL	$0x3,%R15

(2560) 0x4f0ebf MOV	%RDI,-0x40(%RBP)

(2560) 0x4f0ec3 MOV	%R8,-0x50(%RBP)

(2560) 0x4f0ec7 MOV	%RDX,-0x48(%RBP)

(2560) 0x4f0ecb MOV	%R15,%RDI

(2560) 0x4f0ece CALL	403240 <_Znwm@plt>

(2560) 0x4f0ed3 MOV	%RAX,%R9

(2560) 0x4f0ed6 MOV	-0x50(%RBP),%RCX

(2560) 0x4f0eda MOV	-0x40(%RBP),%RAX

(2560) 0x4f0ede MOV	-0x48(%RBP),%RDI

(2560) 0x4f0ee2 MOV	%RAX,(%R9,%RCX,1)

(2560) 0x4f0ee6 CMP	%RDI,%R12

(2560) 0x4f0ee9 JE	4f103c

(2560) 0x4f0eef MOV	%R12,%R8

(2560) 0x4f0ef2 MOV	%R9,%R11

(2560) 0x4f0ef5 MOV	%RDI,%R10

(2560) 0x4f0ef8 SUB	%RDI,%R8

(2560) 0x4f0efb SUB	$0x8,%R8

(2560) 0x4f0eff SHR	$0x3,%R8

(2560) 0x4f0f03 INC	%R8

(2560) 0x4f0f06 AND	$0x7,%R8D

(2560) 0x4f0f0a JE	4f0fa1

(2560) 0x4f0f10 CMP	$0x1,%R8

(2560) 0x4f0f14 JE	4f0f8d

(2560) 0x4f0f16 CMP	$0x2,%R8

(2560) 0x4f0f1a JE	4f0f7e

(2560) 0x4f0f1c CMP	$0x3,%R8

(2560) 0x4f0f20 JE	4f0f6f

(2560) 0x4f0f22 CMP	$0x4,%R8

(2560) 0x4f0f26 JE	4f0f60

(2560) 0x4f0f28 CMP	$0x5,%R8

(2560) 0x4f0f2c JE	4f0f51

(2560) 0x4f0f2e CMP	$0x6,%R8

(2560) 0x4f0f32 JE	4f0f42

(2560) 0x4f0f34 MOV	(%RDI),%RDX

(2560) 0x4f0f37 LEA	0x8(%RDI),%R10

(2560) 0x4f0f3b LEA	0x8(%R9),%R11

(2560) 0x4f0f3f MOV	%RDX,(%R9)

(2560) 0x4f0f42 MOV	(%R10),%RAX

(2560) 0x4f0f45 ADD	$0x8,%R11

(2560) 0x4f0f49 ADD	$0x8,%R10

(2560) 0x4f0f4d MOV	%RAX,-0x8(%R11)

(2560) 0x4f0f51 MOV	(%R10),%RCX

(2560) 0x4f0f54 ADD	$0x8,%R11

(2560) 0x4f0f58 ADD	$0x8,%R10

(2560) 0x4f0f5c MOV	%RCX,-0x8(%R11)

(2560) 0x4f0f60 MOV	(%R10),%RSI

(2560) 0x4f0f63 ADD	$0x8,%R11

(2560) 0x4f0f67 ADD	$0x8,%R10

(2560) 0x4f0f6b MOV	%RSI,-0x8(%R11)

(2560) 0x4f0f6f MOV	(%R10),%R8

(2560) 0x4f0f72 ADD	$0x8,%R11

(2560) 0x4f0f76 ADD	$0x8,%R10

(2560) 0x4f0f7a MOV	%R8,-0x8(%R11)

(2560) 0x4f0f7e MOV	(%R10),%RDX

(2560) 0x4f0f81 ADD	$0x8,%R11

(2560) 0x4f0f85 ADD	$0x8,%R10

(2560) 0x4f0f89 MOV	%RDX,-0x8(%R11)

(2560) 0x4f0f8d MOV	(%R10),%RAX

(2560) 0x4f0f90 ADD	$0x8,%R10

(2560) 0x4f0f94 ADD	$0x8,%R11

(2560) 0x4f0f98 MOV	%RAX,-0x8(%R11)

(2560) 0x4f0f9c CMP	%R10,%R12

(2560) 0x4f0f9f JE	4f0fed

  (2561) 0x4f0fa1 MOV	(%R10),%RCX

  (2561) 0x4f0fa4 ADD	$0x40,%R10

  (2561) 0x4f0fa8 ADD	$0x40,%R11

  (2561) 0x4f0fac MOV	%RCX,-0x40(%R11)

  (2561) 0x4f0fb0 MOV	-0x38(%R10),%RSI

  (2561) 0x4f0fb4 MOV	%RSI,-0x38(%R11)

  (2561) 0x4f0fb8 MOV	-0x30(%R10),%R8

  (2561) 0x4f0fbc MOV	%R8,-0x30(%R11)

  (2561) 0x4f0fc0 MOV	-0x28(%R10),%RDX

  (2561) 0x4f0fc4 MOV	%RDX,-0x28(%R11)

  (2561) 0x4f0fc8 MOV	-0x20(%R10),%RAX

  (2561) 0x4f0fcc MOV	%RAX,-0x20(%R11)

  (2561) 0x4f0fd0 MOV	-0x18(%R10),%RCX

  (2561) 0x4f0fd4 MOV	%RCX,-0x18(%R11)

  (2561) 0x4f0fd8 MOV	-0x10(%R10),%RSI

  (2561) 0x4f0fdc MOV	%RSI,-0x10(%R11)

  (2561) 0x4f0fe0 MOV	-0x8(%R10),%R8

  (2561) 0x4f0fe4 MOV	%R8,-0x8(%R11)

  (2561) 0x4f0fe8 CMP	%R10,%R12

  (2561) 0x4f0feb JNE	4f0fa1

(2560) 0x4f0fed SUB	%RDI,%R12

(2560) 0x4f0ff0 LEA	(%R9,%R12,1),%RSI

(2560) 0x4f0ff4 ADD	$0x8,%RSI

(2560) 0x4f0ff8 VMOVQ	%R9,%XMM1

(2560) 0x4f0ffd VPINSRQ	$0x1,%RSI,%XMM1,%XMM0

(2560) 0x4f1003 TEST	%RDI,%RDI

(2560) 0x4f1006 JE	4f1026

(2560) 0x4f1008 MOV	0x10(%R13),%RSI

(2560) 0x4f100c VMOVDQA	%XMM0,-0x40(%RBP)

(2560) 0x4f1011 MOV	%R9,-0x48(%RBP)

(2560) 0x4f1015 SUB	%RDI,%RSI

(2560) 0x4f1018 CALL	403250 <_ZdlPvm@plt>

(2560) 0x4f101d VMOVDQA	-0x40(%RBP),%XMM0

(2560) 0x4f1022 MOV	-0x48(%RBP),%R9

(2560) 0x4f1026 ADD	%R15,%R9

(2560) 0x4f1029 VMOVDQU	%XMM0,(%R13)

(2560) 0x4f102f MOV	0x70(%R14),%R15

(2560) 0x4f1033 MOV	%R9,0x10(%R13)

(2560) 0x4f1037 JMP	4f0e00

(2560) 0x4f103c MOV	%R9,%RSI

(2560) 0x4f103f JMP	4f0ff4

(2560) 0x4f1041 MOV	$0x7ffffffffffffff8,%R15

(2560) 0x4f104b JMP	4f0ebf

0x4f1050 JMP	41545c

0x4f1055 NOP

0x4f1056 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►95.65+	Kripke::SweepComm::readySubdom[...]	SweepComm.cpp:66	exec
○	Kripke::SweepSolver(Kripke::Co[...]	stl_vector.h:992	exec
○	Kripke::SteadyStateSolver(Krip[...]	alloc_traits.h:941	exec
○	main	new_allocator.h:88	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	kripke.cpp:129	exec
○2.90	Kripke::SweepComm::readySubdom[...]	SweepComm.cpp:66	exec
►1.45+	Kripke::SweepComm::readySubdom[...]	SweepComm.cpp:66	exec
○	Kripke::SweepSolver(Kripke::Co[...]	stl_vector.h:992	exec
○	Kripke::SteadyStateSolver(Krip[...]	alloc_traits.h:941	exec
○	main	new_allocator.h:88	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_9

Source file and lines	ParallelComm.cpp:254-263
Module	exec

The function is defined in:

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_uninitialized.h:1101-1102
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:99,993,1908-1912
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp:254-263
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/new_allocator.h:126,151-156,172,191
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h:262
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/vector.tcc:114-119,581,614,649,687-695

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 3.50 to 0.23 cycles (15.14x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 24 bytes.

General properties

nb instructions	35
nb uops	28
loop length	125
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.33	1.33	1.33	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	1.00	1.33	1.33	1.33	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.50
Dispatch	1.33
Overall L1	3.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.50 cycles. At this rate:

1% of peak load performance is reached (4.57 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.86 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.50 to 1.33 cycles (2.63x speedup).

ASM code

In the binary file, the address of the function is: 4f0dc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x70(%RSI),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOVQ $0,(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ $0,0x8(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ $0,0x10(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP 0x78(%RSI),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JE 4f0e50 <_ZN6Kripke12ParallelComm12getReadyListEv+0x90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 4f0e13 <_ZN6Kripke12ParallelComm12getReadyListEv+0x53>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 41545c <_ZN6Kripke12ParallelComm12getReadyListEv.cold+0xc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_9

Source file and lines	ParallelComm.cpp:254-263
Module	exec

The function is defined in:

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_uninitialized.h:1101-1102
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:99,993,1908-1912
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp:254-263
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/new_allocator.h:126,151-156,172,191
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h:262
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/vector.tcc:114-119,581,614,649,687-695

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 24 bytes.

General properties

nb instructions	35
nb uops	28
loop length	125
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.33	1.33	1.33	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	1.00	1.33	1.33	1.33	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.50
Dispatch	1.33
Overall L1	3.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.50 cycles. At this rate:

1% of peak load performance is reached (4.57 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.86 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4f0dc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x70(%RSI),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOVQ $0,(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ $0,0x8(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ $0,0x10(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP 0x78(%RSI),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JE 4f0e50 <_ZN6Kripke12ParallelComm12getReadyListEv+0x90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 4f0e13 <_ZN6Kripke12ParallelComm12getReadyListEv+0x53>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 41545c <_ZN6Kripke12ParallelComm12getReadyListEv.cold+0xc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼Kripke::ParallelComm::getReadyList()–	0.01	0.00
▼Loop 2560 - new_allocator.h:126-191 - exec–	0.01	0.03
○Loop 2561 - new_allocator.h:191-191 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code