OV - exec - Loop 2043

	Loop Id: 2043	Module: exec	Source: For.hpp:137-137 [...]	Coverage: 0.04%

0x49fe00 LEA	0x1(%RDX),%RAX

0x49fe04 CMP	-0xf8(%RBP),%RDX

0x49fe0b MOV	%RAX,%RDX

0x49fe0e JE	49fd20

0x49fe14 CMPQ	$0,-0x48(%RBP)

0x49fe19 JLE	49fe00

0x49fe1b MOV	-0xe8(%RBP),%RAX

0x49fe22 MOV	-0xf0(%RBP),%RCX

0x49fe29 MOV	(%RAX,%RCX,8),%R8

0x49fe2d IMUL	-0xd8(%RBP),%R8

0x49fe35 ADD	-0x70(%RBP),%R8

0x49fe39 ADD	-0xe0(%RBP),%R8

0x49fe40 MOV	-0x68(%RBP),%RAX

0x49fe44 IMUL	%RDX,%RAX

0x49fe48 MOV	%RAX,-0x140(%RBP)

0x49fe4f MOV	-0x78(%RBP),%RAX

0x49fe53 ADD	%R8,%RAX

0x49fe56 ADD	%RDX,%RAX

0x49fe59 XOR	%ECX,%ECX

0x49fe5b JMP	49fead

  (2044) 0x49fe60 XORPD	%XMM0,%XMM0

  (2044) 0x49fe64 MOV	-0x140(%RBP),%RSI

  (2044) 0x49fe6b ADD	%RCX,%RSI

  (2044) 0x49fe6e ADD	-0x138(%RBP),%RSI

  (2044) 0x49fe75 MOV	-0x120(%RBP),%RDI

  (2044) 0x49fe7c MULSD	(%RDI,%RSI,8),%XMM0

  (2044) 0x49fe81 MOV	-0x130(%RBP),%RSI

  (2044) 0x49fe88 ADD	%RCX,%RSI

  (2044) 0x49fe8b ADDSD	(%R13,%RSI,8),%XMM0

  (2044) 0x49fe92 MOVSD	%XMM0,(%R13,%RSI,8)

  (2044) 0x49fe99 LEA	0x1(%RCX),%RSI

  (2044) 0x49fe9d CMP	-0x118(%RBP),%RCX

  (2044) 0x49fea4 MOV	%RSI,%RCX

  (2044) 0x49fea7 JE	49fe00

  (2044) 0x49fead MOV	-0x50(%RBP),%RSI

  (2044) 0x49feb1 LEA	(%RSI,%RCX,1),%RDI

  (2044) 0x49feb5 MOV	-0x128(%RBP),%RSI

  (2044) 0x49febc MOVSXD	(%RSI,%RDI,4),%RSI

  (2044) 0x49fec0 TEST	%RSI,%RSI

  (2044) 0x49fec3 JLE	49fe60

  (2044) 0x49fec5 MOV	-0x110(%RBP),%R9

  (2044) 0x49fecc MOV	(%R9,%RDI,8),%R11

  (2044) 0x49fed0 ADD	%R11,%RSI

  (2044) 0x49fed3 LEA	0x1(%R11),%RDI

  (2044) 0x49fed7 CMP	%RDI,%RSI

  (2044) 0x49feda CMOVLE	%RDI,%RSI

  (2044) 0x49fede SUB	%R11,%RSI

  (2044) 0x49fee1 XORPD	%XMM0,%XMM0

  (2044) 0x49fee5 CMP	$0x4,%RSI

  (2044) 0x49fee9 JB	49ff7b

  (2044) 0x49feef MOV	%RSI,%R9

  (2044) 0x49fef2 SHR	$0x2,%R9

  (2044) 0x49fef6 LEA	0x18(,%R11,8),%RDI

  (2044) 0x49fefe XCHG	%AX,%AX

    (2045) 0x49ff00 MOV	-0x18(%RBX,%RDI,1),%R10

    (2045) 0x49ff05 IMUL	%R15,%R10

    (2045) 0x49ff09 ADD	%RAX,%R10

    (2045) 0x49ff0c MOVSD	(%R14,%R10,8),%XMM1

    (2045) 0x49ff12 MULSD	-0x18(%R12,%RDI,1),%XMM1

    (2045) 0x49ff19 MOV	-0x10(%RBX,%RDI,1),%R10

    (2045) 0x49ff1e IMUL	%R15,%R10

    (2045) 0x49ff22 ADD	%RAX,%R10

    (2045) 0x49ff25 MOVSD	(%R14,%R10,8),%XMM2

    (2045) 0x49ff2b MULSD	-0x10(%R12,%RDI,1),%XMM2

    (2045) 0x49ff32 MOV	-0x8(%RBX,%RDI,1),%R10

    (2045) 0x49ff37 IMUL	%R15,%R10

    (2045) 0x49ff3b ADD	%RAX,%R10

    (2045) 0x49ff3e MOVSD	(%R14,%R10,8),%XMM3

    (2045) 0x49ff44 MULSD	-0x8(%R12,%RDI,1),%XMM3

    (2045) 0x49ff4b ADDSD	%XMM0,%XMM1

    (2045) 0x49ff4f ADDSD	%XMM2,%XMM3

    (2045) 0x49ff53 MOV	(%RBX,%RDI,1),%R10

    (2045) 0x49ff57 IMUL	%R15,%R10

    (2045) 0x49ff5b ADD	%RAX,%R10

    (2045) 0x49ff5e MOVSD	(%R14,%R10,8),%XMM0

    (2045) 0x49ff64 MULSD	(%R12,%RDI,1),%XMM0

    (2045) 0x49ff6a ADDSD	%XMM1,%XMM3

    (2045) 0x49ff6e ADDSD	%XMM3,%XMM0

    (2045) 0x49ff72 ADD	$0x20,%RDI

    (2045) 0x49ff76 DEC	%R9

    (2045) 0x49ff79 JNE	49ff00

  (2044) 0x49ff7b MOV	%RSI,%RDI

  (2044) 0x49ff7e AND	$-0x4,%RDI

  (2044) 0x49ff82 AND	$0x3,%ESI

  (2044) 0x49ff85 CMP	$0x1,%RSI

  (2044) 0x49ff89 JE	49fffc

  (2044) 0x49ff8b CMP	$0x3,%ESI

  (2044) 0x49ff8e JE	49ffa5

  (2044) 0x49ff90 CMP	$0x2,%ESI

  (2044) 0x49ff93 JNE	49fe64

  (2044) 0x49ff99 ADD	%RDI,%R11

  (2044) 0x49ff9c MOV	-0x100(%RBP),%RSI

  (2044) 0x49ffa3 JMP	49ffd6

  (2044) 0x49ffa5 ADD	%RDI,%R11

  (2044) 0x49ffa8 MOV	0x10(%RBX,%R11,8),%RSI

  (2044) 0x49ffad IMUL	%R15,%RSI

  (2044) 0x49ffb1 MOV	-0x108(%RBP),%R9

  (2044) 0x49ffb8 LEA	(%R8,%R9,1),%RDI

  (2044) 0x49ffbc ADD	%RDX,%RDI

  (2044) 0x49ffbf ADD	%RSI,%RDI

  (2044) 0x49ffc2 MOVSD	(%R14,%RDI,8),%XMM1

  (2044) 0x49ffc8 MULSD	0x10(%R12,%R11,8),%XMM1

  (2044) 0x49ffcf ADDSD	%XMM1,%XMM0

  (2044) 0x49ffd3 MOV	%R9,%RSI

  (2044) 0x49ffd6 MOV	0x8(%RBX,%R11,8),%RDI

  (2044) 0x49ffdb IMUL	%R15,%RDI

  (2044) 0x49ffdf LEA	(%R8,%RSI,1),%R9

  (2044) 0x49ffe3 ADD	%RDX,%R9

  (2044) 0x49ffe6 ADD	%RDI,%R9

  (2044) 0x49ffe9 MOVSD	(%R14,%R9,8),%XMM1

  (2044) 0x49ffef MULSD	0x8(%R12,%R11,8),%XMM1

  (2044) 0x49fff6 ADDSD	%XMM1,%XMM0

  (2044) 0x49fffa JMP	4a0003

  (2044) 0x49fffc ADD	%RDI,%R11

  (2044) 0x49ffff MOV	-0x78(%RBP),%RSI

  (2044) 0x4a0003 MOV	(%RBX,%R11,8),%RDI

  (2044) 0x4a0007 IMUL	%R15,%RDI

  (2044) 0x4a000b ADD	%R8,%RSI

  (2044) 0x4a000e ADD	%RDX,%RSI

  (2044) 0x4a0011 ADD	%RDI,%RSI

  (2044) 0x4a0014 MOVSD	(%R14,%RSI,8),%XMM1

  (2044) 0x4a001a MULSD	(%R12,%R11,8),%XMM1

  (2044) 0x4a0020 ADDSD	%XMM1,%XMM0

  (2044) 0x4a0024 JMP	49fe64

/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/IndexValue.hpp: 109 - 221

--------------------------------------------------------------------------------

109:     return TYPE(value + a);

[...]

221:     return (value < x.value);

/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp: 137 - 137

--------------------------------------------------------------------------------

137:     for (decltype(distance_it) i = 0; i < distance_it; ++i) {

/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/src/Kripke/Kernel/Scattering.cpp: 87 - 97

--------------------------------------------------------------------------------

87:             MixElem mix_start = zone_to_mixelem(z);

88:             MixElem mix_stop = mix_start + zone_to_num_mixelem(z);

89:

90:             double sigs_z = 0.0;

91:             for(MixElem mix = mix_start;mix < mix_stop;++ mix){

92:               Material mat = mixelem_to_material(mix);

93:               double fraction = mixelem_to_fraction(mix);

94:

95:               sigs_z += sigs(mat, n, global_g, global_gp) * fraction;

96:             }

97:             phi_out(nm, g, z) += sigs_z * phi(nm, gp, z);

/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp: 190 - 190

--------------------------------------------------------------------------------

190:          strides[RangeInts]*indices // it's not stride one

/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp: 74 - 74

--------------------------------------------------------------------------------

74: #pragma omp parallel for private(i0, i1) firstprivate(privatizer) \

Coverage (%)	Name	Source Location	Module
►91.47+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►5.25+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
►1.53+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	scattering	Collapse.hpp:74	exec
○	SteadyStateSolver	SteadyStateSolver.cpp:73	exec
○	main	kripke.cpp:504	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	kripke.cpp:0	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	P6, P7, P8, P9,
Function	void Kripke::DispatchHelper::operator()&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&>(Kripke::LayoutT_DGZ, ScatteringSdom const&, Kripke::SdomId&, Kripke::SdomId&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source	For.hpp:137-137,Scattering.cpp:95-97,Layout.hpp:190-190
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.75
CQA cycles if no scalar integer	2.75
CQA cycles if FP arith vectorized	2.75
CQA cycles if fully vectorized	0.34
Front-end cycles	2.50
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	2.75
P7 cycles	2.75
P8 cycles	2.75
P9 cycles	2.75
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	20.00
Nb loads	10.00
Nb stores	1.00
Nb stack references	10.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	P6, P7, P8, P9,
Function	void Kripke::DispatchHelper::operator()&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&>(Kripke::LayoutT_DGZ, ScatteringSdom const&, Kripke::SdomId&, Kripke::SdomId&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source	For.hpp:137-137,Scattering.cpp:95-97,Layout.hpp:190-190
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.75
CQA cycles if no scalar integer	2.75
CQA cycles if FP arith vectorized	2.75
CQA cycles if fully vectorized	0.34
Front-end cycles	2.50
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	2.75
P7 cycles	2.75
P8 cycles	2.75
P9 cycles	2.75
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	20.00
Nb loads	10.00
Nb stores	1.00
Nb stack references	10.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void Kripke::DispatchHelper::operator()&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&>(Kripke::LayoutT_DGZ, ScatteringSdom const&, Kripke::SdomId&, Kripke::SdomId&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source file and lines	For.hpp:137-137
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/IndexValue.hpp:109,221
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:137
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/src/Kripke/Kernel/Scattering.cpp:87-97
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:190
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:74

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=10
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 10 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 2.75 to 0.34 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 2.75 to 2.50 cycles (1.10x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 80 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	20
nb uops	20
loop length	93
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.50 cycles
front end	2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.00	2.00	2.00	2.00	2.00	2.00	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.00	2.00	2.00	2.00	2.00	2.00	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.50
Dispatch	2.75
Overall L1	2.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.75 cycles. At this rate:

11% of peak load performance is reached (29.09 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.91 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 49fe14

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
LEA 0x1(%RDX),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
CMP -0xf8(%RBP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 49fd20 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x230>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPQ $0,-0x48(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JLE 49fe00 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x310>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0xe8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0xf0(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX,%RCX,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
IMUL -0xd8(%RBP),%R8	1	0.33	0.33	0.33	0	0	0	0.25	0.25	0.25	0.25	3	0.33	scal (12.5%)
ADD -0x70(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
ADD -0xe0(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
MOV -0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RDX,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RAX,-0x140(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x78(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %R8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 49fead <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Function	void Kripke::DispatchHelper::operator()&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&>(Kripke::LayoutT_DGZ, ScatteringSdom const&, Kripke::SdomId&, Kripke::SdomId&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source file and lines	For.hpp:137-137
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/IndexValue.hpp:109,221
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:137
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/src/Kripke/Kernel/Scattering.cpp:87-97
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:190
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:74

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=10
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 2.75 to 0.34 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 2.75 to 2.50 cycles (1.10x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 80 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	20
nb uops	20
loop length	93
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.50 cycles
front end	2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.00	2.00	2.00	2.00	2.00	2.00	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.00	2.00	2.00	2.00	2.00	2.00	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.50
Dispatch	2.75
Overall L1	2.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.75 cycles. At this rate:

11% of peak load performance is reached (29.09 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.91 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 49fe14

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
LEA 0x1(%RDX),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
CMP -0xf8(%RBP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 49fd20 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x230>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPQ $0,-0x48(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JLE 49fe00 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x310>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0xe8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0xf0(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX,%RCX,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
IMUL -0xd8(%RBP),%R8	1	0.33	0.33	0.33	0	0	0	0.25	0.25	0.25	0.25	3	0.33	scal (12.5%)
ADD -0x70(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
ADD -0xe0(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
MOV -0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RDX,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RAX,-0x140(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x78(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %R8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 49fead <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code