OV - exec - Function _ZN6Kripke12ParallelComm12getReadyListEv.A

	Function: _ZN6Kripke12ParallelComm12getReadyListEv.A	Module: exec	Source: ParallelComm.cpp:254-263 [...]	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h: 127 - 162

--------------------------------------------------------------------------------

127: 	return static_cast<_Tp*>(::operator new(__n * sizeof(_Tp)));

[...]

145: 	::operator delete(__p

[...]

162: 	{ ::new((void *)__p) _Up(std::forward<_Args>(__args)...); }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 98 - 1762

--------------------------------------------------------------------------------

98: 	: _M_start(), _M_finish(), _M_end_of_storage()

[...]

346: 	return __n != 0 ? _Tr::allocate(_M_impl, __n) : pointer();

[...]

353: 	if (__p)

[...]

919:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1046: 	return *(this->_M_impl._M_start + __n);

[...]

1758: 	if (max_size() - size() < __n)

1759: 	  __throw_length_error(__N(__s));

1760:

1761: 	const size_type __len = size() + (std::max)(size(), __n);

1762: 	return (__len < size() || __len > max_size()) ? max_size() : __len;

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h: 259 - 259

--------------------------------------------------------------------------------

259:       if (__a < __b)

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_uninitialized.h: 1031 - 1031

--------------------------------------------------------------------------------

1031:       for (; __first != __last; ++__first, (void)++__cur)

/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp: 254 - 263

--------------------------------------------------------------------------------

254: std::vector<SdomId> ParallelComm::getReadyList(void){

255:   // build up a list of ready subdomains

256:   std::vector<SdomId> ready;

257:   for(size_t i = 0;i < queue_depends.size();++ i){

258:     if(queue_depends[i] == 0){

259:       ready.push_back(SdomId(queue_sdom_ids[i]));

260:     }

261:   }

262:   return ready;

263: }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/vector.tcc: 112 - 504

--------------------------------------------------------------------------------

112: 	if (this->_M_impl._M_finish != this->_M_impl._M_end_of_storage)

113: 	  {

114: 	    _GLIBCXX_ASAN_ANNOTATE_GROW(1);

115: 	    _Alloc_traits::construct(this->_M_impl, this->_M_impl._M_finish,

116: 				     std::forward<_Args>(__args)...);

117: 	    ++this->_M_impl._M_finish;

[...]

502:       this->_M_impl._M_start = __new_start;

503:       this->_M_impl._M_finish = __new_finish;

504:       this->_M_impl._M_end_of_storage = __new_start + __len;

0x4ecbe0 PUSH	%RBP

0x4ecbe1 MOV	%RSP,%RBP

0x4ecbe4 PUSH	%R15

0x4ecbe6 PUSH	%R14

0x4ecbe8 PUSH	%R13

0x4ecbea PUSH	%R12

0x4ecbec PUSH	%RBX

0x4ecbed SUB	$0x18,%RSP

0x4ecbf1 XORPS	%XMM0,%XMM0

0x4ecbf4 MOVUPS	%XMM0,(%RDI)

0x4ecbf7 MOV	%RDI,-0x30(%RBP)

0x4ecbfb MOVQ	$0,0x10(%RDI)

0x4ecc03 MOV	0x70(%RSI),%RCX

0x4ecc07 CMP	%RCX,0x78(%RSI)

0x4ecc0b JE	4ecd4d

0x4ecc11 XOR	%R13D,%R13D

0x4ecc14 XOR	%R14D,%R14D

0x4ecc17 XOR	%EAX,%EAX

0x4ecc19 XOR	%R15D,%R15D

0x4ecc1c MOV	%RSI,-0x40(%RBP)

0x4ecc20 JMP	4ecc60

0x4ecc22 NOPW	%CS:(%RAX,%RAX,1)

(2756) 0x4ecc30 MOV	%RDI,(%R14)

(2756) 0x4ecc33 ADD	$0x8,%R14

(2756) 0x4ecc37 MOV	-0x30(%RBP),%RCX

(2756) 0x4ecc3b MOV	%R14,0x8(%RCX)

(2756) 0x4ecc3f MOV	%R15,%R12

(2756) 0x4ecc42 INC	%R13

(2756) 0x4ecc45 MOV	0x70(%RSI),%RCX

(2756) 0x4ecc49 MOV	0x78(%RSI),%RDX

(2756) 0x4ecc4d SUB	%RCX,%RDX

(2756) 0x4ecc50 SAR	$0x2,%RDX

(2756) 0x4ecc54 MOV	%R12,%R15

(2756) 0x4ecc57 CMP	%RDX,%R13

(2756) 0x4ecc5a JAE	4ecd4d

(2756) 0x4ecc60 CMPL	$0,(%RCX,%R13,4)

(2756) 0x4ecc65 JNE	4ecc3f

(2756) 0x4ecc67 MOV	0x58(%RSI),%RCX

(2756) 0x4ecc6b MOVSXD	(%RCX,%R13,4),%RDI

(2756) 0x4ecc6f CMP	%RAX,%R14

(2756) 0x4ecc72 JNE	4ecc30

(2756) 0x4ecc74 MOV	%R14,%RBX

(2756) 0x4ecc77 SUB	%R15,%RBX

(2756) 0x4ecc7a MOV	$0x7ffffffffffffff8,%RAX

(2756) 0x4ecc84 CMP	%RAX,%RBX

(2756) 0x4ecc87 JE	4ecd60

(2756) 0x4ecc8d SAR	$0x3,%RBX

(2756) 0x4ecc91 CMP	%R15,%R14

(2756) 0x4ecc94 MOV	%RBX,%RAX

(2756) 0x4ecc97 MOV	$0x1,%ECX

(2756) 0x4ecc9c CMOVE	%RCX,%RAX

(2756) 0x4ecca0 MOV	$0xfffffffffffffff,%RDX

(2756) 0x4eccaa ADD	%RBX,%RAX

(2756) 0x4eccad JB	4eccc9

(2756) 0x4eccaf MOV	$0xfffffffffffffff,%RCX

(2756) 0x4eccb9 MOV	%RCX,%RDX

(2756) 0x4eccbc CMP	%RCX,%RAX

(2756) 0x4eccbf JA	4eccc9

(2756) 0x4eccc1 MOV	%RAX,%RDX

(2756) 0x4eccc4 TEST	%RAX,%RAX

(2756) 0x4eccc7 JE	4ecd42

(2756) 0x4eccc9 MOV	%RDX,-0x38(%RBP)

(2756) 0x4ecccd MOV	%RDI,%R12

(2756) 0x4eccd0 LEA	(,%RDX,8),%RDI

(2756) 0x4eccd8 CALL	403270 <_Znwm@plt>

(2756) 0x4eccdd MOV	%R12,%RDI

(2756) 0x4ecce0 MOV	%RAX,%R12

(2756) 0x4ecce3 MOV	%RDI,(%R12,%RBX,8)

(2756) 0x4ecce7 MOV	%R12,%RBX

(2756) 0x4eccea SUB	%R15,%R14

(2756) 0x4ecced JE	4ecd0e

(2756) 0x4eccef ADD	$-0x8,%R14

(2756) 0x4eccf3 AND	$-0x8,%R14

(2756) 0x4eccf7 LEA	0x8(%R14),%RDX

(2756) 0x4eccfb MOV	%R12,%RDI

(2756) 0x4eccfe MOV	%R15,%RSI

(2756) 0x4ecd01 CALL	4f5800 <_intel_fast_memcpy>

(2756) 0x4ecd06 LEA	(%R14,%R12,1),%RBX

(2756) 0x4ecd0a ADD	$0x8,%RBX

(2756) 0x4ecd0e TEST	%R15,%R15

(2756) 0x4ecd11 JE	4ecd1b

(2756) 0x4ecd13 MOV	%R15,%RDI

(2756) 0x4ecd16 CALL	403260 <_ZdlPv@plt>

(2756) 0x4ecd1b ADD	$0x8,%RBX

(2756) 0x4ecd1f MOV	-0x30(%RBP),%RCX

(2756) 0x4ecd23 MOV	%R12,(%RCX)

(2756) 0x4ecd26 MOV	%RBX,0x8(%RCX)

(2756) 0x4ecd2a MOV	-0x38(%RBP),%RAX

(2756) 0x4ecd2e LEA	(%R12,%RAX,8),%RAX

(2756) 0x4ecd32 MOV	%RAX,0x10(%RCX)

(2756) 0x4ecd36 MOV	%RBX,%R14

(2756) 0x4ecd39 MOV	-0x40(%RBP),%RSI

(2756) 0x4ecd3d JMP	4ecc42

(2756) 0x4ecd42 XOR	%EAX,%EAX

(2756) 0x4ecd44 MOV	%RAX,-0x38(%RBP)

(2756) 0x4ecd48 XOR	%R12D,%R12D

(2756) 0x4ecd4b JMP	4ecce3

0x4ecd4d MOV	-0x30(%RBP),%RAX

0x4ecd51 ADD	$0x18,%RSP

0x4ecd55 POP	%RBX

0x4ecd56 POP	%R12

0x4ecd58 POP	%R13

0x4ecd5a POP	%R14

0x4ecd5c POP	%R15

0x4ecd5e POP	%RBP

0x4ecd5f RET

0x4ecd60 LEA	0x1868f(%RIP),%RDI

0x4ecd67 CALL	403160 <_ZSt20__throw_length_errorPKc@plt>

0x4ecd6c JMP	4ecd6e

0x4ecd6e MOV	%RAX,%RBX

0x4ecd71 TEST	%R15,%R15

0x4ecd74 JE	4ecd7e

0x4ecd76 MOV	%R15,%RDI

0x4ecd79 CALL	403260 <_ZdlPv@plt>

0x4ecd7e MOV	%RBX,%RDI

0x4ecd81 CALL	403500 <_Unwind_Resume@plt>

0x4ecd86 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►97.22+	Kripke::ParallelComm::getReady[...]	new_allocator.h:145	exec
○	Kripke::SweepComm::readySubdom[...]	SweepComm.cpp:65	exec
○	SweepSolver	stl_vector.h:919	exec
○	SteadyStateSolver	stl_vector.h:335	exec
○	main	kripke.cpp:504	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	kripke.cpp:0	exec
►2.78+	Kripke::ParallelComm::getReady[...]	new_allocator.h:145	exec
○	Kripke::SweepComm::readySubdom[...]	SweepComm.cpp:65	exec
○	SweepSolver	stl_vector.h:919	exec
○	SteadyStateSolver	stl_vector.h:335	exec
○	main	kripke.cpp:504	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_10

Source file and lines	ParallelComm.cpp:254-263
Module	exec

The function is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:127,145,162
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:98,346,353,919,1046,1758-1762
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:259
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_uninitialized.h:1031
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp:254-263
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/vector.tcc:112-117,502-504

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.38 to 0.67 cycles (8.06x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 5.38 to 0.41 cycles (13.18x speedup).

Details

16% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
25% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
20% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

_Unwind_Resume@plt: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:145
operator delete(void*): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:145
std::__throw_length_error(char const*): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1759

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

MOVUPS: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:98

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	42
nb uops	43
loop length	147
used x86 registers	11
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.38 cycles
front end	5.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.67	1.67	1.67	2.67	2.67	2.67	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	0.50	0.50
cycles	1.67	1.67	1.67	2.67	2.67	2.67	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.38
Dispatch	2.67
Overall L1	5.38

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	16%
load	0%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	10%
load	12%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	13%
load	12%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.38 cycles. At this rate:

1% of peak load performance is reached (4.47 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.44 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.38 to 2.67 cycles (2.02x speedup).

ASM code

In the binary file, the address of the function is: 4ecbe0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
XORPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVUPS %XMM0,(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (25.0%)
MOV %RDI,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOVQ $0,0x10(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV 0x70(%RSI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
CMP %RCX,0x78(%RSI)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JE 4ecd4d <_ZN6Kripke12ParallelComm12getReadyListEv.A+0x16d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
JMP 4ecc60 <_ZN6Kripke12ParallelComm12getReadyListEv.A+0x80>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
ADD $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
LEA 0x1868f(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
CALL 403160 <_ZSt20__throw_length_errorPKc@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
JMP 4ecd6e <_ZN6Kripke12ParallelComm12getReadyListEv.A+0x18e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
TEST %R15,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JE 4ecd7e <_ZN6Kripke12ParallelComm12getReadyListEv.A+0x19e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 403260 <_ZdlPv@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 403500 <_Unwind_Resume@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_10

Source file and lines	ParallelComm.cpp:254-263
Module	exec

The function is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:127,145,162
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:98,346,353,919,1046,1758-1762
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:259
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_uninitialized.h:1031
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp:254-263
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/vector.tcc:112-117,502-504

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.38 to 0.67 cycles (8.06x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

16% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
25% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
20% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

_Unwind_Resume@plt: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:145
operator delete(void*): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:145
std::__throw_length_error(char const*): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1759

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

MOVUPS: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:98

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	42
nb uops	43
loop length	147
used x86 registers	11
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.38 cycles
front end	5.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.67	1.67	1.67	2.67	2.67	2.67	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	0.50	0.50
cycles	1.67	1.67	1.67	2.67	2.67	2.67	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.38
Dispatch	2.67
Overall L1	5.38

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	16%
load	0%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	10%
load	12%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	13%
load	12%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.38 cycles. At this rate:

1% of peak load performance is reached (4.47 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.44 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4ecbe0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
XORPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVUPS %XMM0,(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (25.0%)
MOV %RDI,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOVQ $0,0x10(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV 0x70(%RSI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
CMP %RCX,0x78(%RSI)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JE 4ecd4d <_ZN6Kripke12ParallelComm12getReadyListEv.A+0x16d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
JMP 4ecc60 <_ZN6Kripke12ParallelComm12getReadyListEv.A+0x80>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
ADD $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
LEA 0x1868f(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
CALL 403160 <_ZSt20__throw_length_errorPKc@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
JMP 4ecd6e <_ZN6Kripke12ParallelComm12getReadyListEv.A+0x18e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
TEST %R15,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JE 4ecd7e <_ZN6Kripke12ParallelComm12getReadyListEv.A+0x19e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 403260 <_ZdlPv@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 403500 <_Unwind_Resume@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼_ZN6Kripke12ParallelComm12getReadyListEv.A–	0.01	0.00
○Loop 2756 - vector.tcc:112-504 - exec	0.01	0.05

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code