OV - exec - Loop 545

	Loop Id: 545	Module: exec	Source: Collapse.hpp:74-76 [...]	Coverage: 0.01%

0x24a210 MOV	%RCX,%RAX

0x24a213 CQTO

0x24a215 IDIVQ	-0x98(%RBP)

0x24a21c MOV	-0x48(%RBP),%R8

0x24a220 ADD	-0x88(%RBP),%RDX

0x24a227 IMUL	%RDX,%R8

0x24a22b IMUL	-0x70(%RBP),%RDX

0x24a230 ADD	-0x50(%RBP),%R8

0x24a234 ADD	-0x30(%RBP),%RDX

0x24a238 ADD	-0x90(%RBP),%RAX

0x24a23f MOV	%RAX,%R9

0x24a242 IMUL	-0x78(%RBP),%R9

0x24a247 ADD	%R9,%RDX

0x24a24a MOV	-0x80(%RBP),%R9

0x24a24e LEA	(%R9,%RDX,8),%RDX

0x24a252 XOR	%R9D,%R9D

0x24a255 NOPW	%CS:(%RAX,%RAX,1)

  (544) 0x24a260 LEA	(%R9,%R13,1),%R10

  (544) 0x24a264 XOR	%R11D,%R11D

  (544) 0x24a267 IMUL	%R12,%R10

  (544) 0x24a26b ADD	%RAX,%R10

  (544) 0x24a26e XCHG	%AX,%AX

    (543) 0x24a270 VMOVSD	(%RBX,%R10,8),%XMM0

    (543) 0x24a276 VMOVSD	(%R8,%R11,8),%XMM1

    (543) 0x24a27c VFMADD213SD	(%RDX,%R11,8),%XMM0,%XMM1

    (543) 0x24a282 VMOVSD	%XMM1,(%RDX,%R11,8)

    (543) 0x24a288 INC	%R11

    (543) 0x24a28b CMP	%R11,%RDI

    (543) 0x24a28e JNE	24a270

  (544) 0x24a290 INC	%R9

  (544) 0x24a293 ADD	%R15,%R8

  (544) 0x24a296 CMP	%RSI,%R9

  (544) 0x24a299 JNE	24a260

0x24a29b LEA	0x1(%RCX),%RAX

0x24a29f CMP	%R14,%RCX

0x24a2a2 MOV	%RAX,%RCX

0x24a2a5 JL	24a210

/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp: 137 - 137

--------------------------------------------------------------------------------

137:     for (decltype(distance_it) i = 0; i < distance_it; ++i) {

/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/src/Kripke/Kernel/LTimes.cpp: 62 - 62

--------------------------------------------------------------------------------

62:            phi(nm,g,z) += ell(nm, d) * psi(d, g, z);

/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp: 74 - 76

--------------------------------------------------------------------------------

74: #pragma omp parallel for private(i0, i1) firstprivate(privatizer) \

75:     RAJA_COLLAPSE(2)

76:     for (i0 = 0; i0 < l0; ++i0) {

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.80 - 4.80
Bottlenecks	P10, P11,
Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<1l, RAJA::policy::sequential::seq_exec, RAJA::statement::For<3l, RAJA::policy::sequential::seq_exec, RAJA::statement::Lambda<0l> > > >, RAJA::internal::LoopTypes, camp::list > >::exec, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, LTimesSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const::{lambda(Kripke::Moment, Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&>(RAJA::internal::LoopData, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, LTimesSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const::{lambda(Kripke::Moment, Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&) [clone .omp_outlined]
Source	For.hpp:137-137,Collapse.hpp:74-76
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00 - 12.00
CQA cycles if no scalar integer	7.00 - 12.00
CQA cycles if FP arith vectorized	7.00 - 12.00
CQA cycles if fully vectorized	0.88 - 1.50
Front-end cycles	2.50
P0 cycles	2.33
P1 cycles	2.33
P2 cycles	2.33
P3 cycles	2.33
P4 cycles	2.33
P5 cycles	2.33
P6 cycles	2.25
P7 cycles	2.25
P8 cycles	2.25
P9 cycles	2.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	7.00 - 12.00
Inter-iter dependencies cycles	7
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	20.00
Nb loads	9.00
Nb stores	0.00
Nb stack references	9.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.00 - 10.29
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	3.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.80 - 4.80
Bottlenecks	P10, P11,
Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<1l, RAJA::policy::sequential::seq_exec, RAJA::statement::For<3l, RAJA::policy::sequential::seq_exec, RAJA::statement::Lambda<0l> > > >, RAJA::internal::LoopTypes, camp::list > >::exec, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, LTimesSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const::{lambda(Kripke::Moment, Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&>(RAJA::internal::LoopData, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, LTimesSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const::{lambda(Kripke::Moment, Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&) [clone .omp_outlined]
Source	For.hpp:137-137,Collapse.hpp:74-76
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00 - 12.00
CQA cycles if no scalar integer	7.00 - 12.00
CQA cycles if FP arith vectorized	7.00 - 12.00
CQA cycles if fully vectorized	0.88 - 1.50
Front-end cycles	2.50
P0 cycles	2.33
P1 cycles	2.33
P2 cycles	2.33
P3 cycles	2.33
P4 cycles	2.33
P5 cycles	2.33
P6 cycles	2.25
P7 cycles	2.25
P8 cycles	2.25
P9 cycles	2.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	7.00 - 12.00
Inter-iter dependencies cycles	7
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	20.00
Nb loads	9.00
Nb stores	0.00
Nb stack references	9.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.00 - 10.29
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	3.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<1l, RAJA::policy::sequential::seq_exec, RAJA::statement::For<3l, RAJA::policy::sequential::seq_exec, RAJA::statement::Lambda<0l> > > >, RAJA::internal::LoopTypes, camp::list > >::exec, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, LTimesSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const::{lambda(Kripke::Moment, Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&>(RAJA::internal::LoopData, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, LTimesSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const::{lambda(Kripke::Moment, Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&) [clone .omp_outlined]
Source file and lines	Collapse.hpp:74-76
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:137
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/src/Kripke/Kernel/LTimes.cpp:62
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:74-76

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 2.50 cycles (4.80x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 7.00 cycles (1.71x speedup).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:74

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:74

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes.

General properties

nb instructions	21
nb uops	20
loop length	96
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.50 cycles
front end	2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.33	2.33	2.33	2.33	2.33	2.33	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.33	2.33	2.33	2.33	2.33	2.33	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	7.00-12.00
Longest recurrence chain latency (RecMII)	7.00

Cycles summary

Front-end	2.50
Dispatch	2.33
DIV/SQRT	7.00-12.00
Data deps.	7.00
Overall L1	7.00-12.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

2% of peak load performance is reached (6.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 24a210

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CQTO																				scal (12.5%)
IDIVQ -0x98(%RBP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	10-22	7-12	scal (12.5%)
MOV -0x48(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
ADD -0x88(%RBP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
IMUL %RDX,%R8	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
IMUL -0x70(%RBP),%RDX	1	0.33	0.33	0.33	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.33	N/A
ADD -0x50(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD -0x30(%RBP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD -0x90(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL -0x78(%RBP),%R9	1	0.33	0.33	0.33	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.33	N/A
ADD %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x80(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R9,%RDX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
LEA 0x1(%RCX),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R14,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JL 24a210 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPST_EElEENSP_INSR_INSS_9DirectionElPSX_EElEENSP_INSR_INSS_5GroupElPS11_EElEENSP_INSR_INSS_4ZoneElPS15_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK10LTimesSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdERKNSS_4Core3SetES1P_S1P_S1P_RNS1M_5FieldIdJSX_S11_S15_EEERNS1Q_IdJST_S11_S15_EEERNS1Q_IdJST_SX_EEEEUlST_SX_S11_S15_E_EEEEEvOS1K_.omp_outlined+0x180>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<1l, RAJA::policy::sequential::seq_exec, RAJA::statement::For<3l, RAJA::policy::sequential::seq_exec, RAJA::statement::Lambda<0l> > > >, RAJA::internal::LoopTypes, camp::list > >::exec, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, LTimesSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const::{lambda(Kripke::Moment, Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&>(RAJA::internal::LoopData, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, LTimesSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const::{lambda(Kripke::Moment, Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&) [clone .omp_outlined]
Source file and lines	Collapse.hpp:74-76
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:137
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/src/Kripke/Kernel/LTimes.cpp:62
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:74-76

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 7.00 cycles (1.71x speedup).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:74

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:74

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes.

General properties

nb instructions	21
nb uops	20
loop length	96
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.50 cycles
front end	2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.33	2.33	2.33	2.33	2.33	2.33	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.33	2.33	2.33	2.33	2.33	2.33	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	7.00-12.00
Longest recurrence chain latency (RecMII)	7.00

Cycles summary

Front-end	2.50
Dispatch	2.33
DIV/SQRT	7.00-12.00
Data deps.	7.00
Overall L1	7.00-12.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

2% of peak load performance is reached (6.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 24a210

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CQTO																				scal (12.5%)
IDIVQ -0x98(%RBP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	10-22	7-12	scal (12.5%)
MOV -0x48(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
ADD -0x88(%RBP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
IMUL %RDX,%R8	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
IMUL -0x70(%RBP),%RDX	1	0.33	0.33	0.33	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.33	N/A
ADD -0x50(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD -0x30(%RBP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD -0x90(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL -0x78(%RBP),%R9	1	0.33	0.33	0.33	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.33	N/A
ADD %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x80(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R9,%RDX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
LEA 0x1(%RCX),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R14,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JL 24a210 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPST_EElEENSP_INSR_INSS_9DirectionElPSX_EElEENSP_INSR_INSS_5GroupElPS11_EElEENSP_INSR_INSS_4ZoneElPS15_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK10LTimesSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdERKNSS_4Core3SetES1P_S1P_S1P_RNS1M_5FieldIdJSX_S11_S15_EEERNS1Q_IdJST_S11_S15_EEERNS1Q_IdJST_SX_EEEEUlST_SX_S11_S15_E_EEEEEvOS1K_.omp_outlined+0x180>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code