OV - exec - Loop 2248

	Loop Id: 2248	Module: exec	Source: :0-0	Coverage: 0.01%

0x48efd0 MOV	0x10(%RSP),%RAX

0x48efd5 MOV	0x18(%RSP),%RDI

0x48efda MOV	0x48(%RSP),%R8

0x48efdf LEA	(,%RAX,8),%RCX

0x48efe7 MOV	0x50(%RSP),%RAX

0x48efec LEA	(%RAX,%RCX,1),%R10

0x48eff0 MOV	0x58(%RSP),%RAX

0x48eff5 LEA	(%RAX,%RDI,8),%RDX

0x48eff9 MOV	0x60(%RSP),%RAX

0x48effe XOR	%EDI,%EDI

0x48f000 LEA	(%RCX,%RAX,1),%R9

0x48f004 MOV	0x68(%RSP),%RAX

0x48f009 ADD	%RAX,%RCX

0x48f00c MOV	0x40(%RSP),%RAX

0x48f011 NOPW	%CS:(%RAX,%RAX,1)

0x48f01c NOPL	(%RAX)

  (2247) 0x48f020 MOVSD	(%RAX),%XMM4

  (2247) 0x48f024 MOVSD	(%R12),%XMM3

  (2247) 0x48f02a ADD	$0x1,%RDI

  (2247) 0x48f02e MOVSD	(%RBP),%XMM1

  (2247) 0x48f033 MOVSD	(%RSI),%XMM0

  (2247) 0x48f037 ADDSD	%XMM3,%XMM3

  (2247) 0x48f03b DIVSD	(%R11),%XMM3

  (2247) 0x48f040 MULSD	%XMM3,%XMM4

  (2247) 0x48f044 MOVSD	(%R13),%XMM2

  (2247) 0x48f04a ADDSD	%XMM1,%XMM1

  (2247) 0x48f04e DIVSD	(%R8),%XMM1

  (2247) 0x48f053 MULSD	%XMM1,%XMM0

  (2247) 0x48f057 ADD	%R15,%R8

  (2247) 0x48f05a ADDSD	(%R10),%XMM0

  (2247) 0x48f05f ADDSD	%XMM2,%XMM2

  (2247) 0x48f063 DIVSD	(%R14),%XMM2

  (2247) 0x48f068 ADD	%RBX,%R10

  (2247) 0x48f06b ADDSD	%XMM3,%XMM1

  (2247) 0x48f06f ADDSD	%XMM4,%XMM0

  (2247) 0x48f073 MOVSD	(%RDX),%XMM4

  (2247) 0x48f077 ADDSD	%XMM2,%XMM1

  (2247) 0x48f07b ADDSD	(%R9),%XMM1

  (2247) 0x48f080 ADD	%RBX,%R9

  (2247) 0x48f083 MULSD	%XMM2,%XMM4

  (2247) 0x48f087 ADDSD	%XMM4,%XMM0

  (2247) 0x48f08b DIVSD	%XMM1,%XMM0

  (2247) 0x48f08f MOVSD	%XMM0,(%RCX)

  (2247) 0x48f093 ADDSD	%XMM0,%XMM0

  (2247) 0x48f097 ADD	%RBX,%RCX

  (2247) 0x48f09a MOVAPD	%XMM0,%XMM1

  (2247) 0x48f09e SUBSD	(%RSI),%XMM1

  (2247) 0x48f0a2 MOVSD	%XMM1,(%RSI)

  (2247) 0x48f0a6 MOVAPD	%XMM0,%XMM1

  (2247) 0x48f0aa SUBSD	(%RAX),%XMM1

  (2247) 0x48f0ae MOVSD	%XMM1,(%RAX)

  (2247) 0x48f0b2 SUBSD	(%RDX),%XMM0

  (2247) 0x48f0b6 ADD	%R15,%RAX

  (2247) 0x48f0b9 MOVSD	%XMM0,(%RDX)

  (2247) 0x48f0bd ADD	%R15,%RDX

  (2247) 0x48f0c0 CMP	%RDI,(%RSP)

  (2247) 0x48f0c4 JG	48f020

0x48f0ca MOV	0x20(%RSP),%RDI

0x48f0cf ADDQ	$0x1,0x8(%RSP)

0x48f0d5 MOV	0x30(%RSP),%RDX

0x48f0da MOV	0x38(%RSP),%RCX

0x48f0df ADD	%RDX,0x10(%RSP)

0x48f0e4 MOV	0x8(%RSP),%RAX

0x48f0e9 ADD	%RDI,%R11

0x48f0ec ADD	%RDI,%RSI

0x48f0ef ADD	%RCX,0x18(%RSP)

0x48f0f4 CMP	%RAX,0x28(%RSP)

0x48f0f9 JG	48efd0

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

Coverage (%)	Name	Source Location	Module
►92.06+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►7.94+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	void Kripke::DispatchHelper<Kr[...]		exec
○	Kripke::Kernel::sweepSubdomain[...]		exec
○	Kripke::SweepSolver(Kripke::Co[...]		exec
○	Kripke::SteadyStateSolver(Krip[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P6, P7, P8, P9,
Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<2l, RAJA::policy::sequential::seq_exec, RAJA::statement::For<3l, RAJA::policy::sequential::seq_exec, RAJA::statement::For<4l, RAJA::policy::sequential::seq_exec, RAJA::statement::Lambda<0l> > > > >, RAJA::internal::LoopTypes, camp::list > >::exec, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, SweepSdom::operator() >(Kripke::ArchLayoutT, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&>(RAJA::internal::LoopData, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, SweepSdom::operator() >(Kripke::ArchLayoutT, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&) [clone ._omp_fn.0]
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	0.50
Front-end cycles	3.00
P0 cycles	1.83
P1 cycles	1.83
P2 cycles	1.83
P3 cycles	1.83
P4 cycles	1.83
P5 cycles	1.83
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	24.00
Nb loads	16.00
Nb stores	3.00
Nb stack references	13.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	38.00
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	24.00
Stride 0	5.00
Stride 1	0.00
Stride n	0.00
Stride unknown	8.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P6, P7, P8, P9,
Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<2l, RAJA::policy::sequential::seq_exec, RAJA::statement::For<3l, RAJA::policy::sequential::seq_exec, RAJA::statement::For<4l, RAJA::policy::sequential::seq_exec, RAJA::statement::Lambda<0l> > > > >, RAJA::internal::LoopTypes, camp::list > >::exec, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, SweepSdom::operator() >(Kripke::ArchLayoutT, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&>(RAJA::internal::LoopData, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, SweepSdom::operator() >(Kripke::ArchLayoutT, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&) [clone ._omp_fn.0]
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	0.50
Front-end cycles	3.00
P0 cycles	1.83
P1 cycles	1.83
P2 cycles	1.83
P3 cycles	1.83
P4 cycles	1.83
P5 cycles	1.83
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	24.00
Nb loads	16.00
Nb stores	3.00
Nb stack references	13.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	38.00
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	24.00
Stride 0	5.00
Stride 1	0.00
Stride n	0.00
Stride unknown	8.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<2l, RAJA::policy::sequential::seq_exec, RAJA::statement::For<3l, RAJA::policy::sequential::seq_exec, RAJA::statement::For<4l, RAJA::policy::sequential::seq_exec, RAJA::statement::Lambda<0l> > > > >, RAJA::internal::LoopTypes, camp::list > >::exec, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, SweepSdom::operator() >(Kripke::ArchLayoutT, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&>(RAJA::internal::LoopData, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, SweepSdom::operator() >(Kripke::ArchLayoutT, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&) [clone ._omp_fn.0]
Source file and lines
Module	exec

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.00 to 0.50 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 4.00 to 3.00 cycles (1.33x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 128 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	27
nb uops	24
loop length	133
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	13

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.00 cycles
front end	3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.83	1.83	1.83	1.83	1.83	1.83	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.83	1.83	1.83	1.83	1.83	1.83	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.00
Dispatch	4.00
Data deps.	1.00
Overall L1	4.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

12% of peak load performance is reached (32.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 48efd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV 0x10(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x48(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
LEA (,%RAX,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x50(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA (%RAX,%RCX,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x58(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA (%RAX,%RDI,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x60(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA (%RCX,%RAX,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x68(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x40(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x20(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADDQ $0x1,0x8(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV 0x30(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x38(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDX,0x10(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV 0x8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
ADD %RDI,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
ADD %RCX,0x18(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
CMP %RAX,0x28(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
JG 48efd0 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEEvOS1Q_._omp_fn.0+0xd30>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A

Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<2l, RAJA::policy::sequential::seq_exec, RAJA::statement::For<3l, RAJA::policy::sequential::seq_exec, RAJA::statement::For<4l, RAJA::policy::sequential::seq_exec, RAJA::statement::Lambda<0l> > > > >, RAJA::internal::LoopTypes, camp::list > >::exec, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, SweepSdom::operator() >(Kripke::ArchLayoutT, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&>(RAJA::internal::LoopData, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, SweepSdom::operator() >(Kripke::ArchLayoutT, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&) [clone ._omp_fn.0]
Source file and lines
Module	exec

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.00 to 0.50 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 4.00 to 3.00 cycles (1.33x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 128 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	27
nb uops	24
loop length	133
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	13

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.00 cycles
front end	3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.83	1.83	1.83	1.83	1.83	1.83	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.83	1.83	1.83	1.83	1.83	1.83	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.00
Dispatch	4.00
Data deps.	1.00
Overall L1	4.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

12% of peak load performance is reached (32.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 48efd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV 0x10(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x48(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
LEA (,%RAX,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x50(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA (%RAX,%RCX,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x58(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA (%RAX,%RDI,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x60(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA (%RCX,%RAX,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x68(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x40(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x20(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADDQ $0x1,0x8(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV 0x30(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x38(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDX,0x10(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV 0x8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
ADD %RDI,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
ADD %RCX,0x18(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
CMP %RAX,0x28(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
JG 48efd0 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvvEEESK_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSU_EElEENSQ_INSS_INST_5GroupElPSY_EElEENSQ_INSR_24strided_numeric_iteratorINST_5ZoneKElPS13_EElEENSQ_INS12_INST_5ZoneJElPS17_EElEENSQ_INS12_INST_5ZoneIElPS1B_EElEEEEENSP_IJEEENS5_9resources2v14HostEJZNK9SweepSdomclINST_11ArchLayoutTINST_12ArchT_OpenMPENST_11LayoutT_DGZEEEEEvT_RNST_4Core9DataStoreENST_6SdomIdEEUlSU_SY_S13_S17_S1B_E_EEEEEvOS1Q_._omp_fn.0+0xd30>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code