OV - exec - Loop 2033

	Loop Id: 2033	Module: exec	Source: :0-0	Coverage: 0.06%

0x480a60 MOV	0x18(%RSP),%RAX

0x480a65 MOV	%RCX,(%RSP)

0x480a69 XOR	%EBX,%EBX

0x480a6b MOV	%R14,%RSI

0x480a6e LEA	(%RAX,%R14,1),%RDI

0x480a72 MOV	0x10(%RSP),%RAX

0x480a77 LEA	(%RAX,%RCX,8),%R13

0x480a7b MOV	0x28(%RSP),%RAX

0x480a80 ADD	%RAX,%RDI

0x480a83 NOPW	%CS:(%RAX,%RAX,1)

0x480a8e XCHG	%AX,%AX

  (2032) 0x480a90 MOV	(%R12,%RBX,8),%RCX

  (2032) 0x480a94 MOVSXD	(%R15,%RBX,4),%R14

  (2032) 0x480a98 ADD	%RCX,%R14

  (2032) 0x480a9b CMP	%R14,%RCX

  (2032) 0x480a9e JGE	480b70

  (2032) 0x480aa4 SAL	$0x3,%RCX

  (2032) 0x480aa8 SAL	$0x3,%R14

  (2032) 0x480aac PXOR	%XMM1,%XMM1

  (2032) 0x480ab0 NOPW	%CS:(%RAX,%RAX,1)

  (2032) 0x480abb NOPL	(%RAX,%RAX,1)

    (2035) 0x480ac0 MOV	(%R11,%RCX,1),%RAX

    (2035) 0x480ac4 IMUL	%R8,%RAX

    (2035) 0x480ac8 ADD	%RDI,%RAX

    (2035) 0x480acb MOVSD	(%R9,%RAX,8),%XMM0

    (2035) 0x480ad1 MULSD	(%R10,%RCX,1),%XMM0

    (2035) 0x480ad7 ADD	$0x8,%RCX

    (2035) 0x480adb ADDSD	%XMM0,%XMM1

    (2035) 0x480adf CMP	%RCX,%R14

    (2035) 0x480ae2 JNE	480ac0

  (2032) 0x480ae4 MULSD	(%R13,%RBX,8),%XMM1

  (2032) 0x480aeb ADDSD	(%RBP,%RBX,8),%XMM1

  (2032) 0x480af1 MOVSD	%XMM1,(%RBP,%RBX,8)

  (2032) 0x480af7 ADD	$0x1,%RBX

  (2032) 0x480afb CMP	%RBX,%RDX

  (2032) 0x480afe JG	480a90

0x480b00 MOV	0x20(%RSP),%RAX

0x480b05 MOV	(%RSP),%RCX

0x480b09 MOV	%RSI,%R14

0x480b0c ADD	$0x1,%R14

0x480b10 ADD	%RAX,%RCX

0x480b13 MOV	0x8(%RSP),%RAX

0x480b18 CMP	%RAX,%R14

0x480b1b JL	480a60

  (2032) 0x480b70 PXOR	%XMM1,%XMM1

  (2032) 0x480b74 JMP	480ae4

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

Coverage (%)	Name	Source Location	Module
►97.59+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.20+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	void Kripke::DispatchHelper<Kr[...]		exec
○	Kripke::Kernel::scattering(Kri[...]		exec
○	Kripke::SteadyStateSolver(Krip[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	14.48
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	micro-operation queue,
Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<2l, RAJA::policy::sequential::seq_exec, RAJA::statement::For<3l, RAJA::policy::sequential::seq_exec, RAJA::statement::Lambda<0l> > > >, RAJA::internal::LoopTypes, camp::list > >::exec, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, ScatteringSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const::{lambda(Kripke::Moment, Kripke::Group, Kripke::Group, Kripke::Zone)#1}>&>(RAJA::internal::LoopData, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, ScatteringSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const::{lambda(Kripke::Moment, Kripke::Group, Kripke::Group, Kripke::Zone)#1}>&) [clone ._omp_fn.0]
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.14
Front-end cycles	2.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	1.75
P7 cycles	1.75
P8 cycles	1.75
P9 cycles	1.75
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	16.00
Nb loads	6.00
Nb stores	1.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.00
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	8.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	1.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.94
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.38

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	14.48
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	micro-operation queue,
Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<2l, RAJA::policy::sequential::seq_exec, RAJA::statement::For<3l, RAJA::policy::sequential::seq_exec, RAJA::statement::Lambda<0l> > > >, RAJA::internal::LoopTypes, camp::list > >::exec, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, ScatteringSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const::{lambda(Kripke::Moment, Kripke::Group, Kripke::Group, Kripke::Zone)#1}>&>(RAJA::internal::LoopData, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, ScatteringSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const::{lambda(Kripke::Moment, Kripke::Group, Kripke::Group, Kripke::Zone)#1}>&) [clone ._omp_fn.0]
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.14
Front-end cycles	2.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	1.75
P7 cycles	1.75
P8 cycles	1.75
P9 cycles	1.75
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	16.00
Nb loads	6.00
Nb stores	1.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.00
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	8.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	1.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.94
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.38

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<2l, RAJA::policy::sequential::seq_exec, RAJA::statement::For<3l, RAJA::policy::sequential::seq_exec, RAJA::statement::Lambda<0l> > > >, RAJA::internal::LoopTypes, camp::list > >::exec, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, ScatteringSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const::{lambda(Kripke::Moment, Kripke::Group, Kripke::Group, Kripke::Zone)#1}>&>(RAJA::internal::LoopData, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, ScatteringSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const::{lambda(Kripke::Moment, Kripke::Group, Kripke::Group, Kripke::Zone)#1}>&) [clone ._omp_fn.0]
Source file and lines
Module	exec

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.14 cycles (14.48x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 48 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	19
nb uops	16
loop length	81
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.00 cycles
front end	2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.00	1.00	1.00	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	1.00	1.00	1.00	1.00	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.00
Dispatch	1.75
Data deps.	1.00
Overall L1	2.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

9% of peak load performance is reached (24.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.00 to 1.75 cycles (1.14x speedup).

ASM code

In the binary file, the address of the loop is: 480a60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV 0x18(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RCX,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %R14,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
LEA (%RAX,%R14,1),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x10(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA (%RAX,%RCX,8),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x28(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x20(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x1,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JL 480a60 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPST_EElEENSP_INSR_INSS_5GroupElPSX_EElEES10_NSP_INSR_INSS_4ZoneElPS11_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK14ScatteringSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdES1H_RKNSS_4Core3SetES1L_S1L_RNS1I_5FieldIdJST_SX_S11_EEES1O_RNS1M_IdJNSS_8MaterialENSS_8LegendreENSS_11GlobalGroupES1R_EEERNS1M_INSS_7MixElemEJS11_EEERNS1M_IiJS11_EEERNS1M_IS1P_JS1U_EEERNS1M_IdJS1U_EEERNS1M_IS1Q_JST_EEEEUlST_SX_SX_S11_E_EEEEEvOS1G_._omp_fn.0+0x260>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A

Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<2l, RAJA::policy::sequential::seq_exec, RAJA::statement::For<3l, RAJA::policy::sequential::seq_exec, RAJA::statement::Lambda<0l> > > >, RAJA::internal::LoopTypes, camp::list > >::exec, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, ScatteringSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const::{lambda(Kripke::Moment, Kripke::Group, Kripke::Group, Kripke::Zone)#1}>&>(RAJA::internal::LoopData, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, ScatteringSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const::{lambda(Kripke::Moment, Kripke::Group, Kripke::Group, Kripke::Zone)#1}>&) [clone ._omp_fn.0]
Source file and lines
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 48 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	19
nb uops	16
loop length	81
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.00 cycles
front end	2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.00	1.00	1.00	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	1.00	1.00	1.00	1.00	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.00
Dispatch	1.75
Data deps.	1.00
Overall L1	2.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

9% of peak load performance is reached (24.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 480a60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV 0x18(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RCX,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %R14,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
LEA (%RAX,%R14,1),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x10(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA (%RAX,%RCX,8),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x28(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x20(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x1,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JL 480a60 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPST_EElEENSP_INSR_INSS_5GroupElPSX_EElEES10_NSP_INSR_INSS_4ZoneElPS11_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK14ScatteringSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdES1H_RKNSS_4Core3SetES1L_S1L_RNS1I_5FieldIdJST_SX_S11_EEES1O_RNS1M_IdJNSS_8MaterialENSS_8LegendreENSS_11GlobalGroupES1R_EEERNS1M_INSS_7MixElemEJS11_EEERNS1M_IiJS11_EEERNS1M_IS1P_JS1U_EEERNS1M_IdJS1U_EEERNS1M_IS1Q_JST_EEEEUlST_SX_SX_S11_E_EEEEEvOS1G_._omp_fn.0+0x260>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code