| Loop Id: 2032 | Module: exec | Source: :0-0 | Coverage: 48.91% |
|---|
| Loop Id: 2032 | Module: exec | Source: :0-0 | Coverage: 48.91% |
|---|
0x480a90 MOV (%R12,%RBX,8),%RCX |
0x480a94 MOVSXD (%R15,%RBX,4),%R14 |
0x480a98 ADD %RCX,%R14 |
0x480a9b CMP %R14,%RCX |
0x480a9e JGE 480b70 |
0x480aa4 SAL $0x3,%RCX |
0x480aa8 SAL $0x3,%R14 |
0x480aac PXOR %XMM1,%XMM1 |
0x480ab0 NOPW %CS:(%RAX,%RAX,1) |
0x480abb NOPL (%RAX,%RAX,1) |
(2035) 0x480ac0 MOV (%R11,%RCX,1),%RAX |
(2035) 0x480ac4 IMUL %R8,%RAX |
(2035) 0x480ac8 ADD %RDI,%RAX |
(2035) 0x480acb MOVSD (%R9,%RAX,8),%XMM0 |
(2035) 0x480ad1 MULSD (%R10,%RCX,1),%XMM0 |
(2035) 0x480ad7 ADD $0x8,%RCX |
(2035) 0x480adb ADDSD %XMM0,%XMM1 |
(2035) 0x480adf CMP %RCX,%R14 |
(2035) 0x480ae2 JNE 480ac0 |
0x480ae4 MULSD (%R13,%RBX,8),%XMM1 |
0x480aeb ADDSD (%RBP,%RBX,8),%XMM1 |
0x480af1 MOVSD %XMM1,(%RBP,%RBX,8) |
0x480af7 ADD $0x1,%RBX |
0x480afb CMP %RBX,%RDX |
0x480afe JG 480a90 |
0x480b70 PXOR %XMM1,%XMM1 |
0x480b74 JMP 480ae4 |
*** This Panel is Intentionally Left Blank. *** It is due to a lack of debug symbols in the given object |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►96.69+ | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
| ○ | start_thread | libc.so.6 | |
| ○ | __GI___clone3 | libc.so.6 | |
| ►2.75+ | GOMP_parallel | libgomp.h:982 | libgomp.so.1.0.0 |
| ○ | void Kripke::DispatchHelper<Kr[...] | exec | |
| ○ | Kripke::Kernel::scattering(Kri[...] | exec | |
| ○ | Kripke::SteadyStateSolver(Krip[...] | exec | |
| ○ | main | exec | |
| ○ | __libc_start_call_main | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | _start | exec |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.53 |
| CQA speedup if FP arith vectorized | 1.30 |
| CQA speedup if fully vectorized | 10.81 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.22 |
| Bottlenecks | |
| Function | void RAJA::internal::StatementExecutor |
| Source | |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 1.63 |
| CQA cycles if no scalar integer | 1.06 |
| CQA cycles if FP arith vectorized | 1.25 |
| CQA cycles if fully vectorized | 0.15 |
| Front-end cycles | 1.63 |
| P0 cycles | 1.33 |
| P1 cycles | 1.33 |
| P2 cycles | 1.33 |
| P3 cycles | 1.33 |
| P4 cycles | 1.33 |
| P5 cycles | 1.33 |
| P6 cycles | 1.25 |
| P7 cycles | 1.25 |
| P8 cycles | 1.25 |
| P9 cycles | 1.25 |
| P10 cycles | 0.50 |
| P11 cycles | 0.50 |
| P12 cycles | 0.50 |
| P13 cycles | 0.50 |
| P14 cycles | 0.50 |
| P15 cycles | 0.50 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 14.50 |
| Nb uops | 13.00 |
| Nb loads | 4.00 |
| Nb stores | 1.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 1.23 |
| Nb FLOP add-sub | 1.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 22.15 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 28.00 |
| Bytes stored | 8.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 3.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 11.25 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 37.50 |
| Vector-efficiency ratio all | 13.20 |
| Vector-efficiency ratio load | 10.94 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 17.19 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.63 |
| CQA speedup if FP arith vectorized | 1.30 |
| CQA speedup if fully vectorized | 10.67 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.22 |
| Bottlenecks | micro-operation queue, |
| Function | void RAJA::internal::StatementExecutor |
| Source | |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 1.63 |
| CQA cycles if no scalar integer | 1.00 |
| CQA cycles if FP arith vectorized | 1.25 |
| CQA cycles if fully vectorized | 0.15 |
| Front-end cycles | 1.63 |
| P0 cycles | 1.33 |
| P1 cycles | 1.33 |
| P2 cycles | 1.33 |
| P3 cycles | 1.33 |
| P4 cycles | 1.33 |
| P5 cycles | 1.33 |
| P6 cycles | 1.25 |
| P7 cycles | 1.25 |
| P8 cycles | 1.25 |
| P9 cycles | 1.25 |
| P10 cycles | 0.50 |
| P11 cycles | 0.50 |
| P12 cycles | 0.50 |
| P13 cycles | 0.50 |
| P14 cycles | 0.50 |
| P15 cycles | 0.50 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 16.00 |
| Nb uops | 13.00 |
| Nb loads | 4.00 |
| Nb stores | 1.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 1.23 |
| Nb FLOP add-sub | 1.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 22.15 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 28.00 |
| Bytes stored | 8.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 3.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 10.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 25.00 |
| Vector-efficiency ratio all | 13.13 |
| Vector-efficiency ratio load | 10.94 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 15.63 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.44 |
| CQA speedup if FP arith vectorized | 1.30 |
| CQA speedup if fully vectorized | 10.95 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.22 |
| Bottlenecks | micro-operation queue, |
| Function | void RAJA::internal::StatementExecutor |
| Source | |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 1.63 |
| CQA cycles if no scalar integer | 1.13 |
| CQA cycles if FP arith vectorized | 1.25 |
| CQA cycles if fully vectorized | 0.15 |
| Front-end cycles | 1.63 |
| P0 cycles | 1.33 |
| P1 cycles | 1.33 |
| P2 cycles | 1.33 |
| P3 cycles | 1.33 |
| P4 cycles | 1.33 |
| P5 cycles | 1.33 |
| P6 cycles | 1.25 |
| P7 cycles | 1.25 |
| P8 cycles | 1.25 |
| P9 cycles | 1.25 |
| P10 cycles | 0.50 |
| P11 cycles | 0.50 |
| P12 cycles | 0.50 |
| P13 cycles | 0.50 |
| P14 cycles | 0.50 |
| P15 cycles | 0.50 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 13.00 |
| Nb uops | 13.00 |
| Nb loads | 4.00 |
| Nb stores | 1.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 1.23 |
| Nb FLOP add-sub | 1.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 22.15 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 28.00 |
| Bytes stored | 8.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 12.50 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 50.00 |
| Vector-efficiency ratio all | 13.28 |
| Vector-efficiency ratio load | 10.94 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 18.75 |
| Path / |
| nb instructions | 14.50 |
| nb uops | 13 |
| loop length | 66.50 |
| used x86 registers | 8.50 |
| used mmx registers | 0 |
| used xmm registers | 1 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 1.00 |
| micro-operation queue | 1.63 cycles |
| front end | 1.63 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.33 | 1.33 | 1.33 | 1.33 | 1.33 | 1.33 | 1.25 | 1.25 | 1.25 | 1.25 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 |
| cycles | 1.33 | 1.33 | 1.33 | 1.33 | 1.33 | 1.33 | 1.25 | 1.25 | 1.25 | 1.25 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 1.63 |
| Dispatch | 1.33 |
| Data deps. | 1.00 |
| Overall L1 | 1.63 |
| all | 17% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 37% |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 11% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 37% |
| all | 13% |
| load | 9% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 17% |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 13% |
| load | 10% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 17% |
| nb instructions | 16 |
| nb uops | 13 |
| loop length | 76 |
| used x86 registers | 9 |
| used mmx registers | 0 |
| used xmm registers | 1 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 1.00 |
| micro-operation queue | 1.63 cycles |
| front end | 1.63 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.33 | 1.33 | 1.33 | 1.33 | 1.33 | 1.33 | 1.25 | 1.25 | 1.25 | 1.25 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 |
| cycles | 1.33 | 1.33 | 1.33 | 1.33 | 1.33 | 1.33 | 1.25 | 1.25 | 1.25 | 1.25 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 1.63 |
| Dispatch | 1.33 |
| Data deps. | 1.00 |
| Overall L1 | 1.63 |
| all | 14% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 25% |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 10% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| all | 13% |
| load | 9% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 15% |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 13% |
| load | 10% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 15% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV (%R12,%RBX,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (12.5%) |
| MOVSXD (%R15,%RBX,4),%R14 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
| ADD %RCX,%R14 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| CMP %R14,%RCX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| JGE 480b70 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPST_EElEENSP_INSR_INSS_5GroupElPSX_EElEES10_NSP_INSR_INSS_4ZoneElPS11_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK14ScatteringSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdES1H_RKNSS_4Core3SetES1L_S1L_RNS1I_5FieldIdJST_SX_S11_EEES1O_RNS1M_IdJNSS_8MaterialENSS_8LegendreENSS_11GlobalGroupES1R_EEERNS1M_INSS_7MixElemEJS11_EEERNS1M_IiJS11_EEERNS1M_IS1P_JS1U_EEERNS1M_IdJS1U_EEERNS1M_IS1Q_JST_EEEEUlST_SX_SX_S11_E_EEEEEvOS1G_._omp_fn.0+0x370> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
| SAL $0x3,%RCX | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| SAL $0x3,%R14 | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| PXOR %XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (25.0%) |
| NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 | N/A |
| NOPL (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 | N/A |
| MULSD (%R13,%RBX,8),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| ADDSD (%RBP,%RBX,8),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| MOVSD %XMM1,(%RBP,%RBX,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| ADD $0x1,%RBX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CMP %RBX,%RDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| JG 480a90 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPST_EElEENSP_INSR_INSS_5GroupElPSX_EElEES10_NSP_INSR_INSS_4ZoneElPS11_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK14ScatteringSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdES1H_RKNSS_4Core3SetES1L_S1L_RNS1I_5FieldIdJST_SX_S11_EEES1O_RNS1M_IdJNSS_8MaterialENSS_8LegendreENSS_11GlobalGroupES1R_EEERNS1M_INSS_7MixElemEJS11_EEERNS1M_IiJS11_EEERNS1M_IS1P_JS1U_EEERNS1M_IdJS1U_EEERNS1M_IS1Q_JST_EEEEUlST_SX_SX_S11_E_EEEEEvOS1G_._omp_fn.0+0x290> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
| nb instructions | 13 |
| nb uops | 13 |
| loop length | 57 |
| used x86 registers | 8 |
| used mmx registers | 0 |
| used xmm registers | 1 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 1.00 |
| micro-operation queue | 1.63 cycles |
| front end | 1.63 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.33 | 1.33 | 1.33 | 1.33 | 1.33 | 1.33 | 1.25 | 1.25 | 1.25 | 1.25 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 |
| cycles | 1.33 | 1.33 | 1.33 | 1.33 | 1.33 | 1.33 | 1.25 | 1.25 | 1.25 | 1.25 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 1.63 |
| Dispatch | 1.33 |
| Data deps. | 1.00 |
| Overall L1 | 1.63 |
| all | 20% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 50% |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 12% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 50% |
| all | 13% |
| load | 9% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 18% |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 13% |
| load | 10% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 18% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV (%R12,%RBX,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (12.5%) |
| MOVSXD (%R15,%RBX,4),%R14 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
| ADD %RCX,%R14 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| CMP %R14,%RCX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| JGE 480b70 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPST_EElEENSP_INSR_INSS_5GroupElPSX_EElEES10_NSP_INSR_INSS_4ZoneElPS11_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK14ScatteringSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdES1H_RKNSS_4Core3SetES1L_S1L_RNS1I_5FieldIdJST_SX_S11_EEES1O_RNS1M_IdJNSS_8MaterialENSS_8LegendreENSS_11GlobalGroupES1R_EEERNS1M_INSS_7MixElemEJS11_EEERNS1M_IiJS11_EEERNS1M_IS1P_JS1U_EEERNS1M_IdJS1U_EEERNS1M_IS1Q_JST_EEEEUlST_SX_SX_S11_E_EEEEEvOS1G_._omp_fn.0+0x370> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
| MULSD (%R13,%RBX,8),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| ADDSD (%RBP,%RBX,8),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| MOVSD %XMM1,(%RBP,%RBX,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| ADD $0x1,%RBX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CMP %RBX,%RDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| JG 480a90 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPST_EElEENSP_INSR_INSS_5GroupElPSX_EElEES10_NSP_INSR_INSS_4ZoneElPS11_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK14ScatteringSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdES1H_RKNSS_4Core3SetES1L_S1L_RNS1I_5FieldIdJST_SX_S11_EEES1O_RNS1M_IdJNSS_8MaterialENSS_8LegendreENSS_11GlobalGroupES1R_EEERNS1M_INSS_7MixElemEJS11_EEERNS1M_IiJS11_EEERNS1M_IS1P_JS1U_EEERNS1M_IdJS1U_EEERNS1M_IS1Q_JST_EEEEUlST_SX_SX_S11_E_EEEEEvOS1G_._omp_fn.0+0x290> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
| PXOR %XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (25.0%) |
| JMP 480ae4 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPST_EElEENSP_INSR_INSS_5GroupElPSX_EElEES10_NSP_INSR_INSS_4ZoneElPS11_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK14ScatteringSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdES1H_RKNSS_4Core3SetES1L_S1L_RNS1I_5FieldIdJST_SX_S11_EEES1O_RNS1M_IdJNSS_8MaterialENSS_8LegendreENSS_11GlobalGroupES1R_EEERNS1M_INSS_7MixElemEJS11_EEERNS1M_IiJS11_EEERNS1M_IS1P_JS1U_EEERNS1M_IdJS1U_EEERNS1M_IS1Q_JST_EEEEUlST_SX_SX_S11_E_EEEEEvOS1G_._omp_fn.0+0x2e4> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | N/A |