OV - exec - Loop 1709

	Loop Id: 1709	Module: exec	Source: :0-0	Coverage: 0.01%

0x46c960 MOV	0x50(%RSP),%RAX

0x46c965 MOV	0x40(%RSP),%RSI

0x46c96a MOV	%RBX,0x30(%RSP)

0x46c96f MOV	0x60(%RSP),%R9

0x46c974 MOV	0x48(%RSP),%R8

0x46c979 LEA	(%RAX,%RBX,1),%RDI

0x46c97d MOV	0x88(%RSP),%RAX

0x46c985 MOV	0x18(%RSP),%R12

0x46c98a MOV	%R10,%RBX

0x46c98d IMUL	%RDI,%R9

0x46c991 MOV	0x90(%RSP),%RBP

0x46c999 MOV	0x10(%RSP),%RDX

0x46c99e IMUL	%RSI,%RAX

0x46c9a2 ADD	%RAX,%R9

0x46c9a5 MOV	0x70(%RSP),%RAX

0x46c9aa IMUL	%RSI,%RAX

0x46c9ae MOV	0x58(%RSP),%RSI

0x46c9b3 ADD	%RSI,%RAX

0x46c9b6 MOV	0x68(%RSP),%RSI

0x46c9bb LEA	(%RSI,%RAX,8),%RSI

0x46c9bf MOV	0x80(%RSP),%RAX

0x46c9c7 IMUL	%RAX,%RDI

0x46c9cb MOV	0x78(%RSP),%RAX

0x46c9d0 ADD	%RAX,%RDI

0x46c9d3 LEA	(%RDI,%R8,1),%RAX

0x46c9d7 ADD	%R9,%R8

0x46c9da ADD	%R12,%R9

0x46c9dd SAL	$0x3,%R8

0x46c9e1 LEA	(%RDX,%RAX,8),%RDX

0x46c9e5 LEA	(%R10,%R9,8),%R12

0x46c9e9 LEA	(%R10,%R8,1),%RAX

0x46c9ed ADD	%RBP,%R8

0x46c9f0 LEA	(%R10,%R8,1),%RBP

0x46c9f4 XOR	%R8D,%R8D

  (1708) 0x46c9f7 LEA	0x8(%RSI),%R9

  (1708) 0x46c9fb CMP	$0x2,%R11

  (1708) 0x46c9ff JLE	46caed

  (1708) 0x46ca05 MOV	%R11,0x20(%RSP)

    (1711) 0x46ca0a LEA	0x8(%RSI),%R9

    (1711) 0x46ca0e CMP	%R9,%RAX

    (1711) 0x46ca11 SETAE	%R11B

    (1711) 0x46ca15 CMP	%RBP,%RSI

    (1711) 0x46ca18 SETAE	%R10B

    (1711) 0x46ca1c OR	%R11B,%R10B

    (1711) 0x46ca1f JE	46cae8

    (1711) 0x46ca25 LEA	0x8(%RDX),%R10

    (1711) 0x46ca29 CMP	%R10,%RAX

    (1711) 0x46ca2c JE	46cae8

    (1711) 0x46ca32 MOVSD	(%RSI),%XMM1

    (1711) 0x46ca36 XOR	%R10D,%R10D

    (1711) 0x46ca39 UNPCKLPD	%XMM1,%XMM1

    (1711) 0x46ca3d NOPL	(%RAX)

      (1710) 0x46ca40 MOVUPD	(%RDX,%R10,1),%XMM0

      (1710) 0x46ca46 MOVUPD	(%RAX,%R10,1),%XMM2

      (1710) 0x46ca4c MULPD	%XMM1,%XMM0

      (1710) 0x46ca50 ADDPD	%XMM2,%XMM0

      (1710) 0x46ca54 MOVUPS	%XMM0,(%RAX,%R10,1)

      (1710) 0x46ca59 ADD	$0x10,%R10

      (1710) 0x46ca5d CMP	%R10,%RCX

      (1710) 0x46ca60 JNE	46ca40

    (1711) 0x46ca62 CMPQ	$0,0x8(%RSP)

    (1711) 0x46ca68 JE	46ca8e

    (1711) 0x46ca6a MOV	0x18(%RSP),%R11

    (1711) 0x46ca6f LEA	(%RDI,%R11,1),%R10

    (1711) 0x46ca73 MOV	0x10(%RSP),%R11

    (1711) 0x46ca78 MOVSD	(%R11,%R10,8),%XMM0

    (1711) 0x46ca7e MULSD	(%RSI),%XMM0

    (1711) 0x46ca82 ADDSD	(%R12),%XMM0

    (1711) 0x46ca88 MOVSD	%XMM0,(%R12)

    (1711) 0x46ca8e ADD	$0x1,%R8

    (1711) 0x46ca92 MOV	%R9,%RSI

    (1711) 0x46ca95 ADD	%R13,%RDI

    (1711) 0x46ca98 ADD	%R15,%RDX

    (1711) 0x46ca9b CMP	%R8,%R14

    (1711) 0x46ca9e JG	46ca0a

0x46caa4 MOV	%RBX,%R10

0x46caa7 MOV	0x20(%RSP),%R11

0x46caac MOV	0x30(%RSP),%RBX

0x46cab1 MOV	0x98(%RSP),%RDI

0x46cab9 CMP	%RDI,0x28(%RSP)

0x46cabe JE	46cad6

0x46cac0 ADD	$0x1,%RBX

0x46cac4 CMP	%RBX,0x38(%RSP)

0x46cac9 JLE	46cb42

0x46cacb ADDQ	$0x1,0x28(%RSP)

0x46cad1 JMP	46c960

  (1708) 0x46cae8 MOV	0x20(%RSP),%R11

  (1708) 0x46caed XOR	%R10D,%R10D

  (1708) 0x46caf0 NOPW	%CS:(%RAX,%RAX,1)

  (1708) 0x46cafb NOPL	(%RAX,%RAX,1)

    (1707) 0x46cb00 MOVSD	(%RDX,%R10,8),%XMM0

    (1707) 0x46cb06 MULSD	(%RSI),%XMM0

    (1707) 0x46cb0a ADDSD	(%RAX,%R10,8),%XMM0

    (1707) 0x46cb10 MOVSD	%XMM0,(%RAX,%R10,8)

    (1707) 0x46cb16 ADD	$0x1,%R10

    (1707) 0x46cb1a CMP	%R10,%R11

    (1707) 0x46cb1d JG	46cb00

  (1708) 0x46cb1f ADD	$0x1,%R8

  (1708) 0x46cb23 MOV	%R9,%RSI

  (1708) 0x46cb26 ADD	%R13,%RDI

  (1708) 0x46cb29 ADD	%R15,%RDX

  (1708) 0x46cb2c CMP	%R14,%R8

  (1708) 0x46cb2f JL	46c9f7

0x46cb35 MOV	%RBX,%R10

0x46cb38 MOV	0x30(%RSP),%RBX

0x46cb3d JMP	46cab1

0x46cb42 ADDQ	$0x1,0xa0(%RSP)

0x46cb4b MOV	0xa8(%RSP),%RDI

0x46cb53 XOR	%EBX,%EBX

0x46cb55 MOV	0xa0(%RSP),%RAX

0x46cb5d ADD	%RDI,%RAX

0x46cb60 MOV	%RAX,0x40(%RSP)

0x46cb65 JMP	46cacb

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

Coverage (%)	Name	Source Location	Module
►96.67+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.33+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	void LPlusTimesSdom::operator([...]		exec
○	Kripke::Kernel::LPlusTimes(Kri[...]		exec
○	Kripke::SteadyStateSolver(Krip[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	micro-operation queue,
Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<1l, RAJA::policy::sequential::seq_exec, RAJA::statement::For<3l, RAJA::policy::sequential::seq_exec, RAJA::statement::Lambda<0l> > > >, RAJA::internal::LoopTypes, camp::list > >::exec, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, LPlusTimesSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const::{lambda(Kripke::Direction, Kripke::Moment, Kripke::Group, Kripke::Zone)#1}>&>(RAJA::internal::LoopData, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, LPlusTimesSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const::{lambda(Kripke::Direction, Kripke::Moment, Kripke::Group, Kripke::Zone)#1}>&) [clone ._omp_fn.0]
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.88
CQA cycles if no scalar integer	6.88
CQA cycles if FP arith vectorized	6.88
CQA cycles if fully vectorized	0.86
Front-end cycles	6.88
P0 cycles	4.83
P1 cycles	4.83
P2 cycles	4.83
P3 cycles	4.83
P4 cycles	4.83
P5 cycles	4.83
P6 cycles	6.25
P7 cycles	6.25
P8 cycles	6.25
P9 cycles	6.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	55.00
Nb uops	55.00
Nb loads	23.00
Nb stores	4.00
Nb stack references	20.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	31.42
Bytes prefetched	0.00
Bytes loaded	184.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	micro-operation queue,
Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<1l, RAJA::policy::sequential::seq_exec, RAJA::statement::For<3l, RAJA::policy::sequential::seq_exec, RAJA::statement::Lambda<0l> > > >, RAJA::internal::LoopTypes, camp::list > >::exec, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, LPlusTimesSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const::{lambda(Kripke::Direction, Kripke::Moment, Kripke::Group, Kripke::Zone)#1}>&>(RAJA::internal::LoopData, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, LPlusTimesSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const::{lambda(Kripke::Direction, Kripke::Moment, Kripke::Group, Kripke::Zone)#1}>&) [clone ._omp_fn.0]
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.88
CQA cycles if no scalar integer	6.88
CQA cycles if FP arith vectorized	6.88
CQA cycles if fully vectorized	0.86
Front-end cycles	6.88
P0 cycles	4.83
P1 cycles	4.83
P2 cycles	4.83
P3 cycles	4.83
P4 cycles	4.83
P5 cycles	4.83
P6 cycles	6.25
P7 cycles	6.25
P8 cycles	6.25
P9 cycles	6.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	55.00
Nb uops	55.00
Nb loads	23.00
Nb stores	4.00
Nb stack references	20.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	31.42
Bytes prefetched	0.00
Bytes loaded	184.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<1l, RAJA::policy::sequential::seq_exec, RAJA::statement::For<3l, RAJA::policy::sequential::seq_exec, RAJA::statement::Lambda<0l> > > >, RAJA::internal::LoopTypes, camp::list > >::exec, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, LPlusTimesSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const::{lambda(Kripke::Direction, Kripke::Moment, Kripke::Group, Kripke::Zone)#1}>&>(RAJA::internal::LoopData, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, LPlusTimesSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const::{lambda(Kripke::Direction, Kripke::Moment, Kripke::Group, Kripke::Zone)#1}>&) [clone ._omp_fn.0]
Source file and lines
Module	exec

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=10
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 10 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.88 to 0.86 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 184 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	55
nb uops	55
loop length	254
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.88 cycles
front end	6.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.83	4.83	4.83	4.83	4.83	4.83	6.25	6.25	6.25	6.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.83	4.83	4.83	4.83	4.83	4.83	6.25	6.25	6.25	6.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.88
Dispatch	6.25
Overall L1	6.88

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.88 cycles. At this rate:

10% of peak load performance is reached (26.76 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.65 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.88 to 6.25 cycles (1.10x speedup).

ASM code

In the binary file, the address of the loop is: 46c960

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV 0x50(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x40(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RBX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x60(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x48(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA (%RAX,%RBX,1),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x88(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV %R10,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RDI,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV 0x90(%RSP),%RBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x10(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RSI,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %RAX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x70(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RSI,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV 0x58(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x68(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA (%RSI,%RAX,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x80(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%RDI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV 0x78(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RDI,%R8,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
ADD %R9,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %R12,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SAL $0x3,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
LEA (%RDX,%RAX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%R10,%R9,8),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%R10,%R8,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
ADD %RBP,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%R10,%R8,1),%RBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RBX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x20(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x30(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x98(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RDI,0x28(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JE 46cad6 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EElEENSP_INSR_INSS_6MomentElPSX_EElEENSP_INSR_INSS_5GroupElPS11_EElEENSP_INSR_INSS_4ZoneElPS15_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK14LPlusTimesSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdERKNSS_4Core3SetES1P_S1P_S1P_RNS1M_5FieldIdJSX_S11_S15_EEERNS1Q_IdJST_S11_S15_EEERNS1Q_IdJST_SX_EEEEUlST_SX_S11_S15_E_EEEEEvOS1K_._omp_fn.0+0x316>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
ADD $0x1,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %RBX,0x38(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JLE 46cb42 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EElEENSP_INSR_INSS_6MomentElPSX_EElEENSP_INSR_INSS_5GroupElPS11_EElEENSP_INSR_INSS_4ZoneElPS15_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK14LPlusTimesSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdERKNSS_4Core3SetES1P_S1P_S1P_RNS1M_5FieldIdJSX_S11_S15_EEERNS1Q_IdJST_S11_S15_EEERNS1Q_IdJST_SX_EEEEUlST_SX_S11_S15_E_EEEEEvOS1K_._omp_fn.0+0x382>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
ADDQ $0x1,0x28(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
JMP 46c960 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EElEENSP_INSR_INSS_6MomentElPSX_EElEENSP_INSR_INSS_5GroupElPS11_EElEENSP_INSR_INSS_4ZoneElPS15_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK14LPlusTimesSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdERKNSS_4Core3SetES1P_S1P_S1P_RNS1M_5FieldIdJSX_S11_S15_EEERNS1Q_IdJST_S11_S15_EEERNS1Q_IdJST_SX_EEEEUlST_SX_S11_S15_E_EEEEEvOS1K_._omp_fn.0+0x1a0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV %RBX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x30(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
JMP 46cab1 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EElEENSP_INSR_INSS_6MomentElPSX_EElEENSP_INSR_INSS_5GroupElPS11_EElEENSP_INSR_INSS_4ZoneElPS15_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK14LPlusTimesSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdERKNSS_4Core3SetES1P_S1P_S1P_RNS1M_5FieldIdJSX_S11_S15_EEERNS1Q_IdJST_S11_S15_EEERNS1Q_IdJST_SX_EEEEUlST_SX_S11_S15_E_EEEEEvOS1K_._omp_fn.0+0x2f1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADDQ $0x1,0xa0(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV 0xa8(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0xa0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RAX,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 46cacb <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EElEENSP_INSR_INSS_6MomentElPSX_EElEENSP_INSR_INSS_5GroupElPS11_EElEENSP_INSR_INSS_4ZoneElPS15_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK14LPlusTimesSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdERKNSS_4Core3SetES1P_S1P_S1P_RNS1M_5FieldIdJSX_S11_S15_EEERNS1Q_IdJST_S11_S15_EEERNS1Q_IdJST_SX_EEEEUlST_SX_S11_S15_E_EEEEEvOS1K_._omp_fn.0+0x30b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<1l, RAJA::policy::sequential::seq_exec, RAJA::statement::For<3l, RAJA::policy::sequential::seq_exec, RAJA::statement::Lambda<0l> > > >, RAJA::internal::LoopTypes, camp::list > >::exec, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, LPlusTimesSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const::{lambda(Kripke::Direction, Kripke::Moment, Kripke::Group, Kripke::Zone)#1}>&>(RAJA::internal::LoopData, long>, RAJA::Span, long>, RAJA::Span, long>, RAJA::Span, long> >, camp::tuple<>, camp::resources::v1::Host, LPlusTimesSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const::{lambda(Kripke::Direction, Kripke::Moment, Kripke::Group, Kripke::Zone)#1}>&) [clone ._omp_fn.0]
Source file and lines
Module	exec

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=10
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.88 to 0.86 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 184 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	55
nb uops	55
loop length	254
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.88 cycles
front end	6.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.83	4.83	4.83	4.83	4.83	4.83	6.25	6.25	6.25	6.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.83	4.83	4.83	4.83	4.83	4.83	6.25	6.25	6.25	6.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.88
Dispatch	6.25
Overall L1	6.88

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.88 cycles. At this rate:

10% of peak load performance is reached (26.76 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.65 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 46c960

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV 0x50(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x40(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RBX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x60(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x48(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA (%RAX,%RBX,1),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x88(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV %R10,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RDI,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV 0x90(%RSP),%RBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x10(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RSI,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %RAX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x70(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RSI,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV 0x58(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x68(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA (%RSI,%RAX,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x80(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%RDI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV 0x78(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RDI,%R8,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
ADD %R9,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %R12,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SAL $0x3,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
LEA (%RDX,%RAX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%R10,%R9,8),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%R10,%R8,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
ADD %RBP,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%R10,%R8,1),%RBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RBX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x20(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x30(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x98(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RDI,0x28(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JE 46cad6 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EElEENSP_INSR_INSS_6MomentElPSX_EElEENSP_INSR_INSS_5GroupElPS11_EElEENSP_INSR_INSS_4ZoneElPS15_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK14LPlusTimesSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdERKNSS_4Core3SetES1P_S1P_S1P_RNS1M_5FieldIdJSX_S11_S15_EEERNS1Q_IdJST_S11_S15_EEERNS1Q_IdJST_SX_EEEEUlST_SX_S11_S15_E_EEEEEvOS1K_._omp_fn.0+0x316>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
ADD $0x1,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %RBX,0x38(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JLE 46cb42 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EElEENSP_INSR_INSS_6MomentElPSX_EElEENSP_INSR_INSS_5GroupElPS11_EElEENSP_INSR_INSS_4ZoneElPS15_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK14LPlusTimesSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdERKNSS_4Core3SetES1P_S1P_S1P_RNS1M_5FieldIdJSX_S11_S15_EEERNS1Q_IdJST_S11_S15_EEERNS1Q_IdJST_SX_EEEEUlST_SX_S11_S15_E_EEEEEvOS1K_._omp_fn.0+0x382>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
ADDQ $0x1,0x28(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
JMP 46c960 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EElEENSP_INSR_INSS_6MomentElPSX_EElEENSP_INSR_INSS_5GroupElPS11_EElEENSP_INSR_INSS_4ZoneElPS15_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK14LPlusTimesSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdERKNSS_4Core3SetES1P_S1P_S1P_RNS1M_5FieldIdJSX_S11_S15_EEERNS1Q_IdJST_S11_S15_EEERNS1Q_IdJST_SX_EEEEUlST_SX_S11_S15_E_EEEEEvOS1K_._omp_fn.0+0x1a0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV %RBX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x30(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
JMP 46cab1 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EElEENSP_INSR_INSS_6MomentElPSX_EElEENSP_INSR_INSS_5GroupElPS11_EElEENSP_INSR_INSS_4ZoneElPS15_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK14LPlusTimesSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdERKNSS_4Core3SetES1P_S1P_S1P_RNS1M_5FieldIdJSX_S11_S15_EEERNS1Q_IdJST_S11_S15_EEERNS1Q_IdJST_SX_EEEEUlST_SX_S11_S15_E_EEEEEvOS1K_._omp_fn.0+0x2f1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADDQ $0x1,0xa0(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV 0xa8(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0xa0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RAX,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 46cacb <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy10sequential8seq_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvvEEESJ_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EElEENSP_INSR_INSS_6MomentElPSX_EElEENSP_INSR_INSS_5GroupElPS11_EElEENSP_INSR_INSS_4ZoneElPS15_EElEEEEENSO_IJEEENS5_9resources2v14HostEJZNK14LPlusTimesSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_NSS_6SdomIdERKNSS_4Core3SetES1P_S1P_S1P_RNS1M_5FieldIdJSX_S11_S15_EEERNS1Q_IdJST_S11_S15_EEERNS1Q_IdJST_SX_EEEEUlST_SX_S11_S15_E_EEEEEvOS1K_._omp_fn.0+0x30b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code