OV - exec - Function Kripke::ParallelComm::getReadyList()

	Function: Kripke::ParallelComm::getReadyList()	Module: exec	Source: :0-0	Coverage (incl. loops): 0.01% \| (excl. loops): 0.01%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x4b0c50 PUSH	%R15

0x4b0c52 PXOR	%XMM0,%XMM0

0x4b0c56 PUSH	%R14

0x4b0c58 PUSH	%R13

0x4b0c5a PUSH	%R12

0x4b0c5c MOV	%RDI,%R12

0x4b0c5f PUSH	%RBP

0x4b0c60 PUSH	%RBX

0x4b0c61 SUB	$0x18,%RSP

0x4b0c65 MOV	0x78(%RSI),%RCX

0x4b0c69 MOV	0x70(%RSI),%RDX

0x4b0c6d MOVUPS	%XMM0,(%RDI)

0x4b0c70 MOVQ	$0,0x10(%RDI)

0x4b0c78 CMP	%RCX,%RDX

0x4b0c7b JE	4b0ccb

0x4b0c7d MOV	%RSI,%R14

0x4b0c80 XOR	%EBX,%EBX

0x4b0c82 NOPW	%CS:(%RAX,%RAX,1)

0x4b0c8d NOPL	(%RAX)

(2425) 0x4b0c90 MOV	(%RDX,%RBX,4),%EAX

(2425) 0x4b0c93 TEST	%EAX,%EAX

(2425) 0x4b0c95 JNE	4b0cb8

(2425) 0x4b0c97 MOV	0x58(%R14),%RAX

(2425) 0x4b0c9b MOV	0x8(%R12),%RBP

(2425) 0x4b0ca0 MOVSXD	(%RAX,%RBX,4),%RSI

(2425) 0x4b0ca4 CMP	0x10(%R12),%RBP

(2425) 0x4b0ca9 JE	4b0ce0

(2425) 0x4b0cab MOV	%RSI,(%RBP)

(2425) 0x4b0caf ADD	$0x8,%RBP

(2425) 0x4b0cb3 MOV	%RBP,0x8(%R12)

(2425) 0x4b0cb8 MOV	%RCX,%RAX

(2425) 0x4b0cbb ADD	$0x1,%RBX

(2425) 0x4b0cbf SUB	%RDX,%RAX

(2425) 0x4b0cc2 SAR	$0x2,%RAX

(2425) 0x4b0cc6 CMP	%RAX,%RBX

(2425) 0x4b0cc9 JB	4b0c90

0x4b0ccb ADD	$0x18,%RSP

0x4b0ccf MOV	%R12,%RAX

0x4b0cd2 POP	%RBX

0x4b0cd3 POP	%RBP

0x4b0cd4 POP	%R12

0x4b0cd6 POP	%R13

0x4b0cd8 POP	%R14

0x4b0cda POP	%R15

0x4b0cdc RET

0x4b0cdd NOPL	(%RAX)

(2425) 0x4b0ce0 MOV	(%R12),%R15

(2425) 0x4b0ce4 MOV	%RBP,%R8

(2425) 0x4b0ce7 MOV	$0xfffffffffffffff,%RAX

(2425) 0x4b0cf1 SUB	%R15,%R8

(2425) 0x4b0cf4 MOV	%R8,%R13

(2425) 0x4b0cf7 SAR	$0x3,%R13

(2425) 0x4b0cfb CMP	%RAX,%R13

(2425) 0x4b0cfe JE	415630

(2425) 0x4b0d04 TEST	%R13,%R13

(2425) 0x4b0d07 MOV	$0x1,%EAX

(2425) 0x4b0d0c CMOVNE	%R13,%RAX

(2425) 0x4b0d10 ADD	%RAX,%R13

(2425) 0x4b0d13 JB	4b0db8

(2425) 0x4b0d19 MOV	$0xfffffffffffffff,%RAX

(2425) 0x4b0d23 CMP	%RAX,%R13

(2425) 0x4b0d26 CMOVA	%RAX,%R13

(2425) 0x4b0d2a SAL	$0x3,%R13

(2425) 0x4b0d2e MOV	%R13,%RDI

(2425) 0x4b0d31 MOV	%R8,0x8(%RSP)

(2425) 0x4b0d36 MOV	%RSI,(%RSP)

(2425) 0x4b0d3a CALL	403240 <_Znwm@plt>

(2425) 0x4b0d3f MOV	(%RSP),%RSI

(2425) 0x4b0d43 MOV	0x8(%RSP),%R8

(2425) 0x4b0d48 MOV	%RAX,%RCX

(2425) 0x4b0d4b MOV	%RSI,(%RAX,%R8,1)

(2425) 0x4b0d4f CMP	%R15,%RBP

(2425) 0x4b0d52 JE	4b0db3

(2425) 0x4b0d54 SUB	%R15,%RBP

(2425) 0x4b0d57 MOV	%R15,%RDX

(2425) 0x4b0d5a ADD	%RAX,%RBP

(2425) 0x4b0d5d NOPL	(%RAX)

  (2426) 0x4b0d60 MOV	(%RDX),%RSI

  (2426) 0x4b0d63 ADD	$0x8,%RAX

  (2426) 0x4b0d67 ADD	$0x8,%RDX

  (2426) 0x4b0d6b MOV	%RSI,-0x8(%RAX)

  (2426) 0x4b0d6f CMP	%RAX,%RBP

  (2426) 0x4b0d72 JNE	4b0d60

(2425) 0x4b0d74 ADD	$0x8,%RBP

(2425) 0x4b0d78 TEST	%R15,%R15

(2425) 0x4b0d7b JE	4b0d95

(2425) 0x4b0d7d MOV	0x10(%R12),%RSI

(2425) 0x4b0d82 MOV	%R15,%RDI

(2425) 0x4b0d85 MOV	%RCX,(%RSP)

(2425) 0x4b0d89 SUB	%R15,%RSI

(2425) 0x4b0d8c CALL	403250 <_ZdlPvm@plt>

(2425) 0x4b0d91 MOV	(%RSP),%RCX

(2425) 0x4b0d95 MOV	%RCX,(%R12)

(2425) 0x4b0d99 ADD	%R13,%RCX

(2425) 0x4b0d9c MOV	0x70(%R14),%RDX

(2425) 0x4b0da0 MOV	%RCX,0x10(%R12)

(2425) 0x4b0da5 MOV	0x78(%R14),%RCX

(2425) 0x4b0da9 MOV	%RBP,0x8(%R12)

(2425) 0x4b0dae JMP	4b0cb8

(2425) 0x4b0db3 MOV	%RAX,%RBP

(2425) 0x4b0db6 JMP	4b0d74

(2425) 0x4b0db8 MOV	$0x7ffffffffffffff8,%R13

(2425) 0x4b0dc2 JMP	4b0d2e

0x4b0dc7 JMP	41563c

0x4b0dcc NOPL	(%RAX)

Coverage (%)	Name	Module
►93.16+	Kripke::SweepComm::readySubdom[...]	exec
○	Kripke::SweepSolver(Kripke::Co[...]	exec
○	Kripke::SteadyStateSolver(Krip[...]	exec
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec
►6.84+	Kripke::SweepComm::readySubdom[...]	exec
○	Kripke::SweepSolver(Kripke::Co[...]	exec
○	Kripke::SteadyStateSolver(Krip[...]	exec
○	main	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.38 to 0.63 cycles (5.40x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 3.38 to 0.25 cycles (13.41x speedup).

Details

22% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.
20% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

MOVUPS: 1 occurrences►

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries
2. inform your compiler that your arrays are vector aligned: read your compiler manual.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 24 bytes.

General properties

nb instructions	31
nb uops	27
loop length	94
used x86 registers	12
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.38 cycles
front end	3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.50	0.50
cycles	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.38
Dispatch	1.00
Overall L1	3.38

Vectorization ratios

INT

all	12%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	22%
load	0%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	12%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	13%
load	12%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.38 cycles. At this rate:

1% of peak load performance is reached (4.74 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.11 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.38 to 1.00 cycles (3.38x speedup).

ASM code

In the binary file, the address of the function is: 4b0c50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PXOR %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RSI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV 0x70(%RSI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOVUPS %XMM0,(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (25.0%)
MOVQ $0,0x10(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 4b0ccb <_ZN6Kripke12ParallelComm12getReadyListEv+0x7b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %R12,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 41563c <_ZN6Kripke12ParallelComm12getReadyListEv.cold+0xc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.38 to 0.63 cycles (5.40x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

22% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.
20% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

MOVUPS: 1 occurrences►

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries
2. inform your compiler that your arrays are vector aligned: read your compiler manual.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 24 bytes.

General properties

nb instructions	31
nb uops	27
loop length	94
used x86 registers	12
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.38 cycles
front end	3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.50	0.50
cycles	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.38
Dispatch	1.00
Overall L1	3.38

Vectorization ratios

INT

all	12%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	22%
load	0%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	12%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	13%
load	12%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.38 cycles. At this rate:

1% of peak load performance is reached (4.74 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.11 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4b0c50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PXOR %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RSI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV 0x70(%RSI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOVUPS %XMM0,(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (25.0%)
MOVQ $0,0x10(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 4b0ccb <_ZN6Kripke12ParallelComm12getReadyListEv+0x7b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %R12,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 41563c <_ZN6Kripke12ParallelComm12getReadyListEv.cold+0xc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼Kripke::ParallelComm::getReadyList()–	0.01	0.00
▼Loop 2425 - - exec–	0.01	0.03
○Loop 2426 - - exec	0.00	0.00

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Vector unaligned load/store instructions

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Matching between your function (in the source code) and the binary function

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Code clean check

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Vectorization

Details

Workaround

Execution units bottlenecks

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code