OV - exec - Function Kripke::ParallelComm::testRecieves()

	Function: Kripke::ParallelComm::testRecieves()	Module: exec	Source: :0-0	Coverage (incl. loops): 0.02% \| (excl. loops): 0.01%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x4b0a80 PUSH	%R15

0x4b0a82 PUSH	%R14

0x4b0a84 PUSH	%R13

0x4b0a86 MOV	%RDI,%R13

0x4b0a89 PUSH	%R12

0x4b0a8b PUSH	%RBP

0x4b0a8c PUSH	%RBX

0x4b0a8d SUB	$0x28,%RSP

0x4b0a91 MOV	0x30(%RDI),%RAX

0x4b0a95 SUB	0x28(%RDI),%RAX

0x4b0a99 SAR	$0x2,%RAX

0x4b0a9d LEA	0x18(%RSP),%RDI

0x4b0aa2 MOV	%RDI,0x8(%RSP)

0x4b0aa7 TEST	%EAX,%EAX

0x4b0aa9 JLE	4b0b41

0x4b0aaf MOVSXD	%EAX,%R12

0x4b0ab2 LEA	0x1c(%RSP),%R15

(2422) 0x4b0ab7 LEA	(%R12,%R12,4),%RBP

(2422) 0x4b0abb MOV	%R12D,%R14D

(2422) 0x4b0abe SAL	$0x2,%RBP

(2422) 0x4b0ac2 MOV	%RBP,%RDI

(2422) 0x4b0ac5 CALL	403240 <_Znwm@plt>

(2422) 0x4b0aca PXOR	%XMM1,%XMM1

(2422) 0x4b0ace MOVL	$0,0x10(%RAX)

(2422) 0x4b0ad5 MOV	%RAX,%RBX

(2422) 0x4b0ad8 LEA	(%RAX,%RBP,1),%RCX

(2422) 0x4b0adc LEA	0x14(%RAX),%RAX

(2422) 0x4b0ae0 MOVUPS	%XMM1,-0x14(%RAX)

(2422) 0x4b0ae4 CMP	$0x1,%R12

(2422) 0x4b0ae8 JE	4b0b17

(2422) 0x4b0aea NOPW	%CS:(%RAX,%RAX,1)

(2422) 0x4b0af5 NOPW	%CS:(%RAX,%RAX,1)

  (2424) 0x4b0b00 MOVDQU	(%RBX),%XMM0

  (2424) 0x4b0b04 ADD	$0x14,%RAX

  (2424) 0x4b0b08 MOVUPS	%XMM0,-0x14(%RAX)

  (2424) 0x4b0b0c MOV	0x10(%RBX),%EDX

  (2424) 0x4b0b0f MOV	%EDX,-0x4(%RAX)

  (2424) 0x4b0b12 CMP	%RAX,%RCX

  (2424) 0x4b0b15 JNE	4b0b00

(2422) 0x4b0b17 MOV	0x28(%R13),%RSI

(2422) 0x4b0b1b MOV	0x8(%RSP),%RDX

(2422) 0x4b0b20 MOV	%RBX,%R8

(2422) 0x4b0b23 MOV	%R15,%RCX

(2422) 0x4b0b26 MOV	%R14D,%EDI

(2422) 0x4b0b29 CALL	403390 <MPI_Testany@plt>

(2422) 0x4b0b2e MOV	0x1c(%RSP),%EAX

(2422) 0x4b0b32 TEST	%EAX,%EAX

(2422) 0x4b0b34 JNE	4b0b50

0x4b0b36 MOV	%RBP,%RSI

0x4b0b39 MOV	%RBX,%RDI

0x4b0b3c CALL	403250 <_ZdlPvm@plt>

0x4b0b41 ADD	$0x28,%RSP

0x4b0b45 POP	%RBX

0x4b0b46 POP	%RBP

0x4b0b47 POP	%R12

0x4b0b49 POP	%R13

0x4b0b4b POP	%R14

0x4b0b4d POP	%R15

0x4b0b4f RET

(2422) 0x4b0b50 MOVSXD	0x18(%RSP),%RAX

(2422) 0x4b0b55 MOV	0x28(%R13),%RSI

(2422) 0x4b0b59 MOV	0x40(%R13),%RCX

(2422) 0x4b0b5d LEA	(%RSI,%RAX,4),%RDI

(2422) 0x4b0b61 MOV	%RAX,%RDX

(2422) 0x4b0b64 MOV	(%RCX,%RAX,4),%R14D

(2422) 0x4b0b68 MOV	0x30(%R13),%RAX

(2422) 0x4b0b6c LEA	0x4(%RDI),%RSI

(2422) 0x4b0b70 CMP	%RSI,%RAX

(2422) 0x4b0b73 JE	4b0b9a

(2422) 0x4b0b75 MOV	%RAX,%R8

(2422) 0x4b0b78 SUB	%RSI,%R8

(2422) 0x4b0b7b CMP	$0x4,%R8

(2422) 0x4b0b7f JLE	4b0c24

(2422) 0x4b0b85 MOV	%R8,%RDX

(2422) 0x4b0b88 CALL	403460 <memmove@plt>

(2422) 0x4b0b8d MOV	0x40(%R13),%RCX

(2422) 0x4b0b91 MOV	0x30(%R13),%RAX

(2422) 0x4b0b95 MOVSXD	0x18(%RSP),%RDX

(2422) 0x4b0b9a SUB	$0x4,%RAX

(2422) 0x4b0b9e LEA	(%RCX,%RDX,4),%RDI

(2422) 0x4b0ba2 MOV	%RAX,0x30(%R13)

(2422) 0x4b0ba6 MOV	0x48(%R13),%RAX

(2422) 0x4b0baa LEA	0x4(%RDI),%RSI

(2422) 0x4b0bae CMP	%RSI,%RAX

(2422) 0x4b0bb1 JE	4b0bc8

(2422) 0x4b0bb3 MOV	%RAX,%RDX

(2422) 0x4b0bb6 SUB	%RSI,%RDX

(2422) 0x4b0bb9 CMP	$0x4,%RDX

(2422) 0x4b0bbd JLE	4b0c39

(2422) 0x4b0bbf CALL	403460 <memmove@plt>

(2422) 0x4b0bc4 MOV	0x48(%R13),%RAX

(2422) 0x4b0bc8 SUB	$0x4,%RAX

(2422) 0x4b0bcc MOV	0x58(%R13),%RDX

(2422) 0x4b0bd0 MOV	%RAX,0x48(%R13)

(2422) 0x4b0bd4 MOV	0x60(%R13),%RAX

(2422) 0x4b0bd8 MOV	%RAX,%RCX

(2422) 0x4b0bdb SUB	%RDX,%RCX

(2422) 0x4b0bde SAR	$0x2,%RCX

(2422) 0x4b0be2 CMP	%RAX,%RDX

(2422) 0x4b0be5 JE	4b0c07

(2422) 0x4b0be7 XOR	%EAX,%EAX

(2422) 0x4b0be9 JMP	4b0bf9

0x4b0beb NOPL	(%RAX,%RAX,1)

  (2423) 0x4b0bf0 ADD	$0x1,%RAX

  (2423) 0x4b0bf4 CMP	%RCX,%RAX

  (2423) 0x4b0bf7 JAE	4b0c07

  (2423) 0x4b0bf9 CMP	%R14D,(%RDX,%RAX,4)

  (2423) 0x4b0bfd JNE	4b0bf0

(2422) 0x4b0bff MOV	0x70(%R13),%RDX

(2422) 0x4b0c03 SUBL	$0x1,(%RDX,%RAX,4)

(2422) 0x4b0c07 MOV	%RBP,%RSI

(2422) 0x4b0c0a MOV	%RBX,%RDI

(2422) 0x4b0c0d SUB	$0x1,%R12

(2422) 0x4b0c11 CALL	403250 <_ZdlPvm@plt>

(2422) 0x4b0c16 TEST	%R12D,%R12D

(2422) 0x4b0c19 JG	4b0ab7

0x4b0c1f JMP	4b0b41

(2422) 0x4b0c24 JNE	4b0b9a

(2422) 0x4b0c2a MOV	0x4(%RDI),%EDX

(2422) 0x4b0c2d MOV	%EDX,(%RDI)

(2422) 0x4b0c2f MOVSXD	0x18(%RSP),%RDX

(2422) 0x4b0c34 JMP	4b0b9a

(2422) 0x4b0c39 JNE	4b0bc8

(2422) 0x4b0c3b MOV	0x4(%RDI),%EDX

(2422) 0x4b0c3e MOV	%EDX,(%RDI)

(2422) 0x4b0c40 JMP	4b0bc8

0x4b0c42 MOV	%RAX,%R12

0x4b0c45 JMP	41561c

0x4b0c4a NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Module
►84.54+	Kripke::SweepComm::readySubdom[...]	exec
○	Kripke::SweepSolver(Kripke::Co[...]	exec
○	Kripke::SteadyStateSolver(Krip[...]	exec
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec
►15.46+	Kripke::SweepComm::readySubdom[...]	exec
○	Kripke::SweepSolver(Kripke::Co[...]	exec
○	Kripke::SteadyStateSolver(Krip[...]	exec
○	main	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 4.00 to 0.26 cycles (15.53x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

operator delete(void*, unsigned long): 1 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	33
nb uops	32
loop length	105
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.00 cycles
front end	4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.17	2.17	2.17	2.17	2.17	2.17	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.17	2.17	2.17	2.17	2.17	2.17	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.00
Dispatch	2.17
Overall L1	4.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.00 cycles. At this rate:

1% of peak load performance is reached (4.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.00 to 2.17 cycles (1.85x speedup).

ASM code

In the binary file, the address of the function is: 4b0a80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x30(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
SUB 0x28(%RDI),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
SAR $0x2,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
LEA 0x18(%RSP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RDI,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 4b0b41 <_ZN6Kripke12ParallelComm12testRecievesEv+0xc1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOVSXD %EAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x1c(%RSP),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RBP,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 403250 <_ZdlPvm@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 4b0b41 <_ZN6Kripke12ParallelComm12testRecievesEv+0xc1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
JMP 41561c <_ZN6Kripke12ParallelComm12testRecievesEv.cold>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

operator delete(void*, unsigned long): 1 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	33
nb uops	32
loop length	105
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.00 cycles
front end	4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.17	2.17	2.17	2.17	2.17	2.17	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.17	2.17	2.17	2.17	2.17	2.17	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.00
Dispatch	2.17
Overall L1	4.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.00 cycles. At this rate:

1% of peak load performance is reached (4.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4b0a80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x30(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
SUB 0x28(%RDI),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
SAR $0x2,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
LEA 0x18(%RSP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RDI,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 4b0b41 <_ZN6Kripke12ParallelComm12testRecievesEv+0xc1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOVSXD %EAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x1c(%RSP),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RBP,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 403250 <_ZdlPvm@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 4b0b41 <_ZN6Kripke12ParallelComm12testRecievesEv+0xc1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
JMP 41561c <_ZN6Kripke12ParallelComm12testRecievesEv.cold>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼Kripke::ParallelComm::testRecieves()–	0.02	0.00
▼Loop 2422 - - exec–	0.00	0.01
○Loop 2424 - - exec	0.01	0.02
○Loop 2423 - - exec	0.00	0.00

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