OV - exec - Function void RAJA::internal::StatementExecutor<RAJA::statement::Collapse<RAJA::omp_parallel_collapse_exec, camp::int_seq<long, 0l, 1l>, RAJA::statement::For<2l, RAJA::policy::sequential::seq_exec, RAJA::statement::Lambda<0l> > >, RAJA::internal::LoopTypes<camp::list<void, void, void>, camp::list<void, void, void> > >::exec<RAJA::internal::LoopData<camp::tuple<RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Direction, long, Kripke::Direction*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Group, long, Kripke::Group*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Zone, long, Kripke::Zone*>, long> >, camp::tuple<>, camp::resources::v1::Host, PopulationSdom::operator()<Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ> >(Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ>, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field<double, Kripke::Direction, Kripke::Group, Kripke::Zone>&, Kripke::Core::Field<double, Kripke::Direction>&, Kripke::Core::Field<double, Kripke::Zone>&, double*) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&>(RAJA::internal::LoopData<camp::tuple<RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Direction, long, Kripke::Direction*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Group, long, Kripke::Group*>, long>, RAJA::Span<RAJA::Iterators::numeric_iterator<Kripke::Zone, long, Kripke::Zone*>, long> >, camp::tuple<>, camp::resources::v1::Host, PopulationSdom::operator()<Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ> >(Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ>, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field<double, Kripke::Direction, Kripke::Group, Kripke::Zone>&, Kripke::Core::Field<double, Kripke::Direction>&, Kripke::Core::Field<double, Kripke::Zone>&, double*) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&) [clone ._omp

	Function: void RAJA::internal::StatementExecutor<RAJA::statement::Collapse<RAJA::omp_parallel_collap ...	Module: exec	Source: :0-0	Coverage (incl. loops): 0.45% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x479740 PUSH	%R15

0x479742 PUSH	%R14

0x479744 PUSH	%R13

0x479746 PUSH	%R12

0x479748 PUSH	%RBP

0x479749 PUSH	%RBX

0x47974a SUB	$0x48,%RSP

0x47974e MOV	0x10(%RDI),%R14

0x479752 MOV	(%RDI),%R13

0x479755 MOV	0x8(%RDI),%RBX

0x479759 MOV	0x38(%R14),%R12

0x47975d LEA	0x38(%R14),%RAX

0x479761 MOVSD	0x40(%R14),%XMM0

0x479767 TEST	%R12,%R12

0x47976a CMOVE	%RAX,%R12

0x47976e TEST	%R13,%R13

0x479771 JLE	47996f

0x479777 TEST	%RBX,%RBX

0x47977a JLE	47996f

0x479780 MOVSD	%XMM0,(%RSP)

0x479785 CALL	403500 <omp_get_num_threads@plt>

0x47978a MOVSXD	%EAX,%RBP

0x47978d CALL	403440 <omp_get_thread_num@plt>

0x479792 XOR	%EDX,%EDX

0x479794 MOVSD	(%RSP),%XMM0

0x479799 MOVSXD	%EAX,%RSI

0x47979c MOV	%R13,%RAX

0x47979f IMUL	%RBX,%RAX

0x4797a3 DIV	%RBP

0x4797a6 CMP	%RDX,%RSI

0x4797a9 MOV	%RAX,%RCX

0x4797ac JB	479a09

0x4797b2 IMUL	%RCX,%RSI

0x4797b6 MOVAPD	%XMM0,%XMM1

0x4797ba LEA	(%RSI,%RDX,1),%RAX

0x4797be LEA	(%RCX,%RAX,1),%RDX

0x4797c2 CMP	%RDX,%RAX

0x4797c5 JAE	479980

0x4797cb MOV	0x98(%R14),%RDX

0x4797d2 MOV	0x20(%R14),%R11

0x4797d6 MOV	0x28(%R14),%RBP

0x4797da MOV	0xe0(%R14),%RSI

0x4797e1 MOV	0x50(%R14),%R15

0x4797e5 MOV	0x78(%R14),%R13

0x4797e9 MOV	%RDX,0x8(%RSP)

0x4797ee MOV	0xa0(%R14),%RDX

0x4797f5 SUB	%R11,%RBP

0x4797f8 MOV	%RSI,0x20(%RSP)

0x4797fd LEA	(%RSI,%R11,8),%RDI

0x479801 MOV	%RDX,0x10(%RSP)

0x479806 XOR	%EDX,%EDX

0x479808 DIV	%RBX

0x47980b MOV	%RAX,0x30(%RSP)

0x479810 LEA	-0x1(%RCX),%RAX

0x479814 MOV	$0x1,%ECX

0x479819 MOV	%RAX,(%RSP)

0x47981d XOR	%EAX,%EAX

0x47981f TEST	%RBP,%RBP

0x479822 CMOVNS	%RBP,%RAX

0x479826 CMOVLE	%RCX,%RAX

0x47982a XOR	%R9D,%R9D

0x47982d TEST	%RBP,%RBP

0x479830 JG	479852

(1932) 0x479832 CMP	%R9,(%RSP)

(1932) 0x479836 JE	47996f

(1932) 0x47983c ADD	$0x1,%RDX

(1932) 0x479840 CMP	%RDX,%RBX

(1932) 0x479843 JLE	479a14

(1932) 0x479849 ADD	$0x1,%R9

(1932) 0x47984d TEST	%RBP,%RBP

(1932) 0x479850 JLE	479832

0x479852 MOV	(%R14),%RSI

0x479855 MOV	0x30(%RSP),%RCX

0x47985a MOVAPD	%XMM0,%XMM1

0x47985e MOV	0x10(%R14),%R14

0x479862 LEA	(%RCX,%RSI,1),%R10

0x479866 MOV	%RAX,%RCX

0x479869 MOV	%RSI,0x38(%RSP)

0x47986e MOV	%RAX,%RSI

0x479871 AND	$0x1,%ECX

0x479874 AND	$-0x2,%RAX

0x479878 SHR	$0x1,%RSI

0x47987b MOV	%RCX,0x18(%RSP)

0x479880 SAL	$0x4,%RSI

0x479884 MOV	%RAX,0x28(%RSP)

0x479889 NOPL	(%RAX)

(1930) 0x479890 MOV	0x10(%RSP),%RCX

(1930) 0x479895 MOV	0x8(%RSP),%R8

(1930) 0x47989a LEA	(%R14,%RDX,1),%RAX

(1930) 0x47989e MOVSD	(%R15,%R10,8),%XMM4

(1930) 0x4798a4 IMUL	%RCX,%RAX

(1930) 0x4798a8 IMUL	%R10,%R8

(1930) 0x4798ac CMP	$0x1,%RBP

(1930) 0x4798b0 JE	4799ff

(1930) 0x4798b6 ADD	%RAX,%R8

(1930) 0x4798b9 MOVAPD	%XMM4,%XMM3

(1930) 0x4798bd LEA	(%R8,%R11,1),%RAX

(1930) 0x4798c1 UNPCKLPD	%XMM3,%XMM3

(1930) 0x4798c5 LEA	(%R13,%RAX,8),%RCX

(1930) 0x4798ca XOR	%EAX,%EAX

(1930) 0x4798cc NOPW	%CS:(%RAX,%RAX,1)

(1930) 0x4798d7 NOPW	%CS:(%RAX,%RAX,1)

(1930) 0x4798e2 NOPW	%CS:(%RAX,%RAX,1)

(1930) 0x4798ed NOPW	%CS:(%RAX,%RAX,1)

(1930) 0x4798f8 NOPL	(%RAX,%RAX,1)

  (1931) 0x479900 MOVUPD	(%RCX,%RAX,1),%XMM7

  (1931) 0x479905 MOVUPD	(%RDI,%RAX,1),%XMM5

  (1931) 0x47990a ADD	$0x10,%RAX

  (1931) 0x47990e MULPD	%XMM3,%XMM7

  (1931) 0x479912 MULPD	%XMM5,%XMM7

  (1931) 0x479916 ADDSD	%XMM7,%XMM1

  (1931) 0x47991a MOVAPD	%XMM7,%XMM6

  (1931) 0x47991e UNPCKHPD	%XMM6,%XMM6

  (1931) 0x479922 ADDSD	%XMM6,%XMM1

  (1931) 0x479926 CMP	%RAX,%RSI

  (1931) 0x479929 JNE	479900

(1930) 0x47992b CMPQ	$0,0x18(%RSP)

(1930) 0x479931 JE	479957

(1930) 0x479933 MOV	0x28(%RSP),%RCX

(1930) 0x479938 ADD	%R11,%RCX

(1930) 0x47993b MOV	0x20(%RSP),%RAX

(1930) 0x479940 ADD	%RCX,%R8

(1930) 0x479943 MULSD	(%R13,%R8,8),%XMM4

(1930) 0x47994a MOVAPD	%XMM4,%XMM2

(1930) 0x47994e MULSD	(%RAX,%RCX,8),%XMM2

(1930) 0x479953 ADDSD	%XMM2,%XMM1

(1930) 0x479957 CMP	%R9,(%RSP)

(1930) 0x47995b JE	479980

(1930) 0x47995d ADD	$0x1,%RDX

(1930) 0x479961 CMP	%RDX,%RBX

(1930) 0x479964 JLE	4799e0

(1930) 0x479966 ADD	$0x1,%R9

(1930) 0x47996a JMP	479890

0x47996f MOVAPD	%XMM0,%XMM1

0x479973 NOPW	%CS:(%RAX,%RAX,1)

0x47997e XCHG	%AX,%AX

0x479980 MOV	$0x4cb3b8,%RBX

0x479987 MOVSD	%XMM0,0x8(%RSP)

0x47998d MOVSD	%XMM1,(%RSP)

0x479992 MOV	%RBX,%RDI

0x479995 CALL	403230 <GOMP_critical_name_start@plt>

0x47999a MOVSD	(%RSP),%XMM1

0x47999f MOV	%RBX,%RDI

0x4799a2 ADDSD	0x10(%R12),%XMM1

0x4799a9 MOVSD	%XMM1,0x10(%R12)

0x4799b0 CALL	4030a0 <GOMP_critical_name_end@plt>

0x4799b5 MOVSD	0x8(%RSP),%XMM0

0x4799bb UCOMISD	%XMM0,%XMM0

0x4799bf JNP	4799cf

0x4799c1 ADDSD	0x10(%R12),%XMM0

0x4799c8 MOVSD	%XMM0,0x10(%R12)

0x4799cf ADD	$0x48,%RSP

0x4799d3 POP	%RBX

0x4799d4 POP	%RBP

0x4799d5 POP	%R12

0x4799d7 POP	%R13

0x4799d9 POP	%R14

0x4799db POP	%R15

0x4799dd RET

0x4799de XCHG	%AX,%AX

(1930) 0x4799e0 ADDQ	$0x1,0x30(%RSP)

(1930) 0x4799e6 MOV	0x38(%RSP),%RCX

(1930) 0x4799eb ADD	$0x1,%R9

(1930) 0x4799ef XOR	%EDX,%EDX

(1930) 0x4799f1 MOV	0x30(%RSP),%RAX

(1930) 0x4799f6 LEA	(%RAX,%RCX,1),%R10

(1930) 0x4799fa JMP	479890

(1930) 0x4799ff XOR	%ECX,%ECX

(1930) 0x479a01 ADD	%RAX,%R8

(1930) 0x479a04 JMP	479938

0x479a09 ADD	$0x1,%RCX

0x479a0d XOR	%EDX,%EDX

0x479a0f JMP	4797b2

(1932) 0x479a14 ADDQ	$0x1,0x30(%RSP)

(1932) 0x479a1a XOR	%EDX,%EDX

(1932) 0x479a1c JMP	479849

0x479a21 NOPW	%CS:(%RAX,%RAX,1)

0x479a2c NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►96.80+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.85+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	void PopulationSdom::operator([...]		exec
○	Kripke::Kernel::population(Kri[...]		exec
○	Kripke::SteadyStateSolver(Krip[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.00 to 3.50 cycles (6.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 24.00 to 3.00 cycles (8.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 24.00 to 14.00 cycles (1.71x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.00 to 13.75 cycles (1.75x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

GOMP_critical_name_end@plt: 1 occurrences►
GOMP_critical_name_start@plt: 1 occurrences►
omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVLE: 1 occurrences►
DIV: 2 occurrences►
UCOMISD: 1 occurrences►

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 2 FP arithmetical operations:

2: addition or subtraction

The binary function is loading 160 bytes (20 double precision FP elements). The binary function is storing 104 bytes (13 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	110
nb uops	112
loop length	443
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.00 cycles
front end	14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.83	7.83	7.83	7.83	7.83	7.83	9.25	9.25	9.25	9.25	0.00	0.00	1.50	1.50	3.00	3.00
cycles	7.83	7.83	7.83	7.83	7.83	7.83	9.25	9.25	9.25	9.25	0.00	0.00	1.50	1.50	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

14.00-24.00

Cycles summary

Front-end	14.00
Dispatch	9.25
DIV/SQRT	14.00-24.00
Overall L1	14.00-24.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	20%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	75%

INT+FP

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	21%

Vector efficiency ratios

INT

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	15%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.00 cycles. At this rate:

2% of peak load performance is reached (6.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 479740

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RDI),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RDI),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x8(%RDI),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x38(%R14),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x38(%R14),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVSD 0x40(%R14),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
TEST %R12,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVE %RAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %R13,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 47996f <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEEvOS1F_._omp_fn.0+0x22f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
TEST %RBX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 47996f <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEEvOS1F_._omp_fn.0+0x22f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSD %XMM0,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 403500 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
MOVSXD %EAX,%RBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 403440 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOVSD (%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVSXD %EAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RBX,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %RBP	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	10-22	7-12	scal (12.5%)
CMP %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JB 479a09 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEEvOS1F_._omp_fn.0+0x2c9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RCX,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
LEA (%RSI,%RDX,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RCX,%RAX,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 479980 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEEvOS1F_._omp_fn.0+0x240>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x98(%R14),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x20(%R14),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%R14),%RBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0xe0(%R14),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x50(%R14),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x78(%R14),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %RDX,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xa0(%R14),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
SUB %R11,%RBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RSI,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RSI,%R11,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
DIV %RBX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	10-22	7-12	scal (12.5%)
MOV %RAX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
LEA -0x1(%RCX),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x1,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
TEST %RBP,%RBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVNS %RBP,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVLE %RCX,%RAX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
TEST %RBP,%RBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 479852 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEEvOS1F_._omp_fn.0+0x112>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R14),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x30(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV 0x10(%R14),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA (%RCX,%RSI,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x1,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x2,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RCX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SAL $0x4,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RAX,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x4cb3b8,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOVSD %XMM0,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM1,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 403230 <GOMP_critical_name_start@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
MOVSD (%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADDSD 0x10(%R12),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOVSD %XMM1,0x10(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 4030a0 <GOMP_critical_name_end@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
MOVSD 0x8(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
UCOMISD %XMM0,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1	scal (12.5%)
JNP 4799cf <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEEvOS1F_._omp_fn.0+0x28f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADDSD 0x10(%R12),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOVSD %XMM0,0x10(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x1,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4797b2 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEEvOS1F_._omp_fn.0+0x72>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.00 to 3.50 cycles (6.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.00 to 13.75 cycles (1.75x speedup).

CALL instructions

Detected function call instructions.

Details

GOMP_critical_name_end@plt: 1 occurrences►
GOMP_critical_name_start@plt: 1 occurrences►
omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVLE: 1 occurrences►
DIV: 2 occurrences►
UCOMISD: 1 occurrences►

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 2 FP arithmetical operations:

2: addition or subtraction

The binary function is loading 160 bytes (20 double precision FP elements). The binary function is storing 104 bytes (13 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	110
nb uops	112
loop length	443
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.00 cycles
front end	14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.83	7.83	7.83	7.83	7.83	7.83	9.25	9.25	9.25	9.25	0.00	0.00	1.50	1.50	3.00	3.00
cycles	7.83	7.83	7.83	7.83	7.83	7.83	9.25	9.25	9.25	9.25	0.00	0.00	1.50	1.50	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

14.00-24.00

Cycles summary

Front-end	14.00
Dispatch	9.25
DIV/SQRT	14.00-24.00
Overall L1	14.00-24.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	20%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	75%

INT+FP

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	21%

Vector efficiency ratios

INT

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	15%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.00 cycles. At this rate:

2% of peak load performance is reached (6.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 479740

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RDI),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RDI),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x8(%RDI),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x38(%R14),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x38(%R14),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVSD 0x40(%R14),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
TEST %R12,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVE %RAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %R13,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 47996f <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEEvOS1F_._omp_fn.0+0x22f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
TEST %RBX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 47996f <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEEvOS1F_._omp_fn.0+0x22f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSD %XMM0,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 403500 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
MOVSXD %EAX,%RBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 403440 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOVSD (%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVSXD %EAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RBX,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %RBP	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	10-22	7-12	scal (12.5%)
CMP %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JB 479a09 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEEvOS1F_._omp_fn.0+0x2c9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RCX,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
LEA (%RSI,%RDX,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RCX,%RAX,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 479980 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEEvOS1F_._omp_fn.0+0x240>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x98(%R14),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x20(%R14),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%R14),%RBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0xe0(%R14),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x50(%R14),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x78(%R14),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %RDX,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xa0(%R14),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
SUB %R11,%RBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RSI,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RSI,%R11,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
DIV %RBX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	10-22	7-12	scal (12.5%)
MOV %RAX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
LEA -0x1(%RCX),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x1,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
TEST %RBP,%RBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVNS %RBP,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVLE %RCX,%RAX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
TEST %RBP,%RBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 479852 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEEvOS1F_._omp_fn.0+0x112>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R14),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x30(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV 0x10(%R14),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA (%RCX,%RSI,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x1,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x2,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RCX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SAL $0x4,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RAX,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x4cb3b8,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOVSD %XMM0,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM1,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 403230 <GOMP_critical_name_start@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
MOVSD (%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADDSD 0x10(%R12),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOVSD %XMM1,0x10(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 4030a0 <GOMP_critical_name_end@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
MOVSD 0x8(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
UCOMISD %XMM0,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1	scal (12.5%)
JNP 4799cf <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEEvOS1F_._omp_fn.0+0x28f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADDSD 0x10(%R12),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOVSD %XMM0,0x10(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x1,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4797b2 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy10sequential8seq_execEJNS2_6LambdaILl0EJEEEEEEEEENS0_9LoopTypesINS5_4listIJvvvEEESI_EEE4execIRNS0_8LoopDataINS5_5tupleIJNS_4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EElEENSO_INSQ_INSR_5GroupElPSW_EElEENSO_INSQ_INSR_4ZoneElPS10_EElEEEEENSN_IJEEENS5_9resources2v14HostEJZNK14PopulationSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1K_S1K_RNS1H_5FieldIdJSS_SW_S10_EEERNS1L_IdJSS_EEERNS1L_IdJS10_EEEPdEUlSS_SW_S10_E_EEEEEvOS1F_._omp_fn.0+0x72>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼void RAJA::internal::StatementExecutor, RAJA::statement::For<2l, RAJA::policy::sequential::seq_exec, RAJA::statement::Lambda<0l> > >, RAJA::internal::LoopTypes–	0.45	0.05
▼Loop 1930 - - exec–	0.00	0.00
○Loop 1931 - - exec	0.45	0.05
○Loop 1932 - - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code