OV - exec - Loop 1349

	Loop Id: 1349	Module: exec	Source: :0-0	Coverage: 0.05%

0x465f50 LEA	0x1(%R9),%RAX

0x465f54 CMP	0x48(%RSP),%R9

0x465f59 MOV	%RAX,%R9

0x465f5c JE	465e60

0x465f62 CMPQ	$0,0x10(%RSP)

0x465f68 JLE	465f50

0x465f6a MOV	0xd0(%RSP),%RAX

0x465f72 MOV	0xd8(%RSP),%RCX

0x465f7a MOV	(%RAX,%RCX,8),%RBX

0x465f7e IMUL	0xc0(%RSP),%RBX

0x465f87 ADD	0xc8(%RSP),%RBX

0x465f8f MOV	0x40(%RSP),%RAX

0x465f94 IMUL	%R9,%RAX

0x465f98 MOV	%RAX,0x128(%RSP)

0x465fa0 MOV	0x50(%RSP),%RAX

0x465fa5 ADD	%RBX,%RAX

0x465fa8 ADD	%RBP,%RAX

0x465fab ADD	%R9,%RAX

0x465fae XOR	%R11D,%R11D

0x465fb1 MOV	%R9,0x28(%RSP)

0x465fb6 MOV	%RBX,0x18(%RSP)

0x465fbb JMP	466013

  (1350) 0x465fc0 XORPD	%XMM0,%XMM0

  (1350) 0x465fc4 MOV	0x128(%RSP),%RCX

  (1350) 0x465fcc ADD	%R11,%RCX

  (1350) 0x465fcf ADD	0x120(%RSP),%RCX

  (1350) 0x465fd7 MOV	0x100(%RSP),%RDX

  (1350) 0x465fdf MULSD	(%RDX,%RCX,8),%XMM0

  (1350) 0x465fe4 MOV	0x118(%RSP),%RCX

  (1350) 0x465fec ADD	%R11,%RCX

  (1350) 0x465fef MOV	0x108(%RSP),%RDX

  (1350) 0x465ff7 ADDSD	(%RDX,%RCX,8),%XMM0

  (1350) 0x465ffc MOVSD	%XMM0,(%RDX,%RCX,8)

  (1350) 0x466001 LEA	0x1(%R11),%RCX

  (1350) 0x466005 CMP	0x58(%RSP),%R11

  (1350) 0x46600a MOV	%RCX,%R11

  (1350) 0x46600d JE	465f50

  (1350) 0x466013 MOV	(%RSP),%RCX

  (1350) 0x466017 LEA	(%RCX,%R11,1),%RSI

  (1350) 0x46601b MOV	0x110(%RSP),%RCX

  (1350) 0x466023 MOVSXD	(%RCX,%RSI,4),%RDI

  (1350) 0x466027 TEST	%RDI,%RDI

  (1350) 0x46602a JLE	465fc0

  (1350) 0x46602c MOV	0xf8(%RSP),%RCX

  (1350) 0x466034 MOV	(%RCX,%RSI,8),%R10

  (1350) 0x466038 ADD	%R10,%RDI

  (1350) 0x46603b LEA	0x1(%R10),%RBX

  (1350) 0x46603f CMP	%RBX,%RDI

  (1350) 0x466042 CMOVLE	%RBX,%RDI

  (1350) 0x466046 SUB	%R10,%RDI

  (1350) 0x466049 XORPD	%XMM0,%XMM0

  (1350) 0x46604d CMP	$0x4,%RDI

  (1350) 0x466051 JB	4660ea

  (1350) 0x466057 MOV	%RDI,%R8

  (1350) 0x46605a SHR	$0x2,%R8

  (1350) 0x46605e LEA	(,%R10,8),%RSI

  (1350) 0x466066 NOPW	%CS:(%RAX,%RAX,1)

    (1351) 0x466070 MOV	(%R13,%RSI,1),%R9

    (1351) 0x466075 IMUL	%R12,%R9

    (1351) 0x466079 ADD	%RAX,%R9

    (1351) 0x46607c MOV	0x8(%R13,%RSI,1),%RCX

    (1351) 0x466081 IMUL	%R12,%RCX

    (1351) 0x466085 ADD	%RAX,%RCX

    (1351) 0x466088 MOV	0x10(%R13,%RSI,1),%RDX

    (1351) 0x46608d IMUL	%R12,%RDX

    (1351) 0x466091 ADD	%RAX,%RDX

    (1351) 0x466094 MOV	0x18(%R13,%RSI,1),%RBP

    (1351) 0x466099 IMUL	%R12,%RBP

    (1351) 0x46609d ADD	%RAX,%RBP

    (1351) 0x4660a0 MOVUPD	(%R14,%RSI,1),%XMM1

    (1351) 0x4660a6 MOVUPD	0x10(%R14,%RSI,1),%XMM2

    (1351) 0x4660ad MOVSD	(%R15,%R9,8),%XMM3

    (1351) 0x4660b3 MOVHPD	(%R15,%RCX,8),%XMM3

    (1351) 0x4660b9 MULPD	%XMM1,%XMM3

    (1351) 0x4660bd MOVSD	(%R15,%RDX,8),%XMM1

    (1351) 0x4660c3 MOVHPD	(%R15,%RBP,8),%XMM1

    (1351) 0x4660c9 MULPD	%XMM2,%XMM1

    (1351) 0x4660cd ADDPD	%XMM3,%XMM1

    (1351) 0x4660d1 MOVAPD	%XMM1,%XMM2

    (1351) 0x4660d5 UNPCKHPD	%XMM1,%XMM2

    (1351) 0x4660d9 ADDSD	%XMM1,%XMM2

    (1351) 0x4660dd ADDSD	%XMM2,%XMM0

    (1351) 0x4660e1 ADD	$0x20,%RSI

    (1351) 0x4660e5 DEC	%R8

    (1351) 0x4660e8 JNE	466070

  (1350) 0x4660ea MOV	%RDI,%R8

  (1350) 0x4660ed AND	$-0x4,%R8

  (1350) 0x4660f1 AND	$0x3,%EDI

  (1350) 0x4660f4 CMP	$0x1,%RDI

  (1350) 0x4660f8 JE	4661ae

  (1350) 0x4660fe CMP	$0x2,%EDI

  (1350) 0x466101 JE	466166

  (1350) 0x466103 CMP	$0x3,%EDI

  (1350) 0x466106 MOV	0x20(%RSP),%RBP

  (1350) 0x46610b MOV	0x28(%RSP),%R9

  (1350) 0x466110 JNE	465fc4

  (1350) 0x466116 LEA	(%R10,%R8,1),%RCX

  (1350) 0x46611a MOV	%RCX,0xf0(%RSP)

  (1350) 0x466122 MOV	0x10(%R13,%RCX,8),%RDX

  (1350) 0x466127 IMUL	%R12,%RDX

  (1350) 0x46612b MOV	0xe0(%RSP),%RCX

  (1350) 0x466133 MOV	%RBP,%RDI

  (1350) 0x466136 MOV	0x18(%RSP),%RBP

  (1350) 0x46613b LEA	(%RCX,%RBP,1),%RSI

  (1350) 0x46613f ADD	%RDI,%RSI

  (1350) 0x466142 ADD	%R9,%RSI

  (1350) 0x466145 ADD	%RDX,%RSI

  (1350) 0x466148 MOVSD	(%R15,%RSI,8),%XMM1

  (1350) 0x46614e MOV	0xf0(%RSP),%RDX

  (1350) 0x466156 MULSD	0x10(%R14,%RDX,8),%XMM1

  (1350) 0x46615d ADDSD	%XMM1,%XMM0

  (1350) 0x466161 MOV	%RCX,%RSI

  (1350) 0x466164 JMP	46617d

  (1350) 0x466166 MOV	0xe8(%RSP),%RSI

  (1350) 0x46616e MOV	0x20(%RSP),%RDI

  (1350) 0x466173 MOV	0x28(%RSP),%R9

  (1350) 0x466178 MOV	0x18(%RSP),%RBP

  (1350) 0x46617d ADD	%R8,%RBX

  (1350) 0x466180 MOV	(%R13,%RBX,8),%RCX

  (1350) 0x466185 IMUL	%R12,%RCX

  (1350) 0x466189 LEA	(%RSI,%RBP,1),%RDX

  (1350) 0x46618d ADD	%RDI,%RDX

  (1350) 0x466190 ADD	%R9,%RDX

  (1350) 0x466193 ADD	%RCX,%RDX

  (1350) 0x466196 MOVSD	(%R15,%RDX,8),%XMM1

  (1350) 0x46619c MULSD	(%R14,%RBX,8),%XMM1

  (1350) 0x4661a2 ADDSD	%XMM1,%XMM0

  (1350) 0x4661a6 MOV	%RBP,%RBX

  (1350) 0x4661a9 MOV	%RDI,%RBP

  (1350) 0x4661ac JMP	4661c2

  (1350) 0x4661ae MOV	0x50(%RSP),%RSI

  (1350) 0x4661b3 MOV	0x20(%RSP),%RBP

  (1350) 0x4661b8 MOV	0x28(%RSP),%R9

  (1350) 0x4661bd MOV	0x18(%RSP),%RBX

  (1350) 0x4661c2 ADD	%R8,%R10

  (1350) 0x4661c5 MOV	(%R13,%R10,8),%RCX

  (1350) 0x4661ca IMUL	%R12,%RCX

  (1350) 0x4661ce ADD	%RBX,%RSI

  (1350) 0x4661d1 ADD	%RBP,%RSI

  (1350) 0x4661d4 ADD	%R9,%RSI

  (1350) 0x4661d7 ADD	%RCX,%RSI

  (1350) 0x4661da MOVSD	(%R15,%RSI,8),%XMM1

  (1350) 0x4661e0 MULSD	(%R14,%R10,8),%XMM1

  (1350) 0x4661e6 ADDSD	%XMM1,%XMM0

  (1350) 0x4661ea JMP	465fc4

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

Coverage (%)	Name	Module
►89.45+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►6.40+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
►2.42+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	Kripke::Kernel::scattering(Kri[...]	exec
○	Kripke::SteadyStateSolver(Krip[...]	exec
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	9.60
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P6, P7, P8, P9,
Function	void Kripke::DispatchHelper::operator()&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&>(Kripke::LayoutT_DGZ, ScatteringSdom const&, Kripke::SdomId&, Kripke::SdomId&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.31
Front-end cycles	2.75
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	22.00
Nb loads	9.00
Nb stores	3.00
Nb stack references	11.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.81
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.42

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	9.60
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P6, P7, P8, P9,
Function	void Kripke::DispatchHelper::operator()&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&>(Kripke::LayoutT_DGZ, ScatteringSdom const&, Kripke::SdomId&, Kripke::SdomId&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.31
Front-end cycles	2.75
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	22.00
Nb loads	9.00
Nb stores	3.00
Nb stack references	11.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.81
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.42

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void Kripke::DispatchHelper::operator()&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&>(Kripke::LayoutT_DGZ, ScatteringSdom const&, Kripke::SdomId&, Kripke::SdomId&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source file and lines
Module	exec

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=10
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 10 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.31 cycles (9.60x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 3.00 to 2.75 cycles (1.09x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	22
nb uops	22
loop length	109
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.75 cycles
front end	2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.00	2.00	2.00	2.00	2.00	2.00	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.00	2.00	2.00	2.00	2.00	2.00	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.75
Dispatch	3.00
Overall L1	3.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

9% of peak load performance is reached (24.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 465f62

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
LEA 0x1(%R9),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
CMP 0x48(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 465e60 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x210>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPQ $0,0x10(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JLE 465f50 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x300>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0xd0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0xd8(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX,%RCX,8),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
IMUL 0xc0(%RSP),%RBX	1	0.33	0.33	0.33	0	0	0	0.25	0.25	0.25	0.25	3	0.33	scal (12.5%)
ADD 0xc8(%RSP),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
MOV 0x40(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %R9,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RAX,0x128(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x50(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RBP,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %R9,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %R9,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RBX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 466013 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x3c3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Function	void Kripke::DispatchHelper::operator()&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&>(Kripke::LayoutT_DGZ, ScatteringSdom const&, Kripke::SdomId&, Kripke::SdomId&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source file and lines
Module	exec

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=10
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 3.00 to 2.75 cycles (1.09x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	22
nb uops	22
loop length	109
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.75 cycles
front end	2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.00	2.00	2.00	2.00	2.00	2.00	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.00	2.00	2.00	2.00	2.00	2.00	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.75
Dispatch	3.00
Overall L1	3.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

9% of peak load performance is reached (24.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 465f62

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
LEA 0x1(%R9),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
CMP 0x48(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 465e60 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x210>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPQ $0,0x10(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JLE 465f50 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x300>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0xd0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0xd8(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX,%RCX,8),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
IMUL 0xc0(%RSP),%RBX	1	0.33	0.33	0.33	0	0	0	0.25	0.25	0.25	0.25	3	0.33	scal (12.5%)
ADD 0xc8(%RSP),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
MOV 0x40(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %R9,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RAX,0x128(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x50(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RBP,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %R9,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %R9,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RBX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 466013 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x3c3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code