OV - exec - Function Kripke::ParallelComm::getReadyList()

	Function: Kripke::ParallelComm::getReadyList()	Module: exec	Source: ParallelComm.cpp:254-263 [...]	Coverage (incl. loops): 0.01% \| (excl. loops): 0.01%

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h: 127 - 162

--------------------------------------------------------------------------------

127: 	return static_cast<_Tp*>(::operator new(__n * sizeof(_Tp)));

[...]

145: 	::operator delete(__p

[...]

162: 	{ ::new((void *)__p) _Up(std::forward<_Args>(__args)...); }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 98 - 1762

--------------------------------------------------------------------------------

98: 	: _M_start(), _M_finish(), _M_end_of_storage()

[...]

346: 	return __n != 0 ? _Tr::allocate(_M_impl, __n) : pointer();

[...]

353: 	if (__p)

[...]

919:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1046: 	return *(this->_M_impl._M_start + __n);

[...]

1758: 	if (max_size() - size() < __n)

1759: 	  __throw_length_error(__N(__s));

1760:

1761: 	const size_type __len = size() + (std::max)(size(), __n);

1762: 	return (__len < size() || __len > max_size()) ? max_size() : __len;

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_uninitialized.h: 1031 - 1031

--------------------------------------------------------------------------------

1031:       for (; __first != __last; ++__first, (void)++__cur)

/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp: 254 - 263

--------------------------------------------------------------------------------

254: std::vector<SdomId> ParallelComm::getReadyList(void){

255:   // build up a list of ready subdomains

256:   std::vector<SdomId> ready;

257:   for(size_t i = 0;i < queue_depends.size();++ i){

258:     if(queue_depends[i] == 0){

259:       ready.push_back(SdomId(queue_sdom_ids[i]));

260:     }

261:   }

262:   return ready;

263: }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/vector.tcc: 112 - 504

--------------------------------------------------------------------------------

112: 	if (this->_M_impl._M_finish != this->_M_impl._M_end_of_storage)

113: 	  {

114: 	    _GLIBCXX_ASAN_ANNOTATE_GROW(1);

115: 	    _Alloc_traits::construct(this->_M_impl, this->_M_impl._M_finish,

116: 				     std::forward<_Args>(__args)...);

117: 	    ++this->_M_impl._M_finish;

[...]

502:       this->_M_impl._M_start = __new_start;

503:       this->_M_impl._M_finish = __new_finish;

504:       this->_M_impl._M_end_of_storage = __new_start + __len;

0x279320 PUSH	%RBP

0x279321 MOV	%RSP,%RBP

0x279324 PUSH	%R15

0x279326 PUSH	%R14

0x279328 PUSH	%R13

0x27932a PUSH	%R12

0x27932c PUSH	%RBX

0x27932d SUB	$0x28,%RSP

0x279331 XORPS	%XMM0,%XMM0

0x279334 MOVUPS	%XMM0,(%RDI)

0x279337 MOVQ	$0,0x10(%RDI)

0x27933f MOV	0x70(%RSI),%RCX

0x279343 CMP	%RCX,0x78(%RSI)

0x279347 JE	2794e8

0x27934d XOR	%R13D,%R13D

0x279350 XOR	%EBX,%EBX

0x279352 XOR	%EAX,%EAX

0x279354 XOR	%R14D,%R14D

0x279357 MOV	%RDI,-0x30(%RBP)

0x27935b MOV	%RSI,-0x38(%RBP)

0x27935f JMP	27939c

0x279361 NOPW	%CS:(%RAX,%RAX,1)

(1296) 0x279370 MOV	%R8,(%RBX)

(1296) 0x279373 ADD	$0x8,%RBX

(1296) 0x279377 MOV	%RBX,0x8(%RDI)

(1296) 0x27937b MOV	%R14,%R15

(1296) 0x27937e INC	%R13

(1296) 0x279381 MOV	0x70(%RSI),%RCX

(1296) 0x279385 MOV	0x78(%RSI),%RDX

(1296) 0x279389 SUB	%RCX,%RDX

(1296) 0x27938c SAR	$0x2,%RDX

(1296) 0x279390 MOV	%R15,%R14

(1296) 0x279393 CMP	%RDX,%R13

(1296) 0x279396 JAE	2794e8

(1296) 0x27939c CMPL	$0,(%RCX,%R13,4)

(1296) 0x2793a1 JNE	27937b

(1296) 0x2793a3 MOV	0x58(%RSI),%RCX

(1296) 0x2793a7 MOVSXD	(%RCX,%R13,4),%R8

(1296) 0x2793ab CMP	%RAX,%RBX

(1296) 0x2793ae JNE	279370

(1296) 0x2793b0 MOV	%RBX,%RSI

(1296) 0x2793b3 SUB	%R14,%RSI

(1296) 0x2793b6 MOV	$0x7ffffffffffffff8,%RAX

(1296) 0x2793c0 CMP	%RAX,%RSI

(1296) 0x2793c3 JE	2794fa

(1296) 0x2793c9 MOV	%RSI,%R12

(1296) 0x2793cc SAR	$0x3,%R12

(1296) 0x2793d0 CMP	$0x1,%R12

(1296) 0x2793d4 MOV	%R12,%RAX

(1296) 0x2793d7 ADC	$0,%RAX

(1296) 0x2793db LEA	(%RAX,%R12,1),%RDX

(1296) 0x2793df MOV	$0xfffffffffffffff,%RCX

(1296) 0x2793e9 CMP	%RCX,%RDX

(1296) 0x2793ec CMOVA	%RCX,%RDX

(1296) 0x2793f0 ADD	%R12,%RAX

(1296) 0x2793f3 CMOVB	%RCX,%RDX

(1296) 0x2793f7 TEST	%RDX,%RDX

(1296) 0x2793fa MOV	%RDX,-0x50(%RBP)

(1296) 0x2793fe JE	279435

(1296) 0x279400 MOV	%R8,-0x40(%RBP)

(1296) 0x279404 MOV	%RSI,-0x48(%RBP)

(1296) 0x279408 LEA	(,%RDX,8),%RDI

(1296) 0x279410 CALL	2ac340 <@plt_start@+0x130>

(1296) 0x279415 MOV	%RAX,%R15

(1296) 0x279418 MOV	-0x30(%RBP),%RDI

(1296) 0x27941c MOV	-0x48(%RBP),%RSI

(1296) 0x279420 MOV	-0x40(%RBP),%R8

(1296) 0x279424 MOV	%R8,(%R15,%R12,8)

(1296) 0x279428 MOV	%R15,%R12

(1296) 0x27942b CMP	%RBX,%R14

(1296) 0x27942e JNE	279444

(1296) 0x279430 JMP	2794b4

(1296) 0x279435 XOR	%R15D,%R15D

(1296) 0x279438 MOV	%R8,(%R15,%R12,8)

(1296) 0x27943c MOV	%R15,%R12

(1296) 0x27943f CMP	%RBX,%R14

(1296) 0x279442 JE	2794b4

(1296) 0x279444 ADD	$-0x8,%RSI

(1296) 0x279448 MOV	%R15,%R12

(1296) 0x27944b MOV	%R14,%RAX

(1296) 0x27944e CMP	$0x18,%RSI

(1296) 0x279452 JB	2794a0

(1296) 0x279454 SHR	$0x3,%RSI

(1296) 0x279458 INC	%RSI

(1296) 0x27945b MOV	%RSI,%RCX

(1296) 0x27945e AND	$-0x4,%RCX

(1296) 0x279462 LEA	(%R15,%RCX,8),%R12

(1296) 0x279466 LEA	(%R14,%RCX,8),%RAX

(1296) 0x27946a XOR	%EDX,%EDX

(1296) 0x27946c NOPL	(%RAX)

  (1298) 0x279470 MOVUPS	(%R14,%RDX,8),%XMM0

  (1298) 0x279475 MOVUPS	0x10(%R14,%RDX,8),%XMM1

  (1298) 0x27947b MOVUPS	%XMM0,(%R15,%RDX,8)

  (1298) 0x279480 MOVUPS	%XMM1,0x10(%R15,%RDX,8)

  (1298) 0x279486 ADD	$0x4,%RDX

  (1298) 0x27948a CMP	%RDX,%RCX

  (1298) 0x27948d JNE	279470

(1296) 0x27948f CMP	%RCX,%RSI

(1296) 0x279492 JE	2794b4

(1296) 0x279494 NOPW	%CS:(%RAX,%RAX,1)

  (1297) 0x2794a0 MOV	(%RAX),%RCX

  (1297) 0x2794a3 MOV	%RCX,(%R12)

  (1297) 0x2794a7 ADD	$0x8,%RAX

  (1297) 0x2794ab ADD	$0x8,%R12

  (1297) 0x2794af CMP	%RBX,%RAX

  (1297) 0x2794b2 JNE	2794a0

(1296) 0x2794b4 TEST	%R14,%R14

(1296) 0x2794b7 JE	2794c5

(1296) 0x2794b9 MOV	%R14,%RDI

(1296) 0x2794bc CALL	2ac270 <@plt_start@+0x60>

(1296) 0x2794c1 MOV	-0x30(%RBP),%RDI

(1296) 0x2794c5 ADD	$0x8,%R12

(1296) 0x2794c9 MOV	%R15,(%RDI)

(1296) 0x2794cc MOV	%R12,0x8(%RDI)

(1296) 0x2794d0 MOV	-0x50(%RBP),%RAX

(1296) 0x2794d4 LEA	(%R15,%RAX,8),%RAX

(1296) 0x2794d8 MOV	%RAX,0x10(%RDI)

(1296) 0x2794dc MOV	%R12,%RBX

(1296) 0x2794df MOV	-0x38(%RBP),%RSI

(1296) 0x2794e3 JMP	27937e

0x2794e8 MOV	%RDI,%RAX

0x2794eb ADD	$0x28,%RSP

0x2794ef POP	%RBX

0x2794f0 POP	%R12

0x2794f2 POP	%R13

0x2794f4 POP	%R14

0x2794f6 POP	%R15

0x2794f8 POP	%RBP

0x2794f9 RET

0x2794fa LEA	-0x73ba8(%RIP),%RDI

0x279501 CALL	2ac350 <@plt_start@+0x140>

0x279506 JMP	279508

0x279508 MOV	%RAX,%RBX

0x27950b TEST	%R14,%R14

0x27950e JE	279518

0x279510 MOV	%R14,%RDI

0x279513 CALL	2ac270 <@plt_start@+0x60>

0x279518 MOV	%RBX,%RDI

0x27951b CALL	2ac320 <@plt_start@+0x110>

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run orig_0

Source file and lines	ParallelComm.cpp:254-263
Module	exec

The function is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:127,145,162
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:98,346,353,919,1046,1758-1762
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_uninitialized.h:1031
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp:254-263
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/vector.tcc:112-117,502-504

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.38 to 0.67 cycles (8.06x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 5.38 to 0.41 cycles (13.12x speedup).

Details

16% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
25% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
20% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1759
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:145
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:145

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

MOVUPS: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:98

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	41
nb uops	43
loop length	136
used x86 registers	11
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.38 cycles
front end	5.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.67	1.67	1.67	2.67	2.67	2.67	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.50	0.50
cycles	1.67	1.67	1.67	2.67	2.67	2.67	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.38
Dispatch	2.67
Overall L1	5.38

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	16%
load	0%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	10%
load	12%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	13%
load	12%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.38 cycles. At this rate:

1% of peak load performance is reached (2.98 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.44 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.38 to 2.67 cycles (2.02x speedup).

ASM code

In the binary file, the address of the function is: 279320

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
XORPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVUPS %XMM0,(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (25.0%)
MOVQ $0,0x10(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV 0x70(%RSI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
CMP %RCX,0x78(%RSI)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JE 2794e8 <_ZN6Kripke12ParallelComm12getReadyListEv+0x1c8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RDI,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RSI,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
JMP 27939c <_ZN6Kripke12ParallelComm12getReadyListEv+0x7c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
LEA -0x73ba8(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
CALL 2ac350 <@plt_start@+0x140>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
JMP 279508 <_ZN6Kripke12ParallelComm12getReadyListEv+0x1e8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
TEST %R14,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JE 279518 <_ZN6Kripke12ParallelComm12getReadyListEv+0x1f8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2ac270 <@plt_start@+0x60>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2ac320 <@plt_start@+0x110>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run orig_0

Source file and lines	ParallelComm.cpp:254-263
Module	exec

The function is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:127,145,162
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:98,346,353,919,1046,1758-1762
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_uninitialized.h:1031
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp:254-263
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/vector.tcc:112-117,502-504

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.38 to 0.67 cycles (8.06x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

16% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
25% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
20% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1759
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:145
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:145

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

MOVUPS: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:98

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	41
nb uops	43
loop length	136
used x86 registers	11
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.38 cycles
front end	5.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.67	1.67	1.67	2.67	2.67	2.67	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.50	0.50
cycles	1.67	1.67	1.67	2.67	2.67	2.67	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.38
Dispatch	2.67
Overall L1	5.38

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	16%
load	0%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	10%
load	12%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	13%
load	12%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.38 cycles. At this rate:

1% of peak load performance is reached (2.98 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.44 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 279320

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
XORPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVUPS %XMM0,(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (25.0%)
MOVQ $0,0x10(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV 0x70(%RSI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
CMP %RCX,0x78(%RSI)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JE 2794e8 <_ZN6Kripke12ParallelComm12getReadyListEv+0x1c8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RDI,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RSI,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
JMP 27939c <_ZN6Kripke12ParallelComm12getReadyListEv+0x7c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
LEA -0x73ba8(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
CALL 2ac350 <@plt_start@+0x140>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
JMP 279508 <_ZN6Kripke12ParallelComm12getReadyListEv+0x1e8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
TEST %R14,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JE 279518 <_ZN6Kripke12ParallelComm12getReadyListEv+0x1f8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2ac270 <@plt_start@+0x60>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2ac320 <@plt_start@+0x110>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A

Name	Coverage (%)	Time (s)
▼Kripke::ParallelComm::getReadyList()–	0.01	0.00
▼Loop 1296 - vector.tcc:112-504 - exec–	0.01	0.03
○Loop 1297 - stl_uninitialized.h:1031-1031 - exec	0.00	0.00
○Loop 1298 - new_allocator.h:162-162 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code