OV - exec - Function Kripke::ParallelComm::testRecieves()

	Function: Kripke::ParallelComm::testRecieves()	Module: exec	Source: ParallelComm.cpp:214-251 [...]	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_construct.h: 119 - 119

--------------------------------------------------------------------------------

119:       ::new((void*)__p) _Tp(std::forward<_Args>(__args)...);

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h: 127 - 145

--------------------------------------------------------------------------------

127: 	return static_cast<_Tp*>(::operator new(__n * sizeof(_Tp)));

[...]

145: 	::operator delete(__p

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 919 - 1046

--------------------------------------------------------------------------------

919:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1046: 	return *(this->_M_impl._M_start + __n);

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h: 429 - 1115

--------------------------------------------------------------------------------

429: 	  const ptrdiff_t _Num = __last - __first;

430: 	  if (_Num)

431: 	    __builtin_memmove(__result, __first, sizeof(_Tp) * _Num);

[...]

911:       for (; __first != __last; ++__first)

912: 	*__first = __value;

[...]

1115:       if (__n <= 0)

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_iterator.h: 1028 - 1182

--------------------------------------------------------------------------------

1028:       : _M_current(__i) { }

[...]

1091:       { return __normal_iterator(_M_current + __n); }

[...]

1182:     { return __lhs.base() != __rhs.base(); }

/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp: 214 - 251

--------------------------------------------------------------------------------

214: void ParallelComm::testRecieves(void){

215: #ifdef KRIPKE_USE_MPI

216:   // Check for any recv requests that have completed

217:   int num_requests = recv_requests.size();

218:   bool done = false;

219:   while(!done && num_requests > 0){

220:     // Create array of status variables

221:     std::vector<MPI_Status> recv_status(num_requests);

222:

223:     // Ask if either one or none of the recvs have completed?

224:     int index; // this will be the index of request that completed

225:     int complete_flag; // this is set to TRUE if somthing completed

226:     MPI_Testany(num_requests, &recv_requests[0], &index, &complete_flag, &recv_status[0]);

227:

228:     if(complete_flag != 0){

229:

230:       // get subdomain that this completed for

231:       int sdom_id = recv_subdomains[index];

232:

233:       // remove the request from the list

234:       recv_requests.erase(recv_requests.begin()+index);

235:       recv_subdomains.erase(recv_subdomains.begin()+index);

236:       num_requests --;

237:

238:       // decrement the dependency count for that subdomain

239:       for(size_t i = 0;i < queue_sdom_ids.size();++ i){

240:         if(queue_sdom_ids[i] == sdom_id){

241:           queue_depends[i] --;

[...]

251: }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/vector.tcc: 174 - 176

--------------------------------------------------------------------------------

174:       if (__position + 1 != end())

175: 	_GLIBCXX_MOVE3(__position + 1, end(), __position);

176:       --this->_M_impl._M_finish;

0x279180 PUSH	%RBP

0x279181 MOV	%RSP,%RBP

0x279184 PUSH	%R15

0x279186 PUSH	%R14

0x279188 PUSH	%R13

0x27918a PUSH	%R12

0x27918c PUSH	%RBX

0x27918d PUSH	%RAX

0x27918e MOV	0x30(%RDI),%R14

0x279192 SUB	0x28(%RDI),%R14

0x279196 SHR	$0x2,%R14

0x27919a TEST	%R14D,%R14D

0x27919d JLE	2792f1

0x2791a3 MOV	%RDI,%RBX

0x2791a6 XOR	%R12D,%R12D

0x2791a9 NOPL	(%RAX)

(1293) 0x2791b0 MOV	%R14D,%EAX

(1293) 0x2791b3 SAL	$0x2,%RAX

(1293) 0x2791b7 LEA	(%RAX,%RAX,4),%R15

(1293) 0x2791bb MOV	%R15,%RDI

(1293) 0x2791be CALL	2ac340 <@plt_start@+0x130>

(1293) 0x2791c3 MOV	%RAX,%R13

(1293) 0x2791c6 XORPS	%XMM0,%XMM0

(1293) 0x2791c9 MOVUPS	%XMM0,(%RAX)

(1293) 0x2791cc MOVL	$0,0x10(%RAX)

(1293) 0x2791d3 CMP	$0x1,%R14D

(1293) 0x2791d7 JE	2791fd

(1293) 0x2791d9 MOV	$0x14,%EAX

(1293) 0x2791de XCHG	%AX,%AX

  (1295) 0x2791e0 MOV	0x10(%R13),%ECX

  (1295) 0x2791e4 MOV	%ECX,0x10(%R13,%RAX,1)

  (1295) 0x2791e9 MOVUPS	(%R13),%XMM0

  (1295) 0x2791ee MOVUPS	%XMM0,(%R13,%RAX,1)

  (1295) 0x2791f4 ADD	$0x14,%RAX

  (1295) 0x2791f8 CMP	%RAX,%R15

  (1295) 0x2791fb JNE	2791e0

(1293) 0x2791fd MOV	0x28(%RBX),%RSI

(1293) 0x279201 MOV	%R14D,%EDI

(1293) 0x279204 LEA	-0x2c(%RBP),%RDX

(1293) 0x279208 LEA	-0x30(%RBP),%RCX

(1293) 0x27920c MOV	%R13,%R8

(1293) 0x27920f CALL	2ac6b0 <@plt_start@+0x4a0>

(1293) 0x279214 CMPL	$0,-0x30(%RBP)

(1293) 0x279218 JE	2792c0

(1293) 0x27921e MOVSXD	-0x2c(%RBP),%RAX

(1293) 0x279222 MOV	0x40(%RBX),%RCX

(1293) 0x279226 MOV	(%RCX,%RAX,4),%R15D

(1293) 0x27922a MOV	0x28(%RBX),%RDI

(1293) 0x27922e MOV	0x30(%RBX),%RDX

(1293) 0x279232 LEA	(%RDI,%RAX,4),%RSI

(1293) 0x279236 ADD	$0x4,%RSI

(1293) 0x27923a CMP	%RDX,%RSI

(1293) 0x27923d JE	279257

(1293) 0x27923f LEA	(%RDI,%RAX,4),%RDI

(1293) 0x279243 SUB	%RSI,%RDX

(1293) 0x279246 CALL	2ac570 <@plt_start@+0x360>

(1293) 0x27924b MOV	0x30(%RBX),%RSI

(1293) 0x27924f MOV	0x40(%RBX),%RCX

(1293) 0x279253 MOVSXD	-0x2c(%RBP),%RAX

(1293) 0x279257 ADD	$-0x4,%RSI

(1293) 0x27925b MOV	%RSI,0x30(%RBX)

(1293) 0x27925f LEA	(%RCX,%RAX,4),%RSI

(1293) 0x279263 ADD	$0x4,%RSI

(1293) 0x279267 MOV	0x48(%RBX),%RDX

(1293) 0x27926b CMP	%RDX,%RSI

(1293) 0x27926e JE	279280

(1293) 0x279270 LEA	(%RCX,%RAX,4),%RDI

(1293) 0x279274 SUB	%RSI,%RDX

(1293) 0x279277 CALL	2ac570 <@plt_start@+0x360>

(1293) 0x27927c MOV	0x48(%RBX),%RSI

(1293) 0x279280 ADD	$-0x4,%RSI

(1293) 0x279284 MOV	%RSI,0x48(%RBX)

(1293) 0x279288 DEC	%R14D

(1293) 0x27928b MOV	0x58(%RBX),%RAX

(1293) 0x27928f MOV	0x60(%RBX),%RCX

(1293) 0x279293 SUB	%RAX,%RCX

(1293) 0x279296 JE	2792c3

(1293) 0x279298 SAR	$0x2,%RCX

(1293) 0x27929c CMP	$0x1,%RCX

(1293) 0x2792a0 ADC	$0,%RCX

(1293) 0x2792a4 XOR	%EDX,%EDX

(1293) 0x2792a6 NOPW	%CS:(%RAX,%RAX,1)

  (1294) 0x2792b0 CMP	%R15D,(%RAX,%RDX,4)

  (1294) 0x2792b4 JE	2792dc

  (1294) 0x2792b6 INC	%RDX

  (1294) 0x2792b9 CMP	%RDX,%RCX

  (1294) 0x2792bc JNE	2792b0

(1293) 0x2792be JMP	2792c3

(1293) 0x2792c0 MOV	$0x1,%R12B

(1293) 0x2792c3 MOV	%R13,%RDI

(1293) 0x2792c6 CALL	2ac270 <@plt_start@+0x60>

(1293) 0x2792cb TEST	$0x1,%R12B

(1293) 0x2792cf JNE	2792f1

(1293) 0x2792d1 TEST	%R14D,%R14D

(1293) 0x2792d4 JG	2791b0

0x2792da JMP	2792f1

(1293) 0x2792dc MOV	0x70(%RBX),%RAX

(1293) 0x2792e0 DECL	(%RAX,%RDX,4)

(1293) 0x2792e3 MOV	%R13,%RDI

(1293) 0x2792e6 CALL	2ac270 <@plt_start@+0x60>

(1293) 0x2792eb TEST	$0x1,%R12B

(1293) 0x2792ef JE	2792d1

0x2792f1 ADD	$0x8,%RSP

0x2792f5 POP	%RBX

0x2792f6 POP	%R12

0x2792f8 POP	%R13

0x2792fa POP	%R14

0x2792fc POP	%R15

0x2792fe POP	%RBP

0x2792ff RET

0x279300 MOV	%RAX,%RBX

0x279303 MOV	%R13,%RDI

0x279306 CALL	2ac270 <@plt_start@+0x60>

0x27930b MOV	%RBX,%RDI

0x27930e CALL	2ac320 <@plt_start@+0x110>

0x279313 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	ParallelComm.cpp:214-251
Module	exec

The function is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_construct.h:119
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:127,145
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:919,1046
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:429-431,911-912,1115
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_iterator.h:1028,1091,1182
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp:214-241,251
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/vector.tcc:174-176

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 3.88 to 0.27 cycles (14.59x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:145
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:145

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes.

General properties

nb instructions	31
nb uops	31
loop length	97
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.88 cycles
front end	3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	2.00	2.00	2.00	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	1.00	2.00	2.00	2.00	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.88
Dispatch	2.00
Overall L1	3.88

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.88 cycles. At this rate:

1% of peak load performance is reached (4.13 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.88 to 2.00 cycles (1.94x speedup).

ASM code

In the binary file, the address of the function is: 279180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV 0x30(%RDI),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
SUB 0x28(%RDI),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
SHR $0x2,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
TEST %R14D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 2792f1 <_ZN6Kripke12ParallelComm12testRecievesEv+0x171>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 2792f1 <_ZN6Kripke12ParallelComm12testRecievesEv+0x171>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2ac270 <@plt_start@+0x60>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2ac320 <@plt_start@+0x110>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	ParallelComm.cpp:214-251
Module	exec

The function is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_construct.h:119
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:127,145
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:919,1046
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:429-431,911-912,1115
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_iterator.h:1028,1091,1182
/home/eoseret/qaas_runs_ZEN5/173-940-2141/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp:214-241,251
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/vector.tcc:174-176

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:145
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:145

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes.

General properties

nb instructions	31
nb uops	31
loop length	97
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.88 cycles
front end	3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	2.00	2.00	2.00	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	1.00	2.00	2.00	2.00	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.88
Dispatch	2.00
Overall L1	3.88

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.88 cycles. At this rate:

1% of peak load performance is reached (4.13 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 279180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV 0x30(%RDI),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
SUB 0x28(%RDI),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
SHR $0x2,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
TEST %R14D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 2792f1 <_ZN6Kripke12ParallelComm12testRecievesEv+0x171>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 2792f1 <_ZN6Kripke12ParallelComm12testRecievesEv+0x171>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2ac270 <@plt_start@+0x60>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2ac320 <@plt_start@+0x110>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼Kripke::ParallelComm::testRecieves()–	0.01	0.00
▼Loop 1293 - ParallelComm.cpp:219-241 - exec–	0.00	0.01
○Loop 1295 - stl_algobase.h:911-912 - exec	0.01	0.04
○Loop 1294 - ParallelComm.cpp:239-240 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code