OV - - Loop 902 - libkripke.so

	Loop Id: 902	Module: libkripke.so	Source: forall.hpp:59-59 [...]	Coverage: 2.63%

0x5b7ad VMOVSD	(%RSI),%XMM14    [2]

0x5b7b1 VMOVSD	(%RBX,%RAX,8),%XMM15    [3]

0x5b7b6 VMOVSD	0x8(%RBX,%RAX,8),%XMM7    [3]

0x5b7bc VFMADD132SD	(%RCX,%RAX,8),%XMM15,%XMM14    [1]

0x5b7c2 VMOVSD	0x10(%RBX,%RAX,8),%XMM2    [3]

0x5b7c8 VMOVSD	%XMM14,(%RBX,%RAX,8)    [3]

0x5b7cd VMOVSD	0x18(%RBX,%RAX,8),%XMM6    [3]

0x5b7d3 VMOVSD	(%RSI),%XMM0    [2]

0x5b7d7 VMOVSD	0x20(%RBX,%RAX,8),%XMM5    [3]

0x5b7dd VFMADD132SD	0x8(%RCX,%RAX,8),%XMM7,%XMM0    [1]

0x5b7e4 VMOVSD	0x28(%RBX,%RAX,8),%XMM9    [3]

0x5b7ea VMOVSD	%XMM0,0x8(%RBX,%RAX,8)    [3]

0x5b7f0 VMOVSD	0x30(%RBX,%RAX,8),%XMM11    [3]

0x5b7f6 VMOVSD	(%RSI),%XMM1    [2]

0x5b7fa VMOVSD	0x38(%RBX,%RAX,8),%XMM13    [3]

0x5b800 VFMADD132SD	0x10(%RCX,%RAX,8),%XMM2,%XMM1    [1]

0x5b807 VMOVSD	%XMM1,0x10(%RBX,%RAX,8)    [3]

0x5b80d VMOVSD	(%RSI),%XMM3    [2]

0x5b811 VFMADD132SD	0x18(%RCX,%RAX,8),%XMM6,%XMM3    [1]

0x5b818 VMOVSD	%XMM3,0x18(%RBX,%RAX,8)    [3]

0x5b81e VMOVSD	(%RSI),%XMM4    [2]

0x5b822 VFMADD132SD	0x20(%RCX,%RAX,8),%XMM5,%XMM4    [1]

0x5b829 VMOVSD	%XMM4,0x20(%RBX,%RAX,8)    [3]

0x5b82f VMOVSD	(%RSI),%XMM8    [2]

0x5b833 VFMADD132SD	0x28(%RCX,%RAX,8),%XMM9,%XMM8    [1]

0x5b83a VMOVSD	%XMM8,0x28(%RBX,%RAX,8)    [3]

0x5b840 VMOVSD	(%RSI),%XMM10    [2]

0x5b844 VFMADD132SD	0x30(%RCX,%RAX,8),%XMM11,%XMM10    [1]

0x5b84b VMOVSD	%XMM10,0x30(%RBX,%RAX,8)    [3]

0x5b851 VMOVSD	(%RSI),%XMM12    [2]

0x5b855 VFMADD132SD	0x38(%RCX,%RAX,8),%XMM13,%XMM12    [1]

0x5b85c VMOVSD	%XMM12,0x38(%RBX,%RAX,8)    [3]

0x5b862 ADD	$0x8,%RAX

0x5b866 CMP	%RAX,%RDI

0x5b869 JNE	5b7ad

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp: 57 - 57

--------------------------------------------------------------------------------

57:             rhs(d,g,z) += ell_plus(d, nm) * phi_out(nm, g, z);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.57
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.88
Bottlenecks	P5, P6, P7,
Function	_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0
Source	forall.hpp:59-59,LPlusTimes.cpp:57-57
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.67
CQA cycles if no scalar integer	10.67
CQA cycles if FP arith vectorized	10.67
CQA cycles if fully vectorized	2.33
Front-end cycles	5.67
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	10.67
P5 cycles	10.67
P6 cycles	10.67
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	34.00
Nb loads	24.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	1.50
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.57
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.88
Bottlenecks	P5, P6, P7,
Function	_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0
Source	forall.hpp:59-59,LPlusTimes.cpp:57-57
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.67
CQA cycles if no scalar integer	10.67
CQA cycles if FP arith vectorized	10.67
CQA cycles if fully vectorized	2.33
Front-end cycles	5.67
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	10.67
P5 cycles	10.67
P6 cycles	10.67
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	34.00
Nb loads	24.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	1.50
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0
Source file and lines	forall.hpp:59-59
Module	libkripke.so

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp:57

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 10.67 to 2.33 cycles (4.57x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 10.67 to 5.67 cycles (1.88x speedup).

Workaround

Read less array elements All SSE and/or AVX registers are used: in that case, try to relax register pressure by reducing the unroll factor or splitting your loop
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 8 FMA (fused multiply-add) operations.

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 192 bytes (24 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	35
nb uops	34
loop length	194
used x86 registers	5
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.67 cycles
front end	5.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	10.67	10.67	10.67	4.00	4.00	0.00	0.00	4.00	4.00
cycles	0.50	0.50	0.25	0.25	0.50	10.67	10.67	10.67	4.00	4.00	0.00	0.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.67
Dispatch	10.67
Data deps.	1.00
Overall L1	10.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.67 cycles. At this rate:

18% of peak load performance is reached (18.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (6.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 5b7ad

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
VMOVSD (%RSI),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD (%RBX,%RAX,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD 0x8(%RBX,%RAX,8),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD (%RCX,%RAX,8),%XMM15,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD 0x10(%RBX,%RAX,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD %XMM14,(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD 0x18(%RBX,%RAX,8),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD (%RSI),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD 0x20(%RBX,%RAX,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD 0x8(%RCX,%RAX,8),%XMM7,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD 0x28(%RBX,%RAX,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD %XMM0,0x8(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD 0x30(%RBX,%RAX,8),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD (%RSI),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD 0x38(%RBX,%RAX,8),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD 0x10(%RCX,%RAX,8),%XMM2,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM1,0x10(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD (%RSI),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD 0x18(%RCX,%RAX,8),%XMM6,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM3,0x18(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD (%RSI),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD 0x20(%RCX,%RAX,8),%XMM5,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM4,0x20(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD (%RSI),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD 0x28(%RCX,%RAX,8),%XMM9,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM8,0x28(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD (%RSI),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD 0x30(%RCX,%RAX,8),%XMM11,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM10,0x30(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD (%RSI),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD 0x38(%RCX,%RAX,8),%XMM13,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM12,0x38(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
ADD $0x8,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 5b7ad <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x29d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Function	_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0
Source file and lines	forall.hpp:59-59
Module	libkripke.so

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp:57

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 10.67 to 2.33 cycles (4.57x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 10.67 to 5.67 cycles (1.88x speedup).

Workaround

Read less array elements All SSE and/or AVX registers are used: in that case, try to relax register pressure by reducing the unroll factor or splitting your loop
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 8 FMA (fused multiply-add) operations.

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 192 bytes (24 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	35
nb uops	34
loop length	194
used x86 registers	5
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.67 cycles
front end	5.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	10.67	10.67	10.67	4.00	4.00	0.00	0.00	4.00	4.00
cycles	0.50	0.50	0.25	0.25	0.50	10.67	10.67	10.67	4.00	4.00	0.00	0.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.67
Dispatch	10.67
Data deps.	1.00
Overall L1	10.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.67 cycles. At this rate:

18% of peak load performance is reached (18.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (6.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 5b7ad

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
VMOVSD (%RSI),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD (%RBX,%RAX,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD 0x8(%RBX,%RAX,8),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD (%RCX,%RAX,8),%XMM15,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD 0x10(%RBX,%RAX,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD %XMM14,(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD 0x18(%RBX,%RAX,8),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD (%RSI),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD 0x20(%RBX,%RAX,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD 0x8(%RCX,%RAX,8),%XMM7,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD 0x28(%RBX,%RAX,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD %XMM0,0x8(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD 0x30(%RBX,%RAX,8),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD (%RSI),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD 0x38(%RBX,%RAX,8),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD 0x10(%RCX,%RAX,8),%XMM2,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM1,0x10(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD (%RSI),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD 0x18(%RCX,%RAX,8),%XMM6,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM3,0x18(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD (%RSI),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD 0x20(%RCX,%RAX,8),%XMM5,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM4,0x20(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD (%RSI),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD 0x28(%RCX,%RAX,8),%XMM9,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM8,0x28(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD (%RSI),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD 0x30(%RCX,%RAX,8),%XMM11,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM10,0x30(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD (%RSI),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD 0x38(%RCX,%RAX,8),%XMM13,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM12,0x38(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
ADD $0x8,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 5b7ad <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x29d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> --groups 1024 --procs 2,1,1MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/run/oneview_runs/compilers/gcc_13/oneview_run_1708510989OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.94	0.18	0.85	0.47	0.76	0.8	0.6	1.69	0.39	3.57	0.19	5.9	0.18	3.73

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	27.06	2.63
2x2	4	0.94	1.87	2	14.26	2.83
2x4	8	0.85	3.39	4	8.13	3.08
2x8	16	0.76	6.09	8	5.1	3.33
2x16	32	0.6	9.56	16	3.23	4.19
2x32	64	0.39	12.37	32	2.47	5.82
2x64	128	0.19	12.04	64	2.18	7.27
2x96	192	0.18	17.65	96	1.69	4.57

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency