OV - - Loop 1084 - libkripke.so

	Loop Id: 1084	Module: libkripke.so	Source: forall.hpp:59-59 [...]	Coverage: 91.17%

0x6cb80 MOV	(%R11,%RAX,8),%R10

0x6cb84 MOVSXD	(%R9,%RAX,4),%R8

0x6cb88 ADD	%R10,%R8

0x6cb8b CMP	%R8,%R10

0x6cb8e JGE	6ce10

0x6cb94 SAL	$0x3,%R8

0x6cb98 VXORPD	%XMM0,%XMM0,%XMM0

0x6cb9c SAL	$0x3,%R10

0x6cba0 MOV	%R8,%RDX

0x6cba3 SUB	%R10,%RDX

0x6cba6 SUB	$0x8,%RDX

0x6cbaa SHR	$0x3,%RDX

0x6cbae INC	%RDX

0x6cbb1 AND	$0x7,%EDX

0x6cbb4 JE	6ccb7

0x6cbba CMP	$0x1,%RDX

0x6cbbe JE	6cc92

0x6cbc4 CMP	$0x2,%RDX

0x6cbc8 JE	6cc76

0x6cbce CMP	$0x3,%RDX

0x6cbd2 JE	6cc5a

0x6cbd8 CMP	$0x4,%RDX

0x6cbdc JE	6cc3e

0x6cbde CMP	$0x5,%RDX

0x6cbe2 JE	6cc22

0x6cbe4 CMP	$0x6,%RDX

0x6cbe8 JE	6cc06

0x6cbea MOV	(%R13,%R10,1),%RDX

0x6cbef VMOVSD	(%R14,%R10,1),%XMM5

0x6cbf5 ADD	$0x8,%R10

0x6cbf9 IMUL	%RCX,%RDX

0x6cbfd ADD	%R12,%RDX

0x6cc00 VFMADD231SD	(%R15,%RDX,8),%XMM5,%XMM0

0x6cc06 MOV	(%R13,%R10,1),%RDX

0x6cc0b VMOVSD	(%R14,%R10,1),%XMM1

0x6cc11 ADD	$0x8,%R10

0x6cc15 IMUL	%RCX,%RDX

0x6cc19 ADD	%R12,%RDX

0x6cc1c VFMADD231SD	(%R15,%RDX,8),%XMM1,%XMM0

0x6cc22 MOV	(%R13,%R10,1),%RDX

0x6cc27 VMOVSD	(%R14,%R10,1),%XMM3

0x6cc2d ADD	$0x8,%R10

0x6cc31 IMUL	%RCX,%RDX

0x6cc35 ADD	%R12,%RDX

0x6cc38 VFMADD231SD	(%R15,%RDX,8),%XMM3,%XMM0

0x6cc3e MOV	(%R13,%R10,1),%RDX

0x6cc43 VMOVSD	(%R14,%R10,1),%XMM7

0x6cc49 ADD	$0x8,%R10

0x6cc4d IMUL	%RCX,%RDX

0x6cc51 ADD	%R12,%RDX

0x6cc54 VFMADD231SD	(%R15,%RDX,8),%XMM7,%XMM0

0x6cc5a MOV	(%R13,%R10,1),%RDX

0x6cc5f VMOVSD	(%R14,%R10,1),%XMM9

0x6cc65 ADD	$0x8,%R10

0x6cc69 IMUL	%RCX,%RDX

0x6cc6d ADD	%R12,%RDX

0x6cc70 VFMADD231SD	(%R15,%RDX,8),%XMM9,%XMM0

0x6cc76 MOV	(%R13,%R10,1),%RDX

0x6cc7b VMOVSD	(%R14,%R10,1),%XMM5

0x6cc81 ADD	$0x8,%R10

0x6cc85 IMUL	%RCX,%RDX

0x6cc89 ADD	%R12,%RDX

0x6cc8c VFMADD231SD	(%R15,%RDX,8),%XMM5,%XMM0

0x6cc92 MOV	(%R13,%R10,1),%RDX

0x6cc97 VMOVSD	(%R14,%R10,1),%XMM1

0x6cc9d ADD	$0x8,%R10

0x6cca1 IMUL	%RCX,%RDX

0x6cca5 ADD	%R12,%RDX

0x6cca8 VFMADD231SD	(%R15,%RDX,8),%XMM1,%XMM0

0x6ccae CMP	%R8,%R10

0x6ccb1 JE	6cd8b

  (1086) 0x6ccb7 MOV	(%R13,%R10,1),%RDX

  (1086) 0x6ccbc VMOVSD	(%R14,%R10,1),%XMM3

  (1086) 0x6ccc2 VMOVSD	0x8(%R14,%R10,1),%XMM7

  (1086) 0x6ccc9 VMOVSD	0x10(%R14,%R10,1),%XMM9

  (1086) 0x6ccd0 VMOVSD	0x18(%R14,%R10,1),%XMM5

  (1086) 0x6ccd7 VMOVSD	0x20(%R14,%R10,1),%XMM1

  (1086) 0x6ccde IMUL	%RCX,%RDX

  (1086) 0x6cce2 ADD	%R12,%RDX

  (1086) 0x6cce5 VFMADD231SD	(%R15,%RDX,8),%XMM3,%XMM0

  (1086) 0x6cceb MOV	0x8(%R13,%R10,1),%RDX

  (1086) 0x6ccf0 VMOVSD	0x28(%R14,%R10,1),%XMM3

  (1086) 0x6ccf7 IMUL	%RCX,%RDX

  (1086) 0x6ccfb ADD	%R12,%RDX

  (1086) 0x6ccfe VFMADD231SD	(%R15,%RDX,8),%XMM7,%XMM0

  (1086) 0x6cd04 MOV	0x10(%R13,%R10,1),%RDX

  (1086) 0x6cd09 VMOVSD	0x30(%R14,%R10,1),%XMM7

  (1086) 0x6cd10 IMUL	%RCX,%RDX

  (1086) 0x6cd14 ADD	%R12,%RDX

  (1086) 0x6cd17 VFMADD231SD	(%R15,%RDX,8),%XMM9,%XMM0

  (1086) 0x6cd1d MOV	0x18(%R13,%R10,1),%RDX

  (1086) 0x6cd22 VMOVSD	0x38(%R14,%R10,1),%XMM9

  (1086) 0x6cd29 IMUL	%RCX,%RDX

  (1086) 0x6cd2d ADD	%R12,%RDX

  (1086) 0x6cd30 VFMADD231SD	(%R15,%RDX,8),%XMM5,%XMM0

  (1086) 0x6cd36 MOV	0x20(%R13,%R10,1),%RDX

  (1086) 0x6cd3b IMUL	%RCX,%RDX

  (1086) 0x6cd3f ADD	%R12,%RDX

  (1086) 0x6cd42 VFMADD231SD	(%R15,%RDX,8),%XMM1,%XMM0

  (1086) 0x6cd48 MOV	0x28(%R13,%R10,1),%RDX

  (1086) 0x6cd4d IMUL	%RCX,%RDX

  (1086) 0x6cd51 ADD	%R12,%RDX

  (1086) 0x6cd54 VFMADD231SD	(%R15,%RDX,8),%XMM3,%XMM0

  (1086) 0x6cd5a MOV	0x30(%R13,%R10,1),%RDX

  (1086) 0x6cd5f IMUL	%RCX,%RDX

  (1086) 0x6cd63 ADD	%R12,%RDX

  (1086) 0x6cd66 VFMADD231SD	(%R15,%RDX,8),%XMM7,%XMM0

  (1086) 0x6cd6c MOV	0x38(%R13,%R10,1),%RDX

  (1086) 0x6cd71 ADD	$0x40,%R10

  (1086) 0x6cd75 IMUL	%RCX,%RDX

  (1086) 0x6cd79 ADD	%R12,%RDX

  (1086) 0x6cd7c VFMADD231SD	(%R15,%RDX,8),%XMM9,%XMM0

  (1086) 0x6cd82 CMP	%R8,%R10

  (1086) 0x6cd85 JNE	6ccb7

0x6cd8b VMOVSD	(%RSI,%RAX,8),%XMM5

0x6cd90 VFMADD132SD	(%RBX,%RAX,8),%XMM5,%XMM0

0x6cd96 VMOVSD	%XMM0,(%RSI,%RAX,8)

0x6cd9b INC	%RAX

0x6cd9e CMP	%RDI,%RAX

0x6cda1 JNE	6cb80

0x6ce10 VXORPD	%XMM0,%XMM0,%XMM0

0x6ce14 JMP	6cd8b

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/IndexValue.hpp: 105 - 105

--------------------------------------------------------------------------------

105:     return TYPE(value + a);

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp: 55 - 55

--------------------------------------------------------------------------------

55:     return a * b;

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/Scattering.cpp: 87 - 97

--------------------------------------------------------------------------------

87:             MixElem mix_start = zone_to_mixelem(z);

88:             MixElem mix_stop = mix_start + zone_to_num_mixelem(z);

89:

90:             double sigs_z = 0.0;

91:             for(MixElem mix = mix_start;mix < mix_stop;++ mix){

92:               Material mat = mixelem_to_material(mix);

93:               double fraction = mixelem_to_fraction(mix);

94:

95:               sigs_z += sigs(mat, n, global_g, global_gp) * fraction;

96:             }

97:             phi_out(nm, g, z) += sigs_z * phi(nm, gp, z);

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp: 110 - 110

--------------------------------------------------------------------------------

110:     return data[idx];

Path /

Metric	Value
CQA speedup if no scalar integer	2.19
CQA speedup if FP arith vectorized	1.98
CQA speedup if fully vectorized	6.20
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	micro-operation queue,
Function	_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0
Source	IndexValue.hpp:105-105,Layout.hpp:55-55,Scattering.cpp:87-91,Scattering.cpp:95-97,forall.hpp:59-59,View.hpp:110-110
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.17
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.67
CQA cycles if fully vectorized	2.13
Front-end cycles	13.17
DIV/SQRT cycles	11.50
P0 cycles	11.50
P1 cycles	11.25
P2 cycles	11.25
P3 cycles	5.50
P4 cycles	8.67
P5 cycles	8.67
P6 cycles	8.67
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	79.00
Nb uops	79.00
Nb loads	25.00
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.22
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.49
Bytes prefetched	0.00
Bytes loaded	196.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	6.67
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	18.18
Vector-efficiency ratio all	13.33
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.77

Metric	Value
CQA speedup if no scalar integer	2.19
CQA speedup if FP arith vectorized	1.98
CQA speedup if fully vectorized	6.20
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	micro-operation queue,
Function	_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0
Source	IndexValue.hpp:105-105,Layout.hpp:55-55,Scattering.cpp:87-91,Scattering.cpp:95-97,forall.hpp:59-59,View.hpp:110-110
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.17
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.67
CQA cycles if fully vectorized	2.13
Front-end cycles	13.17
DIV/SQRT cycles	11.50
P0 cycles	11.50
P1 cycles	11.25
P2 cycles	11.25
P3 cycles	5.50
P4 cycles	8.67
P5 cycles	8.67
P6 cycles	8.67
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	79.00
Nb uops	79.00
Nb loads	25.00
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.22
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.49
Bytes prefetched	0.00
Bytes loaded	196.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	6.67
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	18.18
Vector-efficiency ratio all	13.33
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.77

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0
Source file and lines	forall.hpp:59-59
Module	libkripke.so

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/IndexValue.hpp:105
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/Scattering.cpp:87-97
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp:110

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 16 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.17 to 6.00 cycles (2.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 13.17 to 2.12 cycles (6.20x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 8 FMA (fused multiply-add) operations.

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 196 bytes (24 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	79
nb uops	79
loop length	348
used x86 registers	14
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.17 cycles
front end	13.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	11.50	11.50	11.25	11.25	5.50	8.67	8.67	8.67	4.00	4.00	0.00	0.00	0.50	0.50
cycles	11.50	11.50	11.25	11.25	5.50	8.67	8.67	8.67	4.00	4.00	0.00	0.00	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.17
Dispatch	11.50
Overall L1	13.17

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	10%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.17 cycles. At this rate:

15% of peak load performance is reached (14.89 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.61 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 13.17 to 11.50 cycles (1.14x speedup).

ASM code

In the binary file, the address of the loop is: 6cb80

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
MOV (%R11,%RAX,8),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOVSXD (%R9,%RAX,4),%R8	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
ADD %R10,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JGE 6ce10 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0+0x5d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
SAL $0x3,%R8	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x3,%R10	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOV %R8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB %R10,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SUB $0x8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SHR $0x3,%RDX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
AND $0x7,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 6ccb7 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0+0x477>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x1,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 6cc92 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0+0x452>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x2,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 6cc76 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0+0x436>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x3,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 6cc5a <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0+0x41a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x4,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 6cc3e <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0+0x3fe>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x5,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 6cc22 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0+0x3e2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x6,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 6cc06 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0+0x3c6>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV (%R13,%R10,1),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD (%R14,%R10,1),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
ADD $0x8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
IMUL %RCX,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R12,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VFMADD231SD (%R15,%RDX,8),%XMM5,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
MOV (%R13,%R10,1),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD (%R14,%R10,1),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
ADD $0x8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
IMUL %RCX,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R12,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VFMADD231SD (%R15,%RDX,8),%XMM1,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
MOV (%R13,%R10,1),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD (%R14,%R10,1),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
ADD $0x8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
IMUL %RCX,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R12,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VFMADD231SD (%R15,%RDX,8),%XMM3,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
MOV (%R13,%R10,1),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD (%R14,%R10,1),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
ADD $0x8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
IMUL %RCX,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R12,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VFMADD231SD (%R15,%RDX,8),%XMM7,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
MOV (%R13,%R10,1),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD (%R14,%R10,1),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
ADD $0x8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
IMUL %RCX,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R12,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VFMADD231SD (%R15,%RDX,8),%XMM9,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
MOV (%R13,%R10,1),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD (%R14,%R10,1),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
ADD $0x8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
IMUL %RCX,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R12,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VFMADD231SD (%R15,%RDX,8),%XMM5,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
MOV (%R13,%R10,1),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD (%R14,%R10,1),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
ADD $0x8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
IMUL %RCX,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R12,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VFMADD231SD (%R15,%RDX,8),%XMM1,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
CMP %R8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 6cd8b <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0+0x54b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
VMOVSD (%RSI,%RAX,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD (%RBX,%RAX,8),%XMM5,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM0,(%RSI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 6cb80 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0+0x340>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 6cd8b <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0+0x54b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1

Function	_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0
Source file and lines	forall.hpp:59-59
Module	libkripke.so

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/IndexValue.hpp:105
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/Scattering.cpp:87-97
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp:110

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.17 to 6.00 cycles (2.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 8 FMA (fused multiply-add) operations.

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 196 bytes (24 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	79
nb uops	79
loop length	348
used x86 registers	14
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.17 cycles
front end	13.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	11.50	11.50	11.25	11.25	5.50	8.67	8.67	8.67	4.00	4.00	0.00	0.00	0.50	0.50
cycles	11.50	11.50	11.25	11.25	5.50	8.67	8.67	8.67	4.00	4.00	0.00	0.00	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.17
Dispatch	11.50
Overall L1	13.17

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	10%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.17 cycles. At this rate:

15% of peak load performance is reached (14.89 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.61 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 6cb80

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
MOV (%R11,%RAX,8),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOVSXD (%R9,%RAX,4),%R8	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
ADD %R10,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JGE 6ce10 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0+0x5d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
SAL $0x3,%R8	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x3,%R10	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOV %R8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB %R10,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SUB $0x8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SHR $0x3,%RDX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
AND $0x7,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 6ccb7 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0+0x477>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x1,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 6cc92 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0+0x452>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x2,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 6cc76 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0+0x436>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x3,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 6cc5a <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0+0x41a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x4,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 6cc3e <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0+0x3fe>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x5,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 6cc22 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0+0x3e2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x6,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 6cc06 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0+0x3c6>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV (%R13,%R10,1),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD (%R14,%R10,1),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
ADD $0x8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
IMUL %RCX,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R12,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VFMADD231SD (%R15,%RDX,8),%XMM5,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
MOV (%R13,%R10,1),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD (%R14,%R10,1),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
ADD $0x8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
IMUL %RCX,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R12,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VFMADD231SD (%R15,%RDX,8),%XMM1,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
MOV (%R13,%R10,1),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD (%R14,%R10,1),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
ADD $0x8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
IMUL %RCX,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R12,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VFMADD231SD (%R15,%RDX,8),%XMM3,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
MOV (%R13,%R10,1),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD (%R14,%R10,1),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
ADD $0x8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
IMUL %RCX,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R12,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VFMADD231SD (%R15,%RDX,8),%XMM7,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
MOV (%R13,%R10,1),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD (%R14,%R10,1),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
ADD $0x8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
IMUL %RCX,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R12,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VFMADD231SD (%R15,%RDX,8),%XMM9,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
MOV (%R13,%R10,1),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD (%R14,%R10,1),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
ADD $0x8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
IMUL %RCX,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R12,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VFMADD231SD (%R15,%RDX,8),%XMM5,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
MOV (%R13,%R10,1),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD (%R14,%R10,1),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
ADD $0x8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
IMUL %RCX,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R12,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VFMADD231SD (%R15,%RDX,8),%XMM1,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
CMP %R8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 6cd8b <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0+0x54b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
VMOVSD (%RSI,%RAX,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD (%RBX,%RAX,8),%XMM5,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM0,(%RSI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 6cb80 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0+0x340>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 6cd8b <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_5GroupElPSW_EESW_EESZ_NSO_INSQ_INSR_4ZoneElPS10_EES10_EEEEENSM_IJEEEJZNK14ScatteringSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdES1D_RKNSR_4Core3SetES1H_S1H_RNS1E_5FieldIdJSS_SW_S10_EEES1K_RNS1I_IdJNSR_8MaterialENSR_8LegendreENSR_11GlobalGroupES1N_EEERNS1I_INSR_7MixElemEJS10_EEERNS1I_IiJS10_EEERNS1I_IS1L_JS1Q_EEERNS1I_IdJS1Q_EEERNS1I_IS1M_JSS_EEEEUlSS_SW_SW_S10_E_EEEEEvOS1C_._omp_fn.0+0x54b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> --groups 1024 --procs 2,1,1MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/run/oneview_runs/compilers/gcc_13/oneview_run_1708510989OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1.01	0	1	0.01	0.98	1.74	1	0.06	0.96	2.84	0.63	27.93	0.39	46.11

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	917.57	91.17
2x2	4	1.01	2.02	2	453.73	90.78
2x4	8	1	4	4	227.69	90.57
2x8	16	0.98	7.84	8	115.28	89.52
2x16	32	1	15.99	16	57.22	86.98
2x32	64	0.96	30.88	32	28.85	80.8
2x64	128	0.63	40.25	64	23.17	75.28
2x96	192	0.39	37.14	96	25.19	75.21

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency