OV - - Function _ZN6Kripke12ParallelComm12testRecievesEv

	Function: _ZN6Kripke12ParallelComm12testRecievesEv	Module: libkripke.so	Source: ParallelComm.cpp:214-251 [...]	Coverage: 0.03%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp: 214 - 251

--------------------------------------------------------------------------------

214: void ParallelComm::testRecieves(void){

215: #ifdef KRIPKE_USE_MPI

216:   // Check for any recv requests that have completed

217:   int num_requests = recv_requests.size();

218:   bool done = false;

219:   while(!done && num_requests > 0){

[...]

226:     MPI_Testany(num_requests, &recv_requests[0], &index, &complete_flag, &recv_status[0]);

227:

228:     if(complete_flag != 0){

229:

230:       // get subdomain that this completed for

231:       int sdom_id = recv_subdomains[index];

232:

233:       // remove the request from the list

234:       recv_requests.erase(recv_requests.begin()+index);

235:       recv_subdomains.erase(recv_subdomains.begin()+index);

236:       num_requests --;

237:

238:       // decrement the dependency count for that subdomain

239:       for(size_t i = 0;i < queue_sdom_ids.size();++ i){

240:         if(queue_sdom_ids[i] == sdom_id){

241:           queue_depends[i] --;

242:           break;

[...]

249:   }

250: #endif

251: }

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_construct.h: 119 - 119

--------------------------------------------------------------------------------

119:       ::new((void*)__p) _Tp(std::forward<_Args>(__args)...);

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/vector.tcc: 184 - 186

--------------------------------------------------------------------------------

184:       if (__position + 1 != end())

185: 	_GLIBCXX_MOVE3(__position + 1, end(), __position);

186:       --this->_M_impl._M_finish;

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h: 395 - 1714

--------------------------------------------------------------------------------

395: 	this->_M_impl._M_start = this->_M_allocate(__n);

396: 	this->_M_impl._M_finish = this->_M_impl._M_start;

397: 	this->_M_impl._M_end_of_storage = this->_M_impl._M_start + __n;

[...]

990:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1126: 	return *(this->_M_impl._M_start + __n);

[...]

1714: 	this->_M_impl._M_finish =

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_uninitialized.h: 667 - 667

--------------------------------------------------------------------------------

667: 	      ++__first;

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_algobase.h: 423 - 1123

--------------------------------------------------------------------------------

423: 	{ *__to = std::move(*__from); }

[...]

435: 	  const ptrdiff_t _Num = __last - __first;

436: 	  if (__builtin_expect(_Num > 1, true))

437: 	    __builtin_memmove(__result, __first, sizeof(_Tp) * _Num);

438: 	  else if (_Num == 1)

[...]

918:       for (; __first != __last; ++__first)

919: 	*__first = __value;

[...]

1123:       if (__n <= 0)

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_iterator.h: 1077 - 1148

--------------------------------------------------------------------------------

1077:       : _M_current(__i) { }

[...]

1148:       { return __normal_iterator(_M_current + __n); }

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/new_allocator.h: 122 - 168

--------------------------------------------------------------------------------

122:       allocate(size_type __n, const void* = static_cast<const void*>(0))

[...]

147: 	return static_cast<_Tp*>(_GLIBCXX_OPERATOR_NEW(__n * sizeof(_Tp)));

[...]

168: 	_GLIBCXX_OPERATOR_DELETE(_GLIBCXX_SIZED_DEALLOC(__p, __n));

0x7c420 PUSH	%RBP

0x7c421 MOV	%RSP,%RBP

0x7c424 PUSH	%R15

0x7c426 PUSH	%R14

0x7c428 PUSH	%R13

0x7c42a PUSH	%R12

0x7c42c PUSH	%RBX

0x7c42d LEA	-0x58(%RBP),%RCX

0x7c431 LEA	-0x54(%RBP),%RDX

0x7c435 SUB	$0x58,%RSP

0x7c439 MOV	0x30(%RDI),%RAX

0x7c43d MOV	%RCX,-0x68(%RBP)

0x7c441 MOV	%RDX,-0x70(%RBP)

0x7c445 SUB	0x28(%RDI),%RAX

0x7c449 SAR	$0x2,%RAX

0x7c44d TEST	%EAX,%EAX

0x7c44f JLE	7c68f

0x7c455 MOV	%RDI,%R14

0x7c458 MOV	%EAX,%R15D

0x7c45b MOVSXD	%EAX,%R13

0x7c45e XCHG	%AX,%AX

(1187) 0x7c460 LEA	(%R13,%R13,4),%R12

(1187) 0x7c465 SAL	$0x2,%R12

(1187) 0x7c469 MOV	%R12,%RDI

(1187) 0x7c46c CALL	9390 <_Znwm@plt>

(1187) 0x7c471 VPXOR	%XMM0,%XMM0,%XMM0

(1187) 0x7c475 LEA	(%RAX,%R12,1),%RSI

(1187) 0x7c479 MOV	%RAX,%RBX

(1187) 0x7c47c VMOVDQU	%XMM0,(%RAX)

(1187) 0x7c480 LEA	0x14(%RAX),%RCX

(1187) 0x7c484 MOV	%RAX,-0x50(%RBP)

(1187) 0x7c488 MOV	%RSI,-0x40(%RBP)

(1187) 0x7c48c MOVL	$0,0x10(%RAX)

(1187) 0x7c493 CMP	$0x1,%R13

(1187) 0x7c497 JE	7c662

(1187) 0x7c49d CMP	%RCX,%RSI

(1187) 0x7c4a0 JE	7c662

(1187) 0x7c4a6 MOV	%RSI,%R8

(1187) 0x7c4a9 MOV	$0xccccccccccccccd,%RDI

(1187) 0x7c4b3 MOV	%RCX,%R10

(1187) 0x7c4b6 SUB	%RCX,%R8

(1187) 0x7c4b9 SUB	$0x14,%R8

(1187) 0x7c4bd SHR	$0x2,%R8

(1187) 0x7c4c1 IMUL	%RDI,%R8

(1187) 0x7c4c5 INC	%R8

(1187) 0x7c4c8 AND	$0x7,%R8D

(1187) 0x7c4cc JE	7c588

(1187) 0x7c4d2 CMP	$0x1,%R8

(1187) 0x7c4d6 JE	7c569

(1187) 0x7c4dc CMP	$0x2,%R8

(1187) 0x7c4e0 JE	7c554

(1187) 0x7c4e2 CMP	$0x3,%R8

(1187) 0x7c4e6 JE	7c53e

(1187) 0x7c4e8 CMP	$0x4,%R8

(1187) 0x7c4ec JE	7c529

(1187) 0x7c4ee CMP	$0x5,%R8

(1187) 0x7c4f2 JE	7c514

(1187) 0x7c4f4 CMP	$0x6,%R8

(1187) 0x7c4f8 JNE	7c890

(1187) 0x7c4fe VMOVDQU	(%RBX),%XMM1

(1187) 0x7c502 ADD	$0x14,%R10

(1187) 0x7c506 VMOVDQU	%XMM1,-0x14(%R10)

(1187) 0x7c50c MOV	0x10(%RBX),%R11D

(1187) 0x7c510 MOV	%R11D,-0x4(%R10)

(1187) 0x7c514 VMOVDQU	(%RBX),%XMM2

(1187) 0x7c518 ADD	$0x14,%R10

(1187) 0x7c51c VMOVDQU	%XMM2,-0x14(%R10)

(1187) 0x7c522 MOV	0x10(%RBX),%EAX

(1187) 0x7c525 MOV	%EAX,-0x4(%R10)

(1187) 0x7c529 VMOVDQU	(%RBX),%XMM4

(1187) 0x7c52d ADD	$0x14,%R10

(1187) 0x7c531 VMOVDQU	%XMM4,-0x14(%R10)

(1187) 0x7c537 MOV	0x10(%RBX),%EDX

(1187) 0x7c53a MOV	%EDX,-0x4(%R10)

(1187) 0x7c53e VMOVDQU	(%RBX),%XMM3

(1187) 0x7c542 ADD	$0x14,%R10

(1187) 0x7c546 VMOVDQU	%XMM3,-0x14(%R10)

(1187) 0x7c54c MOV	0x10(%RBX),%R8D

(1187) 0x7c550 MOV	%R8D,-0x4(%R10)

(1187) 0x7c554 VMOVDQU	(%RBX),%XMM6

(1187) 0x7c558 ADD	$0x14,%R10

(1187) 0x7c55c VMOVDQU	%XMM6,-0x14(%R10)

(1187) 0x7c562 MOV	0x10(%RBX),%EDI

(1187) 0x7c565 MOV	%EDI,-0x4(%R10)

(1187) 0x7c569 VMOVDQU	(%RBX),%XMM7

(1187) 0x7c56d ADD	$0x14,%R10

(1187) 0x7c571 VMOVDQU	%XMM7,-0x14(%R10)

(1187) 0x7c577 MOV	0x10(%RBX),%R9D

(1187) 0x7c57b MOV	%R9D,-0x4(%R10)

(1187) 0x7c57f CMP	%R10,%RSI

(1187) 0x7c582 JE	7c62d

  (1189) 0x7c588 VMOVDQU	(%RBX),%XMM8

  (1189) 0x7c58c ADD	$0xa0,%R10

  (1189) 0x7c593 VMOVDQU	%XMM8,-0xa0(%R10)

  (1189) 0x7c59c MOV	0x10(%RBX),%R11D

  (1189) 0x7c5a0 MOV	%R11D,-0x90(%R10)

  (1189) 0x7c5a7 VMOVDQU	(%RBX),%XMM9

  (1189) 0x7c5ab VMOVDQU	%XMM9,-0x8c(%R10)

  (1189) 0x7c5b4 MOV	0x10(%RBX),%EAX

  (1189) 0x7c5b7 MOV	%EAX,-0x7c(%R10)

  (1189) 0x7c5bb VMOVDQU	(%RBX),%XMM10

  (1189) 0x7c5bf VMOVDQU	%XMM10,-0x78(%R10)

  (1189) 0x7c5c5 MOV	0x10(%RBX),%EDX

  (1189) 0x7c5c8 MOV	%EDX,-0x68(%R10)

  (1189) 0x7c5cc VMOVDQU	(%RBX),%XMM11

  (1189) 0x7c5d0 VMOVDQU	%XMM11,-0x64(%R10)

  (1189) 0x7c5d6 MOV	0x10(%RBX),%R8D

  (1189) 0x7c5da MOV	%R8D,-0x54(%R10)

  (1189) 0x7c5de VMOVDQU	(%RBX),%XMM12

  (1189) 0x7c5e2 VMOVDQU	%XMM12,-0x50(%R10)

  (1189) 0x7c5e8 MOV	0x10(%RBX),%EDI

  (1189) 0x7c5eb MOV	%EDI,-0x40(%R10)

  (1189) 0x7c5ef VMOVDQU	(%RBX),%XMM13

  (1189) 0x7c5f3 VMOVDQU	%XMM13,-0x3c(%R10)

  (1189) 0x7c5f9 MOV	0x10(%RBX),%R9D

  (1189) 0x7c5fd MOV	%R9D,-0x2c(%R10)

  (1189) 0x7c601 VMOVDQU	(%RBX),%XMM14

  (1189) 0x7c605 VMOVDQU	%XMM14,-0x28(%R10)

  (1189) 0x7c60b MOV	0x10(%RBX),%R11D

  (1189) 0x7c60f MOV	%R11D,-0x18(%R10)

  (1189) 0x7c613 VMOVDQU	(%RBX),%XMM15

  (1189) 0x7c617 VMOVDQU	%XMM15,-0x14(%R10)

  (1189) 0x7c61d MOV	0x10(%RBX),%EAX

  (1189) 0x7c620 MOV	%EAX,-0x4(%R10)

  (1189) 0x7c624 CMP	%R10,%RSI

  (1189) 0x7c627 JNE	7c588

(1187) 0x7c62d MOV	$-0x28,%R10

(1187) 0x7c634 MOV	$0x3fffffffffffffff,%RDX

(1187) 0x7c63e SUB	%RBX,%R10

(1187) 0x7c641 ADD	%RSI,%R10

(1187) 0x7c644 MOV	$0xccccccccccccccd,%RSI

(1187) 0x7c64e SHR	$0x2,%R10

(1187) 0x7c652 IMUL	%RSI,%R10

(1187) 0x7c656 AND	%RDX,%R10

(1187) 0x7c659 LEA	0x5(%R10,%R10,4),%R8

(1187) 0x7c65e LEA	(%RCX,%R8,4),%RCX

(1187) 0x7c662 MOV	%RCX,-0x48(%RBP)

(1187) 0x7c666 MOV	0x28(%R14),%RSI

(1187) 0x7c66a MOV	-0x68(%RBP),%RCX

(1187) 0x7c66e MOV	-0x70(%RBP),%RDX

(1187) 0x7c672 MOV	%RBX,%R8

(1187) 0x7c675 MOV	%R15D,%EDI

(1187) 0x7c678 CALL	9580 <MPI_Testany@plt>

(1187) 0x7c67d MOV	-0x58(%RBP),%EDI

(1187) 0x7c680 TEST	%EDI,%EDI

(1187) 0x7c682 JNE	7c6a0

0x7c684 MOV	%R12,%RSI

0x7c687 MOV	%RBX,%RDI

0x7c68a CALL	93a0 <_ZdlPvm@plt>

0x7c68f ADD	$0x58,%RSP

0x7c693 POP	%RBX

0x7c694 POP	%R12

0x7c696 POP	%R13

0x7c698 POP	%R14

0x7c69a POP	%R15

0x7c69c POP	%RBP

0x7c69d RET

0x7c69e XCHG	%AX,%AX

(1187) 0x7c6a0 MOVSXD	-0x54(%RBP),%RDI

(1187) 0x7c6a4 MOV	0x40(%R14),%RSI

(1187) 0x7c6a8 MOV	0x30(%R14),%RAX

(1187) 0x7c6ac MOV	%RDI,%RDX

(1187) 0x7c6af SAL	$0x2,%RDI

(1187) 0x7c6b3 MOV	(%RSI,%RDI,1),%ECX

(1187) 0x7c6b6 ADD	0x28(%R14),%RDI

(1187) 0x7c6ba LEA	0x4(%RDI),%R11

(1187) 0x7c6be CMP	%R11,%RAX

(1187) 0x7c6c1 JE	7c6f0

(1187) 0x7c6c3 MOV	%RAX,%R9

(1187) 0x7c6c6 SUB	%R11,%R9

(1187) 0x7c6c9 CMP	$0x4,%R9

(1187) 0x7c6cd JLE	7c8cc

(1187) 0x7c6d3 MOV	%R9,%RDX

(1187) 0x7c6d6 MOV	%R11,%RSI

(1187) 0x7c6d9 MOV	%ECX,-0x74(%RBP)

(1187) 0x7c6dc CALL	9680 <memmove@plt>

(1187) 0x7c6e1 MOV	0x40(%R14),%RSI

(1187) 0x7c6e5 MOV	0x30(%R14),%RAX

(1187) 0x7c6e9 MOVSXD	-0x54(%RBP),%RDX

(1187) 0x7c6ed MOV	-0x74(%RBP),%ECX

(1187) 0x7c6f0 MOV	0x48(%R14),%R11

(1187) 0x7c6f4 LEA	(%RSI,%RDX,4),%RDI

(1187) 0x7c6f8 SUB	$0x4,%RAX

(1187) 0x7c6fc LEA	0x4(%RDI),%RSI

(1187) 0x7c700 MOV	%RAX,0x30(%R14)

(1187) 0x7c704 CMP	%RSI,%R11

(1187) 0x7c707 JE	7c728

(1187) 0x7c709 MOV	%R11,%RDX

(1187) 0x7c70c SUB	%RSI,%RDX

(1187) 0x7c70f CMP	$0x4,%RDX

(1187) 0x7c713 JLE	7c8ba

(1187) 0x7c719 MOV	%ECX,-0x74(%RBP)

(1187) 0x7c71c CALL	9680 <memmove@plt>

(1187) 0x7c721 MOV	0x48(%R14),%R11

(1187) 0x7c725 MOV	-0x74(%RBP),%ECX

(1187) 0x7c728 MOV	0x60(%R14),%R9

(1187) 0x7c72c MOV	0x58(%R14),%R10

(1187) 0x7c730 SUB	$0x4,%R11

(1187) 0x7c734 DEC	%R15D

(1187) 0x7c737 MOV	%R11,0x48(%R14)

(1187) 0x7c73b MOV	%R9,%RDI

(1187) 0x7c73e SUB	%R10,%RDI

(1187) 0x7c741 SAR	$0x2,%RDI

(1187) 0x7c745 CMP	%R9,%R10

(1187) 0x7c748 JE	7c870

(1187) 0x7c74e LEA	-0x1(%RDI),%RDX

(1187) 0x7c752 XOR	%EAX,%EAX

(1187) 0x7c754 AND	$0x7,%EDX

(1187) 0x7c757 CMP	%ECX,(%R10)

(1187) 0x7c75a JE	7c8b0

(1187) 0x7c760 MOV	$0x1,%EAX

(1187) 0x7c765 CMP	%RDI,%RAX

(1187) 0x7c768 JAE	7c870

(1187) 0x7c76e TEST	%RDX,%RDX

(1187) 0x7c771 JE	7c7fb

(1187) 0x7c777 CMP	$0x1,%RDX

(1187) 0x7c77b JE	7c7e9

(1187) 0x7c77d CMP	$0x2,%RDX

(1187) 0x7c781 JE	7c7dc

(1187) 0x7c783 CMP	$0x3,%RDX

(1187) 0x7c787 JE	7c7cf

(1187) 0x7c789 CMP	$0x4,%RDX

(1187) 0x7c78d JE	7c7c2

(1187) 0x7c78f CMP	$0x5,%RDX

(1187) 0x7c793 JE	7c7b5

(1187) 0x7c795 CMP	$0x6,%RDX

(1187) 0x7c799 JE	7c7a8

(1187) 0x7c79b CMP	%ECX,0x4(%R10)

(1187) 0x7c79f JE	7c8b0

(1187) 0x7c7a5 INC	%RAX

(1187) 0x7c7a8 CMP	%ECX,(%R10,%RAX,4)

(1187) 0x7c7ac JE	7c8b0

(1187) 0x7c7b2 INC	%RAX

(1187) 0x7c7b5 CMP	%ECX,(%R10,%RAX,4)

(1187) 0x7c7b9 JE	7c8b0

(1187) 0x7c7bf INC	%RAX

(1187) 0x7c7c2 CMP	%ECX,(%R10,%RAX,4)

(1187) 0x7c7c6 JE	7c8b0

(1187) 0x7c7cc INC	%RAX

(1187) 0x7c7cf CMP	%ECX,(%R10,%RAX,4)

(1187) 0x7c7d3 JE	7c8b0

(1187) 0x7c7d9 INC	%RAX

(1187) 0x7c7dc CMP	%ECX,(%R10,%RAX,4)

(1187) 0x7c7e0 JE	7c8b0

(1187) 0x7c7e6 INC	%RAX

(1187) 0x7c7e9 CMP	%ECX,(%R10,%RAX,4)

(1187) 0x7c7ed JE	7c8b0

(1187) 0x7c7f3 INC	%RAX

(1187) 0x7c7f6 CMP	%RDI,%RAX

(1187) 0x7c7f9 JAE	7c870

  (1188) 0x7c7fb CMP	%ECX,(%R10,%RAX,4)

  (1188) 0x7c7ff JE	7c8b0

  (1188) 0x7c805 LEA	0x1(%RAX),%RSI

  (1188) 0x7c809 MOV	%RSI,%RAX

  (1188) 0x7c80c CMP	%ECX,(%R10,%RSI,4)

  (1188) 0x7c810 JE	7c8b0

  (1188) 0x7c816 INC	%RAX

  (1188) 0x7c819 CMP	%ECX,(%R10,%RAX,4)

  (1188) 0x7c81d JE	7c8b0

  (1188) 0x7c823 LEA	0x2(%RSI),%RAX

  (1188) 0x7c827 CMP	%ECX,0x8(%R10,%RSI,4)

  (1188) 0x7c82c JE	7c8b0

  (1188) 0x7c832 LEA	0x3(%RSI),%RAX

  (1188) 0x7c836 CMP	%ECX,0xc(%R10,%RSI,4)

  (1188) 0x7c83b JE	7c8b0

  (1188) 0x7c83d LEA	0x4(%RSI),%RAX

  (1188) 0x7c841 CMP	%ECX,0x10(%R10,%RSI,4)

  (1188) 0x7c846 JE	7c8b0

  (1188) 0x7c848 LEA	0x5(%RSI),%RAX

  (1188) 0x7c84c CMP	%ECX,0x14(%R10,%RSI,4)

  (1188) 0x7c851 JE	7c8b0

  (1188) 0x7c853 LEA	0x6(%RSI),%RAX

  (1188) 0x7c857 CMP	%ECX,0x18(%R10,%RSI,4)

  (1188) 0x7c85c JE	7c8b0

  (1188) 0x7c85e LEA	0x7(%RSI),%RAX

  (1188) 0x7c862 CMP	%RDI,%RAX

  (1188) 0x7c865 JB	7c7fb

(1187) 0x7c867 NOPW	(%RAX,%RAX,1)

(1187) 0x7c870 MOV	%R12,%RSI

(1187) 0x7c873 MOV	%RBX,%RDI

(1187) 0x7c876 DEC	%R13

(1187) 0x7c879 CALL	93a0 <_ZdlPvm@plt>

(1187) 0x7c87e TEST	%R15D,%R15D

(1187) 0x7c881 JNE	7c460

0x7c887 JMP	7c68f

0x7c88c NOPL	(%RAX)

(1187) 0x7c890 VMOVDQU	(%RAX),%XMM5

(1187) 0x7c894 MOV	0x10(%RAX),%R9D

(1187) 0x7c898 LEA	0x28(%RAX),%R10

(1187) 0x7c89c VMOVDQU	%XMM5,0x14(%RAX)

(1187) 0x7c8a1 MOV	%R9D,0x10(%RCX)

(1187) 0x7c8a5 JMP	7c4fe

0x7c8aa NOPW	(%RAX,%RAX,1)

(1187) 0x7c8b0 MOV	0x70(%R14),%R8

(1187) 0x7c8b4 DECL	(%R8,%RAX,4)

(1187) 0x7c8b8 JMP	7c870

(1187) 0x7c8ba JNE	7c728

(1187) 0x7c8c0 MOV	0x4(%RDI),%R8D

(1187) 0x7c8c4 MOV	%R8D,(%RDI)

(1187) 0x7c8c7 JMP	7c728

(1187) 0x7c8cc JNE	7c6f0

(1187) 0x7c8d2 MOV	0x4(%RDI),%R10D

(1187) 0x7c8d6 MOV	%R10D,(%RDI)

(1187) 0x7c8d9 MOVSXD	-0x54(%RBP),%RDX

(1187) 0x7c8dd JMP	7c6f0

0x7c8e2 MOV	%RAX,%RBX

0x7c8e5 JMP	dc1c

0x7c8ea NOPW	(%RAX,%RAX,1)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	ParallelComm.cpp:214-251
Module	libkripke.so

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp:214-219,226-242,249-251
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_construct.h:119
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/vector.tcc:184-186
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h:395-397,990,1126,1714
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_uninitialized.h:667
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_algobase.h:423,435-438,918-919,1123
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_iterator.h:1077,1148
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/new_allocator.h:122,147,168

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 5.83 to 0.38 cycles (15.22x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

_ZdlPvm@plt: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 16 bytes.

General properties

nb instructions	39
nb uops	35
loop length	121
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.83 cycles
front end	5.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.75	2.75	2.50	2.50	2.50	1.67	1.67	1.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.75	2.75	2.50	2.50	2.50	1.67	1.67	1.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.83
Dispatch	2.75
Overall L1	5.83

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.83 cycles. At this rate:

2% of peak load performance is reached (2.74 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.74 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.83 to 2.75 cycles (2.12x speedup).

ASM code

In the binary file, the address of the function is: 7c420

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50
LEA -0x58(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x54(%RBP),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
SUB $0x58,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV 0x30(%RDI),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %RCX,-0x68(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %RDX,-0x70(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
SUB 0x28(%RDI),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
SAR $0x2,%RAX	1	0	0.50	0.50	0	0	0	0	0	1	0.50
TEST %EAX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 7c68f <_ZN6Kripke12ParallelComm12testRecievesEv+0x26f>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0.17
MOV %EAX,%R15D	1	0	0	0	0	0	0	0	0	0	0.17
MOVSXD %EAX,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0.09
MOV %R12,%RSI	1	0	0	0	0	0	0	0	0	0	0.17
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17
CALL 93a0 <_ZdlPvm@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
ADD $0x58,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0.09
JMP 7c68f <_ZN6Kripke12ParallelComm12testRecievesEv+0x26f>	1	0.50	0	0	0	0.50	0	0	0	0	1
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0.17
JMP dc1c <_ZN6Kripke12ParallelComm12testRecievesEv.cold>	1	0.50	0	0	0	0.50	0	0	0	0	1
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	ParallelComm.cpp:214-251
Module	libkripke.so

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp:214-219,226-242,249-251
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_construct.h:119
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/vector.tcc:184-186
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h:395-397,990,1126,1714
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_uninitialized.h:667
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_algobase.h:423,435-438,918-919,1123
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_iterator.h:1077,1148
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/new_allocator.h:122,147,168

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

_ZdlPvm@plt: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 16 bytes.

General properties

nb instructions	39
nb uops	35
loop length	121
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.83 cycles
front end	5.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.75	2.75	2.50	2.50	2.50	1.67	1.67	1.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.75	2.75	2.50	2.50	2.50	1.67	1.67	1.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.83
Dispatch	2.75
Overall L1	5.83

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.83 cycles. At this rate:

2% of peak load performance is reached (2.74 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.74 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 7c420

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50
LEA -0x58(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x54(%RBP),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
SUB $0x58,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV 0x30(%RDI),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %RCX,-0x68(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %RDX,-0x70(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
SUB 0x28(%RDI),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
SAR $0x2,%RAX	1	0	0.50	0.50	0	0	0	0	0	1	0.50
TEST %EAX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 7c68f <_ZN6Kripke12ParallelComm12testRecievesEv+0x26f>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0.17
MOV %EAX,%R15D	1	0	0	0	0	0	0	0	0	0	0.17
MOVSXD %EAX,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0.09
MOV %R12,%RSI	1	0	0	0	0	0	0	0	0	0	0.17
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17
CALL 93a0 <_ZdlPvm@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
ADD $0x58,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0.09
JMP 7c68f <_ZN6Kripke12ParallelComm12testRecievesEv+0x26f>	1	0.50	0	0	0	0.50	0	0	0	0	1
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0.17
JMP dc1c <_ZN6Kripke12ParallelComm12testRecievesEv.cold>	1	0.50	0	0	0	0.50	0	0	0	0	1
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> --groups 1024 --procs 2,1,1MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/run/oneview_runs/compilers/gcc_13/oneview_run_1708510989OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.41	0.05	1.7	0	2.13	0	1	0	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.53	0.03
2x2	1	0.41	0.83	2	1.6	0.08
2x4	1	1.7	6.8	4	0.42	0.02
2x8	1	2.13	17	8	0.28	0.01
2x16	1	1	1	16	0.1	0.01
2x32	1	1	1	32	0.08	0
2x64	1	1	1	64	0.16	0
2x96	1	1	1	96	0.24	0

Name	Coverage (%)	Time (s)
▼_ZN6Kripke12ParallelComm12testRecievesEv–	0.03	0.34
▼Loop 1187 - stl_algobase.h:423-1123 - libkripke.so–	0.03	0.28
○Loop 1188 - ParallelComm.cpp:239-240 - libkripke.so	0	0
○Loop 1189 - stl_algobase.h:918-919 - libkripke.so	0	0

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency