OV - - Loop 1121 - libkripke.so

	Loop Id: 1121	Module: libkripke.so	Source: forall.hpp:59-59 [...]	Coverage: 0.08%

0x71683 MOV	%R15,%R9

0x71686 MOV	%RBX,%R8

0x71689 MOV	%R12,%RCX

0x7168c VMOVQ	%XMM18,%RDX

0x71692 VMOVQ	%XMM20,%RSI

0x71698 VMOVQ	%XMM17,%RDI

0x7169e ADD	%R14,%R15

0x716a1 MOV	%R13,0x5e8(%RSP)    [1]

0x716a9 CALL	706c0 <_ZZNK9SweepSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_RNS1_4Core9DataStoreENS1_6SdomIdEENKUlNS1_9DirectionENS1_5GroupENS1_5ZoneKENS1_5ZoneJENS1_5ZoneIEE_clESB_SC_SD_SE_SF_>

0x716ae LEA	0x1(%R13),%RDI

0x716b2 MOV	%R15,%R9

0x716b5 MOV	%RBX,%R8

0x716b8 MOV	%R12,%RCX

0x716bb VMOVQ	%XMM18,%RDX

0x716c1 VMOVQ	%XMM20,%RSI

0x716c7 MOV	%RDI,0x5e8(%RSP)    [1]

0x716cf VMOVQ	%XMM17,%RDI

0x716d5 ADD	%R14,%R15

0x716d8 CALL	706c0 <_ZZNK9SweepSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_RNS1_4Core9DataStoreENS1_6SdomIdEENKUlNS1_9DirectionENS1_5GroupENS1_5ZoneKENS1_5ZoneJENS1_5ZoneIEE_clESB_SC_SD_SE_SF_>

0x716dd LEA	0x2(%R13),%RSI

0x716e1 MOV	%R15,%R9

0x716e4 MOV	%RBX,%R8

0x716e7 MOV	%R12,%RCX

0x716ea VMOVQ	%XMM18,%RDX

0x716f0 VMOVQ	%XMM17,%RDI

0x716f6 MOV	%RSI,0x5e8(%RSP)    [1]

0x716fe VMOVQ	%XMM20,%RSI

0x71704 ADD	%R14,%R15

0x71707 CALL	706c0 <_ZZNK9SweepSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_RNS1_4Core9DataStoreENS1_6SdomIdEENKUlNS1_9DirectionENS1_5GroupENS1_5ZoneKENS1_5ZoneJENS1_5ZoneIEE_clESB_SC_SD_SE_SF_>

0x7170c LEA	0x3(%R13),%R9

0x71710 MOV	%RBX,%R8

0x71713 MOV	%R12,%RCX

0x71716 MOV	%R9,0x5e8(%RSP)    [1]

0x7171e VMOVQ	%XMM18,%RDX

0x71724 MOV	%R15,%R9

0x71727 VMOVQ	%XMM20,%RSI

0x7172d VMOVQ	%XMM17,%RDI

0x71733 ADD	$0x4,%R13

0x71737 ADD	%R14,%R15

0x7173a CALL	706c0 <_ZZNK9SweepSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_RNS1_4Core9DataStoreENS1_6SdomIdEENKUlNS1_9DirectionENS1_5GroupENS1_5ZoneKENS1_5ZoneJENS1_5ZoneIEE_clESB_SC_SD_SE_SF_>

0x7173f MOV	0x100(%RSP),%R11    [1]

0x71747 CMP	%R11,%R13

0x7174a JNE	71683

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/internal.hpp: 165 - 254

--------------------------------------------------------------------------------

165:     camp::get<Idx>(offset_tuple) = i;

[...]

254:     ((camp::get<OffsetIdx>(data.segment_tuple).begin()[camp::get<OffsetIdx>(data.offset_tuple)])...,

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

Path /

Metric	Value
CQA speedup if no scalar integer	1.28
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.28
Bottlenecks	micro-operation queue,
Function	_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSH_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EEST_EENSP_INSR_INSS_5GroupElPSX_EESX_EENSP_INSQ_24strided_numeric_iteratorINSS_5ZoneKElPS12_EES12_EENSP_INS11_INSS_5ZoneJElPS16_EES16_EENSP_INS11_INSS_5ZoneIElPS1A_EES1A_EEEEENSN_IJEEEJZNK9SweepSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_RNSS_4Core9DataStoreENSS_6SdomIdEEUlST_SX_S12_S16_S1A_E_EEEEEvOS1M_._omp_fn.0.lto_priv.0
Source	internal.hpp:165-165,internal.hpp:254-254,forall.hpp:59-59
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.67
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	7.67
CQA cycles if fully vectorized	0.96
Front-end cycles	7.67
DIV/SQRT cycles	2.75
P0 cycles	2.75
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	6.00
P12 cycles	6.00
P13 cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	43.00
Nb uops	46.00
Nb loads	1.00
Nb stores	4.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.22
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.28
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.28
Bottlenecks	micro-operation queue,
Function	_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSH_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EEST_EENSP_INSR_INSS_5GroupElPSX_EESX_EENSP_INSQ_24strided_numeric_iteratorINSS_5ZoneKElPS12_EES12_EENSP_INS11_INSS_5ZoneJElPS16_EES16_EENSP_INS11_INSS_5ZoneIElPS1A_EES1A_EEEEENSN_IJEEEJZNK9SweepSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_RNSS_4Core9DataStoreENSS_6SdomIdEEUlST_SX_S12_S16_S1A_E_EEEEEvOS1M_._omp_fn.0.lto_priv.0
Source	internal.hpp:165-165,internal.hpp:254-254,forall.hpp:59-59
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.67
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	7.67
CQA cycles if fully vectorized	0.96
Front-end cycles	7.67
DIV/SQRT cycles	2.75
P0 cycles	2.75
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	6.00
P12 cycles	6.00
P13 cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	43.00
Nb uops	46.00
Nb loads	1.00
Nb stores	4.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.22
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSH_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EEST_EENSP_INSR_INSS_5GroupElPSX_EESX_EENSP_INSQ_24strided_numeric_iteratorINSS_5ZoneKElPS12_EES12_EENSP_INS11_INSS_5ZoneJElPS16_EES16_EENSP_INS11_INSS_5ZoneIElPS1A_EES1A_EEEEENSN_IJEEEJZNK9SweepSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_RNSS_4Core9DataStoreENSS_6SdomIdEEUlST_SX_S12_S16_S1A_E_EEEEEvOS1M_._omp_fn.0.lto_priv.0
Source file and lines	forall.hpp:59-59
Module	libkripke.so

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/internal.hpp:165,254
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

The related source loop is multi-versionned.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.67 to 6.00 cycles (1.28x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 7.67 to 0.96 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

_ZZNK9SweepSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_RNS1_4Core9DataStoreENS1_6SdomIdEENKUlNS1_9DirectionENS1_5GroupENS1_5ZoneKENS1_5ZoneJENS1_5ZoneIEE_clESB_SC_SD_SE_SF_: 4 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes. The binary loop is storing 32 bytes.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	43
nb uops	46
loop length	205
used x86 registers	13
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.67 cycles
front end	7.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.75	2.75	2.50	2.50	2.50	3.00	3.00	3.00	0.00	0.00	0.00	0.00	6.00	6.00
cycles	2.75	2.75	2.50	2.50	2.50	3.00	3.00	3.00	0.00	0.00	0.00	0.00	6.00	6.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	7.67
Dispatch	6.00
Data deps.	4.00
Overall L1	7.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.67 cycles. At this rate:

1% of peak load performance is reached (1.04 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (4.17 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 7.67 to 6.00 cycles (1.28x speedup).

ASM code

In the binary file, the address of the loop is: 71683

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
MOV %R15,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R12,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVQ %XMM18,%RDX	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM20,%RSI	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM17,%RDI	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
ADD %R14,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R13,0x5e8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
CALL 706c0 <_ZZNK9SweepSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_RNS1_4Core9DataStoreENS1_6SdomIdEENKUlNS1_9DirectionENS1_5GroupENS1_5ZoneKENS1_5ZoneJENS1_5ZoneIEE_clESB_SC_SD_SE_SF_>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
LEA 0x1(%R13),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R15,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R12,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVQ %XMM18,%RDX	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM20,%RSI	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOV %RDI,0x5e8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
VMOVQ %XMM17,%RDI	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
ADD %R14,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CALL 706c0 <_ZZNK9SweepSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_RNS1_4Core9DataStoreENS1_6SdomIdEENKUlNS1_9DirectionENS1_5GroupENS1_5ZoneKENS1_5ZoneJENS1_5ZoneIEE_clESB_SC_SD_SE_SF_>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
LEA 0x2(%R13),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R15,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R12,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVQ %XMM18,%RDX	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM17,%RDI	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOV %RSI,0x5e8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
VMOVQ %XMM20,%RSI	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
ADD %R14,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CALL 706c0 <_ZZNK9SweepSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_RNS1_4Core9DataStoreENS1_6SdomIdEENKUlNS1_9DirectionENS1_5GroupENS1_5ZoneKENS1_5ZoneJENS1_5ZoneIEE_clESB_SC_SD_SE_SF_>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
LEA 0x3(%R13),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R12,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R9,0x5e8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
VMOVQ %XMM18,%RDX	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOV %R15,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVQ %XMM20,%RSI	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM17,%RDI	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
ADD $0x4,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %R14,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CALL 706c0 <_ZZNK9SweepSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_RNS1_4Core9DataStoreENS1_6SdomIdEENKUlNS1_9DirectionENS1_5GroupENS1_5ZoneKENS1_5ZoneJENS1_5ZoneIEE_clESB_SC_SD_SE_SF_>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV 0x100(%RSP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CMP %R11,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 71683 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSH_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EEST_EENSP_INSR_INSS_5GroupElPSX_EESX_EENSP_INSQ_24strided_numeric_iteratorINSS_5ZoneKElPS12_EES12_EENSP_INS11_INSS_5ZoneJElPS16_EES16_EENSP_INS11_INSS_5ZoneIElPS1A_EES1A_EEEEENSN_IJEEEJZNK9SweepSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_RNSS_4Core9DataStoreENSS_6SdomIdEEUlST_SX_S12_S16_S1A_E_EEEEEvOS1M_._omp_fn.0.lto_priv.0+0x5a3>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1

Function	_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSH_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EEST_EENSP_INSR_INSS_5GroupElPSX_EESX_EENSP_INSQ_24strided_numeric_iteratorINSS_5ZoneKElPS12_EES12_EENSP_INS11_INSS_5ZoneJElPS16_EES16_EENSP_INS11_INSS_5ZoneIElPS1A_EES1A_EEEEENSN_IJEEEJZNK9SweepSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_RNSS_4Core9DataStoreENSS_6SdomIdEEUlST_SX_S12_S16_S1A_E_EEEEEvOS1M_._omp_fn.0.lto_priv.0
Source file and lines	forall.hpp:59-59
Module	libkripke.so

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/internal.hpp:165,254
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

The related source loop is multi-versionned.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.67 to 6.00 cycles (1.28x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 7.67 to 0.96 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

_ZZNK9SweepSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_RNS1_4Core9DataStoreENS1_6SdomIdEENKUlNS1_9DirectionENS1_5GroupENS1_5ZoneKENS1_5ZoneJENS1_5ZoneIEE_clESB_SC_SD_SE_SF_: 4 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes. The binary loop is storing 32 bytes.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	43
nb uops	46
loop length	205
used x86 registers	13
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.67 cycles
front end	7.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.75	2.75	2.50	2.50	2.50	3.00	3.00	3.00	0.00	0.00	0.00	0.00	6.00	6.00
cycles	2.75	2.75	2.50	2.50	2.50	3.00	3.00	3.00	0.00	0.00	0.00	0.00	6.00	6.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	7.67
Dispatch	6.00
Data deps.	4.00
Overall L1	7.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.67 cycles. At this rate:

1% of peak load performance is reached (1.04 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (4.17 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 71683

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
MOV %R15,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R12,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVQ %XMM18,%RDX	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM20,%RSI	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM17,%RDI	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
ADD %R14,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R13,0x5e8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
CALL 706c0 <_ZZNK9SweepSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_RNS1_4Core9DataStoreENS1_6SdomIdEENKUlNS1_9DirectionENS1_5GroupENS1_5ZoneKENS1_5ZoneJENS1_5ZoneIEE_clESB_SC_SD_SE_SF_>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
LEA 0x1(%R13),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R15,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R12,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVQ %XMM18,%RDX	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM20,%RSI	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOV %RDI,0x5e8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
VMOVQ %XMM17,%RDI	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
ADD %R14,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CALL 706c0 <_ZZNK9SweepSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_RNS1_4Core9DataStoreENS1_6SdomIdEENKUlNS1_9DirectionENS1_5GroupENS1_5ZoneKENS1_5ZoneJENS1_5ZoneIEE_clESB_SC_SD_SE_SF_>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
LEA 0x2(%R13),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R15,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R12,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVQ %XMM18,%RDX	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM17,%RDI	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOV %RSI,0x5e8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
VMOVQ %XMM20,%RSI	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
ADD %R14,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CALL 706c0 <_ZZNK9SweepSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_RNS1_4Core9DataStoreENS1_6SdomIdEENKUlNS1_9DirectionENS1_5GroupENS1_5ZoneKENS1_5ZoneJENS1_5ZoneIEE_clESB_SC_SD_SE_SF_>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
LEA 0x3(%R13),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R12,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R9,0x5e8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
VMOVQ %XMM18,%RDX	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOV %R15,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVQ %XMM20,%RSI	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM17,%RDI	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
ADD $0x4,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %R14,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CALL 706c0 <_ZZNK9SweepSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_RNS1_4Core9DataStoreENS1_6SdomIdEENKUlNS1_9DirectionENS1_5GroupENS1_5ZoneKENS1_5ZoneJENS1_5ZoneIEE_clESB_SC_SD_SE_SF_>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV 0x100(%RSP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CMP %R11,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 71683 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSH_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EEST_EENSP_INSR_INSS_5GroupElPSX_EESX_EENSP_INSQ_24strided_numeric_iteratorINSS_5ZoneKElPS12_EES12_EENSP_INS11_INSS_5ZoneJElPS16_EES16_EENSP_INS11_INSS_5ZoneIElPS1A_EES1A_EEEEENSN_IJEEEJZNK9SweepSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_RNSS_4Core9DataStoreENSS_6SdomIdEEUlST_SX_S12_S16_S1A_E_EEEEEvOS1M_._omp_fn.0.lto_priv.0+0x5a3>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> --groups 1024 --procs 2,1,1MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/run/oneview_runs/compilers/gcc_13/oneview_run_1708510989I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.96	0	1.04	-0	1.1	0	0.99	0	1.23	0	0.62	0.02	0.82	0.01

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.83	0.08
2x2	4	0.96	1.93	2	0.45	0.08
2x4	8	1.04	4.16	4	0.22	0.08
2x8	16	1.1	8.78	8	0.14	0.07
2x16	32	0.99	15.8	16	0.07	0.08
2x32	64	1.23	39.5	32	0.05	0.07
2x64	128	0.62	39.5	64	0.03	0.06
2x96	192	0.82	79	96	0.03	0.05

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency