OV - - Function _ZN6Kripke12ParallelComm12getReadyListEv

	Function: _ZN6Kripke12ParallelComm12getReadyListEv	Module: libkripke.so	Source: ParallelComm.cpp:254-263 [...]	Coverage: 0.04%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp: 254 - 263

--------------------------------------------------------------------------------

254: std::vector<SdomId> ParallelComm::getReadyList(void){

255:   // build up a list of ready subdomains

256:   std::vector<SdomId> ready;

257:   for(size_t i = 0;i < queue_depends.size();++ i){

258:     if(queue_depends[i] == 0){

259:       ready.push_back(SdomId(queue_sdom_ids[i]));

260:     }

261:   }

262:   return ready;

263: }

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/vector.tcc: 114 - 523

--------------------------------------------------------------------------------

114: 	if (this->_M_impl._M_finish != this->_M_impl._M_end_of_storage)

115: 	  {

116: 	    _GLIBCXX_ASAN_ANNOTATE_GROW(1);

117: 	    _Alloc_traits::construct(this->_M_impl, this->_M_impl._M_finish,

118: 				     std::forward<_Args>(__args)...);

119: 	    ++this->_M_impl._M_finish;

[...]

445:       vector<_Tp, _Alloc>::

[...]

483: 	      ++__new_finish;

[...]

520: 		    this->_M_impl._M_end_of_storage - __old_start);

521:       this->_M_impl._M_start = __new_start;

522:       this->_M_impl._M_finish = __new_finish;

523:       this->_M_impl._M_end_of_storage = __new_start + __len;

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h: 100 - 1899

--------------------------------------------------------------------------------

100: 	: _M_start(), _M_finish(), _M_end_of_storage()

[...]

378: 	return __n != 0 ? _Tr::allocate(_M_impl, __n) : pointer();

[...]

386: 	if (__p)

[...]

990:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1895: 	if (max_size() - size() < __n)

1896: 	  __throw_length_error(__N(__s));

1897:

1898: 	const size_type __len = size() + (std::max)(size(), __n);

1899: 	return (__len < size() || __len > max_size()) ? max_size() : __len;

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_uninitialized.h: 1104 - 1105

--------------------------------------------------------------------------------

1104:       _ForwardIterator __cur = __result;

1105:       for (; __first != __last; ++__first, (void)++__cur)

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_algobase.h: 262 - 262

--------------------------------------------------------------------------------

262:       if (__a < __b)

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/new_allocator.h: 147 - 187

--------------------------------------------------------------------------------

147: 	return static_cast<_Tp*>(_GLIBCXX_OPERATOR_NEW(__n * sizeof(_Tp)));

[...]

168: 	_GLIBCXX_OPERATOR_DELETE(_GLIBCXX_SIZED_DEALLOC(__p, __n));

[...]

187: 	{ ::new((void *)__p) _Up(std::forward<_Args>(__args)...); }

0x7da10 PUSH	%RBP

0x7da11 MOV	%RSP,%RBP

0x7da14 PUSH	%R15

0x7da16 PUSH	%R14

0x7da18 PUSH	%R13

0x7da1a PUSH	%R12

0x7da1c PUSH	%RBX

0x7da1d MOV	%RDI,%R14

0x7da20 SUB	$0x28,%RSP

0x7da24 MOV	0x70(%RSI),%R8

0x7da28 MOVQ	$0,(%RDI)

0x7da2f MOVQ	$0,0x8(%RDI)

0x7da37 MOVQ	$0,0x10(%RDI)

0x7da3f CMP	%R8,0x78(%RSI)

0x7da43 JE	7daa0

0x7da45 MOV	%RSI,%R13

0x7da48 XOR	%EBX,%EBX

0x7da4a JMP	7da63

0x7da4c NOPL	(%RAX)

(1191) 0x7da50 MOV	0x78(%R13),%RSI

(1191) 0x7da54 INC	%RBX

(1191) 0x7da57 SUB	%R8,%RSI

(1191) 0x7da5a SAR	$0x2,%RSI

(1191) 0x7da5e CMP	%RSI,%RBX

(1191) 0x7da61 JAE	7daa0

(1191) 0x7da63 MOV	(%R8,%RBX,4),%ECX

(1191) 0x7da67 LEA	(,%RBX,4),%RAX

(1191) 0x7da6f TEST	%ECX,%ECX

(1191) 0x7da71 JNE	7da50

(1191) 0x7da73 MOV	0x58(%R13),%RSI

(1191) 0x7da77 MOV	0x8(%R14),%R12

(1191) 0x7da7b MOVSXD	(%RSI,%RAX,1),%R15

(1191) 0x7da7f MOV	0x10(%R14),%RSI

(1191) 0x7da83 CMP	%RSI,%R12

(1191) 0x7da86 JE	7dac0

(1191) 0x7da88 MOV	%R15,(%R12)

(1191) 0x7da8c ADD	$0x8,%R12

(1191) 0x7da90 MOV	%R12,0x8(%R14)

(1191) 0x7da94 JMP	7da50

0x7da96 NOPW	%CS:(%RAX,%RAX,1)

0x7daa0 ADD	$0x28,%RSP

0x7daa4 MOV	%R14,%RAX

0x7daa7 POP	%RBX

0x7daa8 POP	%R12

0x7daaa POP	%R13

0x7daac POP	%R14

0x7daae POP	%R15

0x7dab0 POP	%RBP

0x7dab1 RET

0x7dab2 NOPW	%CS:(%RAX,%RAX,1)

0x7dabd NOPL	(%RAX)

(1191) 0x7dac0 MOV	(%R14),%RDX

(1191) 0x7dac3 MOV	%R12,%RDI

(1191) 0x7dac6 MOV	$0xfffffffffffffff,%R8

(1191) 0x7dad0 SUB	%RDX,%RDI

(1191) 0x7dad3 MOV	%RDX,-0x38(%RBP)

(1191) 0x7dad7 MOV	%RDI,-0x50(%RBP)

(1191) 0x7dadb SAR	$0x3,%RDI

(1191) 0x7dadf CMP	%R8,%RDI

(1191) 0x7dae2 JE	7dcfa

(1191) 0x7dae8 MOV	-0x38(%RBP),%R9

(1191) 0x7daec CMP	%R9,%R12

(1191) 0x7daef JE	7dca0

(1191) 0x7daf5 LEA	(%RDI,%RDI,1),%R10

(1191) 0x7daf9 CMP	%RDI,%R10

(1191) 0x7dafc JB	7dc60

(1191) 0x7db02 TEST	%R10,%R10

(1191) 0x7db05 JNE	7dcd8

(1191) 0x7db0b MOV	-0x50(%RBP),%R11

(1191) 0x7db0f XOR	%EAX,%EAX

(1191) 0x7db11 XOR	%R8D,%R8D

(1191) 0x7db14 MOV	%R15,(%R11)

(1191) 0x7db17 MOV	-0x38(%RBP),%R15

(1191) 0x7db1b MOV	%RAX,%RDX

(1191) 0x7db1e SUB	%R15,%R12

(1191) 0x7db21 LEA	(%RAX,%R12,1),%R9

(1191) 0x7db25 LEA	-0x8(%R12),%R12

(1191) 0x7db2a SHR	$0x3,%R12

(1191) 0x7db2e LEA	0x1(%R12),%R10

(1191) 0x7db33 AND	$0x7,%R10D

(1191) 0x7db37 JE	7dbc4

(1191) 0x7db3d CMP	$0x1,%R10

(1191) 0x7db41 JE	7dbb0

(1191) 0x7db43 CMP	$0x2,%R10

(1191) 0x7db47 JE	7dba1

(1191) 0x7db49 CMP	$0x3,%R10

(1191) 0x7db4d JE	7db92

(1191) 0x7db4f CMP	$0x4,%R10

(1191) 0x7db53 JE	7db83

(1191) 0x7db55 CMP	$0x5,%R10

(1191) 0x7db59 JE	7db74

(1191) 0x7db5b CMP	$0x6,%R10

(1191) 0x7db5f JNE	7dcc1

(1191) 0x7db65 MOV	(%R15),%RDI

(1191) 0x7db68 ADD	$0x8,%RDX

(1191) 0x7db6c ADD	$0x8,%R15

(1191) 0x7db70 MOV	%RDI,-0x8(%RDX)

(1191) 0x7db74 MOV	(%R15),%R12

(1191) 0x7db77 ADD	$0x8,%RDX

(1191) 0x7db7b ADD	$0x8,%R15

(1191) 0x7db7f MOV	%R12,-0x8(%RDX)

(1191) 0x7db83 MOV	(%R15),%R10

(1191) 0x7db86 ADD	$0x8,%RDX

(1191) 0x7db8a ADD	$0x8,%R15

(1191) 0x7db8e MOV	%R10,-0x8(%RDX)

(1191) 0x7db92 MOV	(%R15),%R11

(1191) 0x7db95 ADD	$0x8,%RDX

(1191) 0x7db99 ADD	$0x8,%R15

(1191) 0x7db9d MOV	%R11,-0x8(%RDX)

(1191) 0x7dba1 MOV	(%R15),%RCX

(1191) 0x7dba4 ADD	$0x8,%RDX

(1191) 0x7dba8 ADD	$0x8,%R15

(1191) 0x7dbac MOV	%RCX,-0x8(%RDX)

(1191) 0x7dbb0 MOV	(%R15),%RDI

(1191) 0x7dbb3 ADD	$0x8,%RDX

(1191) 0x7dbb7 ADD	$0x8,%R15

(1191) 0x7dbbb MOV	%RDI,-0x8(%RDX)

(1191) 0x7dbbf CMP	%R9,%RDX

(1191) 0x7dbc2 JE	7dc10

  (1192) 0x7dbc4 MOV	(%R15),%R12

  (1192) 0x7dbc7 ADD	$0x40,%RDX

  (1192) 0x7dbcb ADD	$0x40,%R15

  (1192) 0x7dbcf MOV	%R12,-0x40(%RDX)

  (1192) 0x7dbd3 MOV	-0x38(%R15),%R10

  (1192) 0x7dbd7 MOV	%R10,-0x38(%RDX)

  (1192) 0x7dbdb MOV	-0x30(%R15),%R11

  (1192) 0x7dbdf MOV	%R11,-0x30(%RDX)

  (1192) 0x7dbe3 MOV	-0x28(%R15),%RCX

  (1192) 0x7dbe7 MOV	%RCX,-0x28(%RDX)

  (1192) 0x7dbeb MOV	-0x20(%R15),%RDI

  (1192) 0x7dbef MOV	%RDI,-0x20(%RDX)

  (1192) 0x7dbf3 MOV	-0x18(%R15),%R12

  (1192) 0x7dbf7 MOV	%R12,-0x18(%RDX)

  (1192) 0x7dbfb MOV	-0x10(%R15),%R10

  (1192) 0x7dbff MOV	%R10,-0x10(%RDX)

  (1192) 0x7dc03 MOV	-0x8(%R15),%R11

  (1192) 0x7dc07 MOV	%R11,-0x8(%RDX)

  (1192) 0x7dc0b CMP	%R9,%RDX

  (1192) 0x7dc0e JNE	7dbc4

(1191) 0x7dc10 ADD	$0x8,%RDX

(1191) 0x7dc14 VMOVQ	%RAX,%XMM1

(1191) 0x7dc19 MOV	-0x38(%RBP),%RAX

(1191) 0x7dc1d VPINSRQ	$0x1,%RDX,%XMM1,%XMM0

(1191) 0x7dc23 TEST	%RAX,%RAX

(1191) 0x7dc26 JE	7dc45

(1191) 0x7dc28 SUB	%RAX,%RSI

(1191) 0x7dc2b MOV	%RAX,%RDI

(1191) 0x7dc2e VMOVDQA	%XMM0,-0x50(%RBP)

(1191) 0x7dc33 MOV	%R8,-0x38(%RBP)

(1191) 0x7dc37 CALL	93a0 <_ZdlPvm@plt>

(1191) 0x7dc3c VMOVDQA	-0x50(%RBP),%XMM0

(1191) 0x7dc41 MOV	-0x38(%RBP),%R8

(1191) 0x7dc45 MOV	%R8,0x10(%R14)

(1191) 0x7dc49 VMOVDQU	%XMM0,(%R14)

(1191) 0x7dc4e MOV	0x70(%R13),%R8

(1191) 0x7dc52 JMP	7da50

0x7dc57 NOPW	(%RAX,%RAX,1)

(1191) 0x7dc60 MOV	$0x7ffffffffffffff8,%RDX

(1191) 0x7dc6a MOV	%RDX,-0x40(%RBP)

(1191) 0x7dc6e MOV	-0x40(%RBP),%RDI

(1191) 0x7dc72 CALL	9390 <_Znwm@plt>

(1191) 0x7dc77 MOV	-0x50(%RBP),%RDI

(1191) 0x7dc7b MOV	-0x40(%RBP),%R8

(1191) 0x7dc7f LEA	0x8(%RAX),%RDX

(1191) 0x7dc83 MOV	0x10(%R14),%RSI

(1191) 0x7dc87 MOV	%R15,(%RAX,%RDI,1)

(1191) 0x7dc8b MOV	-0x38(%RBP),%R15

(1191) 0x7dc8f ADD	%RAX,%R8

(1191) 0x7dc92 CMP	%R15,%R12

(1191) 0x7dc95 JNE	7db17

(1191) 0x7dc9b JMP	7dc14

(1191) 0x7dca0 ADD	$0x1,%RDI

(1191) 0x7dca4 JB	7dc60

(1191) 0x7dca6 MOV	$0xfffffffffffffff,%RSI

(1191) 0x7dcb0 CMP	%RSI,%RDI

(1191) 0x7dcb3 CMOVA	%RSI,%RDI

(1191) 0x7dcb7 SAL	$0x3,%RDI

(1191) 0x7dcbb MOV	%RDI,-0x40(%RBP)

(1191) 0x7dcbf JMP	7dc6e

(1191) 0x7dcc1 MOV	-0x38(%RBP),%R11

(1191) 0x7dcc5 LEA	0x8(%RAX),%RDX

(1191) 0x7dcc9 MOV	(%R11),%RCX

(1191) 0x7dccc LEA	0x8(%R11),%R15

(1191) 0x7dcd0 MOV	%RCX,(%RAX)

(1191) 0x7dcd3 JMP	7db65

(1191) 0x7dcd8 MOV	$0xfffffffffffffff,%RAX

(1191) 0x7dce2 CMP	%RAX,%R10

(1191) 0x7dce5 CMOVA	%RAX,%R10

(1191) 0x7dce9 LEA	(,%R10,8),%RCX

(1191) 0x7dcf1 MOV	%RCX,-0x40(%RBP)

(1191) 0x7dcf5 JMP	7dc6e

0x7dcfa LEA	0x79349(%RIP),%RDI

0x7dd01 CALL	9220 <_ZSt20__throw_length_errorPKc@plt>

0x7dd06 MOV	%RAX,%R13

0x7dd09 JMP	dc30

0x7dd0e XCHG	%AX,%AX

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	ParallelComm.cpp:254-263
Module	libkripke.so

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp:254-263
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/vector.tcc:114-119,445,483,520-523
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h:100,378,386,990,1895-1899
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_uninitialized.h:1104-1105
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_algobase.h:262
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/new_allocator.h:147,168,187

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 5.33 to 0.35 cycles (15.18x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

_ZSt20__throw_length_errorPKc@plt: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 24 bytes.

General properties

nb instructions	37
nb uops	32
loop length	137
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.33 cycles
front end	5.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.50	1.50	1.25	1.25	2.50	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.50	1.50	1.25	1.25	2.50	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.33
Dispatch	2.50
Overall L1	5.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.33 cycles. At this rate:

3% of peak load performance is reached (3.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.50 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.33 to 2.50 cycles (2.13x speedup).

ASM code

In the binary file, the address of the function is: 7da10

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0.17
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV 0x70(%RSI),%R8	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOVQ $0,(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x8(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x10(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
CMP %R8,0x78(%RSI)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
JE 7daa0 <_ZN6Kripke12ParallelComm12getReadyListEv+0x90>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV %RSI,%R13	1	0	0	0	0	0	0	0	0	0	0.17
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0.25
JMP 7da63 <_ZN6Kripke12ParallelComm12getReadyListEv+0x53>	1	0.50	0	0	0	0.50	0	0	0	0	1
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0.17
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
LEA 0x79349(%RIP),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CALL 9220 <_ZSt20__throw_length_errorPKc@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0.17
JMP dc30 <_ZN6Kripke12ParallelComm12getReadyListEv.cold>	1	0.50	0	0	0	0.50	0	0	0	0	1
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	ParallelComm.cpp:254-263
Module	libkripke.so

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp:254-263
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/vector.tcc:114-119,445,483,520-523
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h:100,378,386,990,1895-1899
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_uninitialized.h:1104-1105
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_algobase.h:262
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/new_allocator.h:147,168,187

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

_ZSt20__throw_length_errorPKc@plt: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 24 bytes.

General properties

nb instructions	37
nb uops	32
loop length	137
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.33 cycles
front end	5.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.50	1.50	1.25	1.25	2.50	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.50	1.50	1.25	1.25	2.50	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.33
Dispatch	2.50
Overall L1	5.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.33 cycles. At this rate:

3% of peak load performance is reached (3.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.50 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 7da10

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0.17
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV 0x70(%RSI),%R8	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOVQ $0,(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x8(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x10(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
CMP %R8,0x78(%RSI)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
JE 7daa0 <_ZN6Kripke12ParallelComm12getReadyListEv+0x90>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV %RSI,%R13	1	0	0	0	0	0	0	0	0	0	0.17
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0.25
JMP 7da63 <_ZN6Kripke12ParallelComm12getReadyListEv+0x53>	1	0.50	0	0	0	0.50	0	0	0	0	1
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0.17
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
LEA 0x79349(%RIP),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CALL 9220 <_ZSt20__throw_length_errorPKc@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0.17
JMP dc30 <_ZN6Kripke12ParallelComm12getReadyListEv.cold>	1	0.50	0	0	0	0.50	0	0	0	0	1
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0.09

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> --groups 1024 --procs 2,1,1MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/run/oneview_runs/compilers/gcc_13/oneview_run_1708510989I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	2.15	0	3.58	0	1	0	1	0	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.79	0.04
2x2	2	2.15	4.3	2	0.26	0.02
2x4	1	3.58	14.33	4	0.23	0.01
2x8	2	1	1	8	0.05	0
2x16	2	1	1	16	0.03	0
2x32	2	1	1	32	0.04	0
2x64	1	1	1	64	0.26	0.01
2x96	2	1	1	96	0.12	0

Name	Coverage (%)	Time (s)
▼_ZN6Kripke12ParallelComm12getReadyListEv–	0.04	0.43
▼Loop 1191 - new_allocator.h:147-187 - libkripke.so–	0.03	0.34
○Loop 1192 - new_allocator.h:187-187 - libkripke.so	0	0

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency