OV - - Loop 664 - libkripke.so

	Loop Id: 664	Module: libkripke.so	Source: forall.hpp:59-59 [...]	Coverage: 0.01%

0x52ff0 ADD	-0xa8(%RBP),%RDX

0x52ff7 ADD	-0x98(%RBP),%R12

0x52ffe INC	%R11

0x53001 CMP	-0x60(%RBP),%R11

0x53005 JE	52ef0

0x5300b MOV	-0x58(%RBP),%RCX

0x5300f LEA	(%R11,%RCX,1),%R13

0x53013 IMUL	-0xa0(%RBP),%R13

0x5301b ADD	-0x148(%RBP),%R13

0x53022 CMPB	$0,-0x29(%RBP)

0x53026 JE	53070

0x53028 XOR	%ESI,%ESI

0x5302a MOV	-0x38(%RBP),%RDI

0x5302e LEA	(%RAX,%RSI,1),%RCX

0x53032 MOV	%R8,%R9

0x53035 SUB	%RSI,%R9

0x53038 ADD	%R12,%RSI

0x5303b LEA	(%RDI,%RCX,8),%RCX

0x5303f MOV	-0x40(%RBP),%RDI

0x53043 LEA	(%RDI,%RSI,8),%RSI

0x53047 XOR	%EDI,%EDI

0x53049 NOPL	(%RAX)

  (662) 0x53050 VMOVSD	(%R14,%R13,8),%XMM0

  (662) 0x53056 VMOVSD	(%RSI,%RDI,8),%XMM1

  (662) 0x5305b VFMADD213SD	(%RCX,%RDI,8),%XMM0,%XMM1

  (662) 0x53061 VMOVSD	%XMM1,(%RCX,%RDI,8)

  (662) 0x53066 INC	%RDI

  (662) 0x53069 CMP	%RDI,%R9

  (662) 0x5306c JNE	53050

0x5306e JMP	52ff0

0x53070 MOV	-0xa8(%RBP),%RSI

0x53077 MOV	-0x138(%RBP),%RCX

0x5307e MOV	-0x40(%RBP),%RAX

0x53082 MOV	-0x120(%RBP),%RDI

0x53089 MOV	-0x140(%RBP),%R9

0x53090 MOV	-0x128(%RBP),%RBX

0x53097 IMUL	%R11,%RSI

0x5309b LEA	(%RDI,%R11,8),%RDI

0x5309f LEA	(%R9,%R11,8),%R9

0x530a3 ADD	%R14,%RDI

0x530a6 ADD	%R14,%R9

0x530a9 ADD	%RSI,%RCX

0x530ac ADD	-0x118(%RBP),%RSI

0x530b3 ADD	%RAX,%RCX

0x530b6 ADD	%RAX,%RSI

0x530b9 MOV	-0x130(%RBP),%RAX

0x530c0 CMP	%RDI,%RAX

0x530c3 SETB	%DIL

0x530c7 CMP	%RBX,%R9

0x530ca SETB	%R9B

0x530ce CMP	%RCX,%RAX

0x530d1 SETB	%CL

0x530d4 CMP	%RBX,%RSI

0x530d7 SETB	%SIL

0x530db TEST	%R9B,%DIL

0x530de JNE	53102

0x530e0 MOV	-0x90(%RBP),%RAX

0x530e7 AND	%SIL,%CL

0x530ea MOV	$0,%ESI

0x530ef JNE	5302a

0x530f5 CMP	$0x20,%R8

0x530f9 JAE	5310e

0x530fb XOR	%EDI,%EDI

0x530fd JMP	5319f

0x53102 MOV	-0x90(%RBP),%RAX

0x53109 JMP	53028

0x5310e VBROADCASTSD	(%R14,%R13,8),%ZMM0

0x53115 XOR	%R9D,%R9D

0x53118 NOPL	(%RAX,%RAX,1)

  (665) 0x53120 VMOVUPD	-0xc0(%RDX,%R9,8),%ZMM1

  (665) 0x53128 VMOVUPD	-0x80(%RDX,%R9,8),%ZMM2

  (665) 0x53130 VMOVUPD	-0x40(%RDX,%R9,8),%ZMM3

  (665) 0x53138 VMOVUPD	(%RDX,%R9,8),%ZMM4

  (665) 0x5313f VFMADD213PD	-0xc0(%R10,%R9,8),%ZMM0,%ZMM1

  (665) 0x53147 VFMADD213PD	-0x80(%R10,%R9,8),%ZMM0,%ZMM2

  (665) 0x5314f VFMADD213PD	-0x40(%R10,%R9,8),%ZMM0,%ZMM3

  (665) 0x53157 VFMADD213PD	(%R10,%R9,8),%ZMM0,%ZMM4

  (665) 0x5315e VMOVUPD	%ZMM1,-0xc0(%R10,%R9,8)

  (665) 0x53166 VMOVUPD	%ZMM2,-0x80(%R10,%R9,8)

  (665) 0x5316e VMOVUPD	%ZMM3,-0x40(%R10,%R9,8)

  (665) 0x53176 VMOVUPD	%ZMM4,(%R10,%R9,8)

  (665) 0x5317d ADD	$0x20,%R9

  (665) 0x53181 CMP	%R9,%R15

  (665) 0x53184 JNE	53120

0x53186 CMP	%R15,%R8

0x53189 JE	52ff0

0x5318f MOV	%R15,%RDI

0x53192 MOV	%R15,%RSI

0x53195 TEST	$0x1c,%R8B

0x53199 JE	5302a

0x5319f VBROADCASTSD	(%R14,%R13,8),%YMM0

0x531a5 MOV	-0x88(%RBP),%R9

0x531ac MOV	-0x38(%RBP),%RSI

0x531b0 MOV	-0x40(%RBP),%RBX

0x531b4 LEA	(%RAX,%RDI,1),%RCX

0x531b8 SUB	%RDI,%R9

0x531bb ADD	%R12,%RDI

0x531be LEA	(%RSI,%RCX,8),%RCX

0x531c2 LEA	(%RBX,%RDI,8),%RSI

0x531c6 XOR	%EDI,%EDI

0x531c8 NOPL	(%RAX,%RAX,1)

  (666) 0x531d0 VMOVUPD	(%RSI,%RDI,8),%YMM1

  (666) 0x531d5 VFMADD213PD	(%RCX,%RDI,8),%YMM0,%YMM1

  (666) 0x531db VMOVUPD	%YMM1,(%RCX,%RDI,8)

  (666) 0x531e0 ADD	$0x4,%RDI

  (666) 0x531e4 CMP	%RDI,%R9

  (666) 0x531e7 JNE	531d0

0x531e9 MOV	-0x88(%RBP),%RCX

0x531f0 MOV	%RCX,%RSI

0x531f3 CMP	%RCX,%R8

0x531f6 JE	52ff0

0x531fc JMP	5302a

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/LTimes.cpp: 62 - 62

--------------------------------------------------------------------------------

62:            phi(nm,g,z) += ell(nm, d) * psi(d, g, z);

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

Path /

Metric	Value
CQA speedup if no scalar integer	3.38
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.72
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	micro-operation queue,
Function	.omp_outlined..152
Source	forall.hpp:59-59
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.50
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	13.50
CQA cycles if fully vectorized	2.01
Front-end cycles	13.50
DIV/SQRT cycles	12.00
P0 cycles	12.00
P1 cycles	11.75
P2 cycles	11.75
P3 cycles	6.50
P4 cycles	8.33
P5 cycles	8.33
P6 cycles	8.33
P7 cycles	0.00
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	84.00
Nb uops	81.00
Nb loads	25.00
Nb stores	0.00
Nb stack references	17.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.30
Bytes prefetched	0.00
Bytes loaded	193.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.59
Vector-efficiency ratio load	10.68
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.41

Metric	Value
CQA speedup if no scalar integer	3.38
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.72
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	micro-operation queue,
Function	.omp_outlined..152
Source	forall.hpp:59-59
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.50
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	13.50
CQA cycles if fully vectorized	2.01
Front-end cycles	13.50
DIV/SQRT cycles	12.00
P0 cycles	12.00
P1 cycles	11.75
P2 cycles	11.75
P3 cycles	6.50
P4 cycles	8.33
P5 cycles	8.33
P6 cycles	8.33
P7 cycles	0.00
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	84.00
Nb uops	81.00
Nb loads	25.00
Nb stores	0.00
Nb stack references	17.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.30
Bytes prefetched	0.00
Bytes loaded	193.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.59
Vector-efficiency ratio load	10.68
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.41

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..152
Source file and lines	forall.hpp:59-59
Module	libkripke.so

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/LTimes.cpp:62
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=9
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 9 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.50 to 4.00 cycles (3.37x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 13.50 to 2.01 cycles (6.72x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 193 bytes.

General properties

nb instructions	84
nb uops	81
loop length	372
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	1
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.50 cycles
front end	13.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	12.00	12.00	11.75	11.75	6.50	8.33	8.33	8.33	0.00	0.50	0.50	0.00	0.00	0.00
cycles	12.00	12.00	11.75	11.75	6.50	8.33	8.33	8.33	0.00	0.50	0.50	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.50
Dispatch	12.00
Overall L1	13.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	9%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.50 cycles. At this rate:

14% of peak load performance is reached (14.30 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 13.50 to 12.00 cycles (1.13x speedup).

ASM code

In the binary file, the address of the loop is: 5300b

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	Latency	Recip. throughput
ADD -0xa8(%RBP),%RDX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
ADD -0x98(%RBP),%R12	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
INC %R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP -0x60(%RBP),%R11	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
JE 52ef0 <.omp_outlined..152+0x230>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV -0x58(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (%R11,%RCX,1),%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
IMUL -0xa0(%RBP),%R13	1	0	1	0	0	0	0.33	0.33	0.33	0	0	3	1
ADD -0x148(%RBP),%R13	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
CMPB $0,-0x29(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
JE 53070 <.omp_outlined..152+0x3b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.25
MOV -0x38(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (%RAX,%RSI,1),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB %RSI,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %R12,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RDI,%RCX,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV -0x40(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (%RDI,%RSI,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
JMP 52ff0 <.omp_outlined..152+0x330>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
MOV -0xa8(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x138(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x120(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x140(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x128(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
IMUL %R11,%RSI	1	0	1	0	0	0	0	0	0	0	0	3	1
LEA (%RDI,%R11,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%R9,%R11,8),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %R14,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %R14,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %RSI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD -0x118(%RBP),%RSI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
ADD %RAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %RAX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV -0x130(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CMP %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SETB %DIL	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50
CMP %RBX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SETB %R9B	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50
CMP %RCX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SETB %CL	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50
CMP %RBX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SETB %SIL	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50
TEST %R9B,%DIL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 53102 <.omp_outlined..152+0x442>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV -0x90(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
AND %SIL,%CL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV $0,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 5302a <.omp_outlined..152+0x36a>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
CMP $0x20,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JAE 5310e <.omp_outlined..152+0x44e>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 5319f <.omp_outlined..152+0x4df>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
MOV -0x90(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
JMP 53028 <.omp_outlined..152+0x368>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
VBROADCASTSD (%R14,%R13,8),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	5	1
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
CMP %R15,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 52ff0 <.omp_outlined..152+0x330>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
TEST $0x1c,%R8B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 5302a <.omp_outlined..152+0x36a>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
VBROADCASTSD (%R14,%R13,8),%YMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV -0x88(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x38(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x40(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (%RAX,%RDI,1),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUB %RDI,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %R12,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RSI,%RCX,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RBX,%RDI,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV -0x88(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %RCX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 52ff0 <.omp_outlined..152+0x330>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
JMP 5302a <.omp_outlined..152+0x36a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1

Function	.omp_outlined..152
Source file and lines	forall.hpp:59-59
Module	libkripke.so

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/LTimes.cpp:62
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=9
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.50 to 4.00 cycles (3.37x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 193 bytes.

General properties

nb instructions	84
nb uops	81
loop length	372
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	1
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.50 cycles
front end	13.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	12.00	12.00	11.75	11.75	6.50	8.33	8.33	8.33	0.00	0.50	0.50	0.00	0.00	0.00
cycles	12.00	12.00	11.75	11.75	6.50	8.33	8.33	8.33	0.00	0.50	0.50	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.50
Dispatch	12.00
Overall L1	13.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	9%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.50 cycles. At this rate:

14% of peak load performance is reached (14.30 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 5300b

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	Latency	Recip. throughput
ADD -0xa8(%RBP),%RDX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
ADD -0x98(%RBP),%R12	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
INC %R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP -0x60(%RBP),%R11	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
JE 52ef0 <.omp_outlined..152+0x230>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV -0x58(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (%R11,%RCX,1),%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
IMUL -0xa0(%RBP),%R13	1	0	1	0	0	0	0.33	0.33	0.33	0	0	3	1
ADD -0x148(%RBP),%R13	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
CMPB $0,-0x29(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
JE 53070 <.omp_outlined..152+0x3b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.25
MOV -0x38(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (%RAX,%RSI,1),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB %RSI,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %R12,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RDI,%RCX,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV -0x40(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (%RDI,%RSI,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
JMP 52ff0 <.omp_outlined..152+0x330>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
MOV -0xa8(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x138(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x120(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x140(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x128(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
IMUL %R11,%RSI	1	0	1	0	0	0	0	0	0	0	0	3	1
LEA (%RDI,%R11,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%R9,%R11,8),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %R14,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %R14,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %RSI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD -0x118(%RBP),%RSI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
ADD %RAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %RAX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV -0x130(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CMP %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SETB %DIL	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50
CMP %RBX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SETB %R9B	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50
CMP %RCX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SETB %CL	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50
CMP %RBX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SETB %SIL	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50
TEST %R9B,%DIL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 53102 <.omp_outlined..152+0x442>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV -0x90(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
AND %SIL,%CL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV $0,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 5302a <.omp_outlined..152+0x36a>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
CMP $0x20,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JAE 5310e <.omp_outlined..152+0x44e>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 5319f <.omp_outlined..152+0x4df>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
MOV -0x90(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
JMP 53028 <.omp_outlined..152+0x368>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
VBROADCASTSD (%R14,%R13,8),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	5	1
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
CMP %R15,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 52ff0 <.omp_outlined..152+0x330>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
TEST $0x1c,%R8B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 5302a <.omp_outlined..152+0x36a>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
VBROADCASTSD (%R14,%R13,8),%YMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV -0x88(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x38(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x40(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (%RAX,%RDI,1),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUB %RDI,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %R12,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RSI,%RCX,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RBX,%RDI,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV -0x88(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %RCX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 52ff0 <.omp_outlined..152+0x330>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
JMP 5302a <.omp_outlined..152+0x36a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> --groups 1024 --procs 2,1,1MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/run/oneview_runs/compilers/aocc_10/oneview_run_1708510900I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1.07	-0	1.25	-0	1.88	0	0.94	0	0.47	0.01	0.23	0.02	0.16	0.03

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.17	0.01
2x2	4	1.07	2.14	2	0.09	0.01
2x4	8	1.25	5	4	0.05	0.01
2x8	16	1.88	15	8	0.04	0.01
2x16	32	0.94	15	16	0.02	0.01
2x32	64	0.47	15	32	0.02	0.02
2x64	127	0.23	15	64	0.02	0.02
2x96	192	0.16	15	96	0.02	0.03

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency