OV - - Loop 1076 - libkripke.so

0x7fe70 MOV	%R15,-0x38(%RBP)

0x7fe74 IMUL	-0x90(%RBP),%R15

0x7fe7c MOV	-0x158(%RBP),%R10

0x7fe83 XOR	%R13D,%R13D

0x7fe86 ADD	-0x98(%RBP),%R15

0x7fe8d LEA	(%R10,%R15,1),%R12

0x7fe91 XOR	%R10D,%R10D

0x7fe94 NOPW	%CS:(%RAX,%RAX,1)

  (1075) 0x7fea0 MOV	-0x178(%RBP),%RAX

  (1075) 0x7fea7 VMOVSD	(%RAX,%R8,8),%XMM1

  (1075) 0x7fead MOV	-0x170(%RBP),%RAX

  (1075) 0x7feb4 VADDSD	%XMM1,%XMM1,%XMM1

  (1075) 0x7feb8 VDIVSD	(%RAX,%R15,8),%XMM1,%XMM1

  (1075) 0x7febe MOV	-0x180(%RBP),%RAX

  (1075) 0x7fec5 VMOVSD	(%RAX,%R8,8),%XMM2

  (1075) 0x7fecb MOV	-0x168(%RBP),%RAX

  (1075) 0x7fed2 VMOVHPD	(%RAX,%R8,8),%XMM2,%XMM2

  (1075) 0x7fed8 MOV	-0x50(%RBP),%RAX

  (1075) 0x7fedc VMOVSD	(%RAX,%R10,1),%XMM3

  (1075) 0x7fee2 MOV	-0x160(%RBP),%RAX

  (1075) 0x7fee9 VADDPD	%XMM2,%XMM2,%XMM2

  (1075) 0x7feed VMOVHPD	(%RAX,%RCX,8),%XMM3,%XMM3

  (1075) 0x7fef2 VDIVPD	%XMM3,%XMM2,%XMM2

  (1075) 0x7fef6 VMOVSD	(%R14,%R12,8),%XMM3

  (1075) 0x7fefc VFMADD213SD	(%RDX,%R13,1),%XMM2,%XMM3

  (1075) 0x7ff02 VPERMILPD	$0x1,%XMM2,%XMM4

  (1075) 0x7ff08 VFMADD231SD	(%RSI,%R10,1),%XMM1,%XMM3

  (1075) 0x7ff0e VADDSD	%XMM1,%XMM2,%XMM1

  (1075) 0x7ff12 VADDSD	%XMM4,%XMM1,%XMM1

  (1075) 0x7ff16 VADDSD	(%RDI,%R13,1),%XMM1,%XMM1

  (1075) 0x7ff1c VFMADD231SD	(%RBX,%R10,1),%XMM4,%XMM3

  (1075) 0x7ff22 VDIVSD	%XMM1,%XMM3,%XMM1

  (1075) 0x7ff26 VMOVSD	%XMM1,(%R9,%R13,1)

  (1075) 0x7ff2c ADD	-0x58(%RBP),%R13

  (1075) 0x7ff30 VMOVSD	(%R14,%R12,8),%XMM2

  (1075) 0x7ff36 VFMSUB231SD	%XMM0,%XMM1,%XMM2

  (1075) 0x7ff3b VMOVSD	%XMM2,(%R14,%R12,8)

  (1075) 0x7ff41 VMOVSD	(%RSI,%R10,1),%XMM2

  (1075) 0x7ff47 VFMSUB231SD	%XMM0,%XMM1,%XMM2

  (1075) 0x7ff4c VMOVSD	%XMM2,(%RSI,%R10,1)

  (1075) 0x7ff52 VFMSUB213SD	(%RBX,%R10,1),%XMM0,%XMM1

  (1075) 0x7ff58 VMOVSD	%XMM1,(%RBX,%R10,1)

  (1075) 0x7ff5e ADD	-0x48(%RBP),%R10

  (1075) 0x7ff62 DEC	%R11

  (1075) 0x7ff65 JNE	7fea0

0x7ff6b MOV	-0x40(%RBP),%RAX

0x7ff6f MOV	-0x38(%RBP),%R15

0x7ff73 ADD	-0x150(%RBP),%RBX

0x7ff7a MOV	-0xa0(%RBP),%R11

0x7ff81 INC	%R15

0x7ff84 ADD	%RAX,%R9

0x7ff87 ADD	%RAX,%RDI

0x7ff8a ADD	%RAX,%RDX

0x7ff8d CMP	-0x30(%RBP),%R15

0x7ff91 JNE	7fe70

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp: 87 - 105

--------------------------------------------------------------------------------

87:             double xcos_dxi = 2.0 * xcos(d) / dx(i);

88:             double ycos_dyj = 2.0 * ycos(d) / dy(j);

89:             double zcos_dzk = 2.0 * zcos(d) / dz(k);

[...]

95:                 + psi_lf(d, g, j, k) * xcos_dxi

96:                 + psi_fr(d, g, i, k) * ycos_dyj

97:                 + psi_bo(d, g, i, j) * zcos_dzk)

98:                 / (xcos_dxi + ycos_dyj + zcos_dzk + sigt(g, z));

99:

100:             psi(d, g, z) = psi_d_g_z;

101:

102:             /* Apply diamond-difference relationships */

103:             psi_lf(d, g, j, k) = 2.0 * psi_d_g_z - psi_lf(d, g, j, k);

104:             psi_fr(d, g, i, k) = 2.0 * psi_d_g_z - psi_fr(d, g, i, k);

105:             psi_bo(d, g, i, j) = 2.0 * psi_d_g_z - psi_bo(d, g, i, j);

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.24
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.12
Bottlenecks	P5, P6, P7,
Function	.omp_outlined..239
Source	forall.hpp:59-59
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.71
Front-end cycles	2.67
DIV/SQRT cycles	2.25
P0 cycles	2.25
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	0.50
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	16.00
Nb loads	8.00
Nb stores	1.00
Nb stack references	8.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	8.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	7.00
Stride indirect	2.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.61
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.24
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.12
Bottlenecks	P5, P6, P7,
Function	.omp_outlined..239
Source	forall.hpp:59-59
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.71
Front-end cycles	2.67
DIV/SQRT cycles	2.25
P0 cycles	2.25
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	0.50
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	16.00
Nb loads	8.00
Nb stores	1.00
Nb stack references	8.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	8.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	7.00
Stride indirect	2.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.61
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..239
Source file and lines	forall.hpp:59-59
Module	libkripke.so

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp:87-89,95-105
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.71 cycles (4.24x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 3.00 to 2.67 cycles (1.13x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 7 occurrence(s)
Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	18
nb uops	16
loop length	92
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	8

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.67 cycles
front end	2.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.25	2.25	2.00	2.00	0.50	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.25	2.25	2.00	2.00	0.50	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.67
Dispatch	3.00
Data deps.	1.00
Overall L1	3.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

22% of peak load performance is reached (21.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.67 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 7fe70

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
IMUL -0x90(%RBP),%R15	1	0	1	0	0	0	0.33	0.33	0.33	3	1
MOV -0x158(%RBP),%R10	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0.25
ADD -0x98(%RBP),%R15	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
LEA (%R10,%R15,1),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0.25
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV -0x38(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
ADD -0x150(%RBP),%RBX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
MOV -0xa0(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
INC %R15	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %RAX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %RAX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP -0x30(%RBP),%R15	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
JNE 7fe70 <.omp_outlined..239+0x7c0>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1

Function	.omp_outlined..239
Source file and lines	forall.hpp:59-59
Module	libkripke.so

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp:87-89,95-105
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.71 cycles (4.24x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 3.00 to 2.67 cycles (1.13x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 7 occurrence(s)
Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	18
nb uops	16
loop length	92
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	8

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.67 cycles
front end	2.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.25	2.25	2.00	2.00	0.50	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.25	2.25	2.00	2.00	0.50	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.67
Dispatch	3.00
Data deps.	1.00
Overall L1	3.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

22% of peak load performance is reached (21.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.67 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 7fe70

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
IMUL -0x90(%RBP),%R15	1	0	1	0	0	0	0.33	0.33	0.33	3	1
MOV -0x158(%RBP),%R10	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0.25
ADD -0x98(%RBP),%R15	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
LEA (%R10,%R15,1),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0.25
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV -0x38(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
ADD -0x150(%RBP),%RBX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
MOV -0xa0(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
INC %R15	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %RAX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %RAX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP -0x30(%RBP),%R15	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
JNE 7fe70 <.omp_outlined..239+0x7c0>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> --groups 1024 --procs 2,1,1MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/run/oneview_runs/compilers/aocc_10/oneview_run_1708510900I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1.17	-0	1.17	-0	0.88	0	0.88	0	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.15	0.01
2x2	4	1.17	2.33	2	0.09	0.01
2x4	8	1.17	4.67	4	0.04	0.01
2x8	16	0.88	7	8	0.04	0.01
2x16	32	0.88	14	16	0.02	0.01
2x32	64	1	1	32	0.01	0.01
2x64	128	1	1	64	0.01	0.01
2x96	192	1	1	96	0.01	0.01

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency