OV - - Function _ZN6Kripke12ParallelComm12getReadyListEv

	Function: _ZN6Kripke12ParallelComm12getReadyListEv	Module: libkripke.so	Source: ParallelComm.cpp:254-263 [...]	Coverage: 0.04%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp: 254 - 263

--------------------------------------------------------------------------------

254: std::vector<SdomId> ParallelComm::getReadyList(void){

255:   // build up a list of ready subdomains

256:   std::vector<SdomId> ready;

257:   for(size_t i = 0;i < queue_depends.size();++ i){

258:     if(queue_depends[i] == 0){

259:       ready.push_back(SdomId(queue_sdom_ids[i]));

260:     }

261:   }

262:   return ready;

263: }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h: 127 - 162

--------------------------------------------------------------------------------

127: 	return static_cast<_Tp*>(::operator new(__n * sizeof(_Tp)));

[...]

145: 	::operator delete(__p

[...]

162: 	{ ::new((void *)__p) _Up(std::forward<_Args>(__args)...); }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 98 - 1762

--------------------------------------------------------------------------------

98: 	: _M_start(), _M_finish(), _M_end_of_storage()

[...]

346: 	return __n != 0 ? _Tr::allocate(_M_impl, __n) : pointer();

[...]

353: 	if (__p)

[...]

919:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1046: 	return *(this->_M_impl._M_start + __n);

[...]

1758: 	if (max_size() - size() < __n)

1759: 	  __throw_length_error(__N(__s));

1760:

1761: 	const size_type __len = size() + (std::max)(size(), __n);

1762: 	return (__len < size() || __len > max_size()) ? max_size() : __len;

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_uninitialized.h: 1031 - 1031

--------------------------------------------------------------------------------

1031:       for (; __first != __last; ++__first, (void)++__cur)

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/vector.tcc: 112 - 504

--------------------------------------------------------------------------------

112: 	if (this->_M_impl._M_finish != this->_M_impl._M_end_of_storage)

113: 	  {

114: 	    _GLIBCXX_ASAN_ANNOTATE_GROW(1);

115: 	    _Alloc_traits::construct(this->_M_impl, this->_M_impl._M_finish,

116: 				     std::forward<_Args>(__args)...);

117: 	    ++this->_M_impl._M_finish;

[...]

464: 	      ++__new_finish;

[...]

502:       this->_M_impl._M_start = __new_start;

503:       this->_M_impl._M_finish = __new_finish;

504:       this->_M_impl._M_end_of_storage = __new_start + __len;

0x9ec40 PUSH	%RBP

0x9ec41 MOV	%RSP,%RBP

0x9ec44 PUSH	%R15

0x9ec46 PUSH	%R14

0x9ec48 PUSH	%R13

0x9ec4a PUSH	%R12

0x9ec4c PUSH	%RBX

0x9ec4d SUB	$0x28,%RSP

0x9ec51 VXORPS	%XMM0,%XMM0,%XMM0

0x9ec55 MOVQ	$0,0x10(%RDI)

0x9ec5d VMOVUPS	%XMM0,(%RDI)

0x9ec61 MOV	0x70(%RSI),%RCX

0x9ec65 CMP	%RCX,0x78(%RSI)

0x9ec69 JE	9ee4b

0x9ec6f XOR	%R13D,%R13D

0x9ec72 XOR	%R8D,%R8D

0x9ec75 XOR	%EAX,%EAX

0x9ec77 XOR	%R14D,%R14D

0x9ec7a MOV	%RDI,-0x38(%RBP)

0x9ec7e MOV	%RSI,-0x30(%RBP)

0x9ec82 JMP	9ecbc

0x9ec84 NOPW	%CS:(%RAX,%RAX,1)

(1359) 0x9ec90 MOV	%R9,(%R8)

(1359) 0x9ec93 ADD	$0x8,%R8

(1359) 0x9ec97 MOV	%R8,0x8(%RDI)

(1359) 0x9ec9b MOV	%R14,%R15

(1359) 0x9ec9e MOV	0x70(%RSI),%RCX

(1359) 0x9eca2 MOV	0x78(%RSI),%RDX

(1359) 0x9eca6 INC	%R13

(1359) 0x9eca9 MOV	%R15,%R14

(1359) 0x9ecac SUB	%RCX,%RDX

(1359) 0x9ecaf SAR	$0x2,%RDX

(1359) 0x9ecb3 CMP	%RDX,%R13

(1359) 0x9ecb6 JAE	9ee4b

(1359) 0x9ecbc CMPL	$0,(%RCX,%R13,4)

(1359) 0x9ecc1 JNE	9ec9b

(1359) 0x9ecc3 MOV	0x58(%RSI),%RCX

(1359) 0x9ecc7 MOVSXD	(%RCX,%R13,4),%R9

(1359) 0x9eccb CMP	%RAX,%R8

(1359) 0x9ecce JNE	9ec90

(1359) 0x9ecd0 MOV	%R8,%RBX

(1359) 0x9ecd3 SUB	%R14,%RBX

(1359) 0x9ecd6 MOV	$0x7ffffffffffffff8,%RAX

(1359) 0x9ece0 CMP	%RAX,%RBX

(1359) 0x9ece3 JE	9ee60

(1359) 0x9ece9 MOV	%RBX,%R12

(1359) 0x9ecec SAR	$0x3,%R12

(1359) 0x9ecf0 MOV	$0x1,%EAX

(1359) 0x9ecf5 MOV	$0xfffffffffffffff,%RCX

(1359) 0x9ecff CMP	$0x2,%R12

(1359) 0x9ed03 CMOVAE	%R12,%RAX

(1359) 0x9ed07 LEA	(%RAX,%R12,1),%RDX

(1359) 0x9ed0b CMP	%RCX,%RDX

(1359) 0x9ed0e CMOVA	%RCX,%RDX

(1359) 0x9ed12 ADD	%R12,%RAX

(1359) 0x9ed15 CMOVB	%RCX,%RDX

(1359) 0x9ed19 MOV	%RDX,-0x50(%RBP)

(1359) 0x9ed1d TEST	%RDX,%RDX

(1359) 0x9ed20 JE	9ed56

(1359) 0x9ed22 MOV	%R9,-0x40(%RBP)

(1359) 0x9ed26 MOV	%R8,-0x48(%RBP)

(1359) 0x9ed2a LEA	(,%RDX,8),%RDI

(1359) 0x9ed32 VZEROUPPER

(1359) 0x9ed35 CALL	a8c30 <@plt_start@+0x160>

(1359) 0x9ed3a MOV	-0x48(%RBP),%R8

(1359) 0x9ed3e MOV	-0x40(%RBP),%R9

(1359) 0x9ed42 MOV	%RAX,%R15

(1359) 0x9ed45 MOV	%R9,(%R15,%R12,8)

(1359) 0x9ed49 MOV	%R15,%R12

(1359) 0x9ed4c CMP	%R8,%R14

(1359) 0x9ed4f JNE	9ed69

(1359) 0x9ed51 JMP	9ee14

(1359) 0x9ed56 XOR	%R15D,%R15D

(1359) 0x9ed59 MOV	%R9,(%R15,%R12,8)

(1359) 0x9ed5d MOV	%R15,%R12

(1359) 0x9ed60 CMP	%R8,%R14

(1359) 0x9ed63 JE	9ee14

(1359) 0x9ed69 ADD	$-0x8,%RBX

(1359) 0x9ed6d MOV	%R15,%R12

(1359) 0x9ed70 MOV	%R14,%RAX

(1359) 0x9ed73 CMP	$0xf8,%RBX

(1359) 0x9ed7a JB	9ee00

(1359) 0x9ed80 SHR	$0x3,%RBX

(1359) 0x9ed84 XOR	%EDX,%EDX

(1359) 0x9ed86 INC	%RBX

(1359) 0x9ed89 MOV	%RBX,%RCX

(1359) 0x9ed8c AND	$-0x20,%RCX

(1359) 0x9ed90 LEA	(,%RCX,8),%RAX

(1359) 0x9ed98 LEA	(%R15,%RCX,8),%R12

(1359) 0x9ed9c NOPL	(%RAX)

  (1361) 0x9eda0 VMOVUPS	(%R14,%RDX,8),%ZMM0

  (1361) 0x9eda7 VMOVUPS	0x40(%R14,%RDX,8),%ZMM1

  (1361) 0x9edaf VMOVUPS	0x80(%R14,%RDX,8),%ZMM2

  (1361) 0x9edb7 VMOVUPS	0xc0(%R14,%RDX,8),%ZMM3

  (1361) 0x9edbf VMOVUPS	%ZMM0,(%R15,%RDX,8)

  (1361) 0x9edc6 VMOVUPS	%ZMM1,0x40(%R15,%RDX,8)

  (1361) 0x9edce VMOVUPS	%ZMM2,0x80(%R15,%RDX,8)

  (1361) 0x9edd6 VMOVUPS	%ZMM3,0xc0(%R15,%RDX,8)

  (1361) 0x9edde ADD	$0x20,%RDX

  (1361) 0x9ede2 CMP	%RDX,%RCX

  (1361) 0x9ede5 JNE	9eda0

(1359) 0x9ede7 CMP	%RCX,%RBX

(1359) 0x9edea JNE	9edf2

(1359) 0x9edec ADD	$0x8,%R12

(1359) 0x9edf0 JMP	9ee1d

(1359) 0x9edf2 ADD	%R14,%RAX

(1359) 0x9edf5 NOPW	%CS:(%RAX,%RAX,1)

  (1360) 0x9ee00 MOV	(%RAX),%RCX

  (1360) 0x9ee03 ADD	$0x8,%RAX

  (1360) 0x9ee07 MOV	%RCX,(%R12)

  (1360) 0x9ee0b ADD	$0x8,%R12

  (1360) 0x9ee0f CMP	%R8,%RAX

  (1360) 0x9ee12 JNE	9ee00

(1359) 0x9ee14 ADD	$0x8,%R12

(1359) 0x9ee18 TEST	%R14,%R14

(1359) 0x9ee1b JE	9ee28

(1359) 0x9ee1d MOV	%R14,%RDI

(1359) 0x9ee20 VZEROUPPER

(1359) 0x9ee23 CALL	a8b10 <@plt_start@+0x40>

(1359) 0x9ee28 MOV	-0x50(%RBP),%RAX

(1359) 0x9ee2c MOV	-0x38(%RBP),%RDI

(1359) 0x9ee30 MOV	-0x30(%RBP),%RSI

(1359) 0x9ee34 MOV	%R12,%R8

(1359) 0x9ee37 LEA	(%R15,%RAX,8),%RAX

(1359) 0x9ee3b MOV	%R15,(%RDI)

(1359) 0x9ee3e MOV	%R12,0x8(%RDI)

(1359) 0x9ee42 MOV	%RAX,0x10(%RDI)

(1359) 0x9ee46 JMP	9ec9e

0x9ee4b MOV	%RDI,%RAX

0x9ee4e ADD	$0x28,%RSP

0x9ee52 POP	%RBX

0x9ee53 POP	%R12

0x9ee55 POP	%R13

0x9ee57 POP	%R14

0x9ee59 POP	%R15

0x9ee5b POP	%RBP

0x9ee5c VZEROUPPER

0x9ee5f RET

0x9ee60 LEA	-0x8c275(%RIP),%RDI

0x9ee67 VZEROUPPER

0x9ee6a CALL	a8bf0 <@plt_start@+0x120>

0x9ee6f JMP	9ee71

0x9ee71 MOV	%RAX,%RBX

0x9ee74 TEST	%R14,%R14

0x9ee77 JE	9ee81

0x9ee79 MOV	%R14,%RDI

0x9ee7c CALL	a8b10 <@plt_start@+0x40>

0x9ee81 MOV	%RBX,%RDI

0x9ee84 CALL	a90e0 <@plt_start@+0x610>

0x9ee89 INT	$0x3

0x9ee8a INT	$0x3

0x9ee8b INT	$0x3

0x9ee8c INT	$0x3

0x9ee8d INT	$0x3

0x9ee8e INT	$0x3

0x9ee8f INT	$0x3

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	ParallelComm.cpp:254-263
Module	libkripke.so

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp:254-263
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:127,145,162
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:98,346,353,919,1046,1758-1762
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_uninitialized.h:1031
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/vector.tcc:112-117,464,502-504

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.50 to 1.17 cycles (6.43x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 7.50 to 0.61 cycles (12.31x speedup).

Details

28% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
25% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
42% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 3 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	50
nb uops	45
loop length	149
used x86 registers	12
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.50 cycles
front end	7.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.00	1.75	1.75	1.50	4.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.50	0.50
cycles	4.00	1.75	1.75	1.50	4.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.50
Dispatch	4.00
Overall L1	7.50

Vectorization ratios

INT

all	16%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	28%
load	0%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	42%

Vector efficiency ratios

INT

all	13%
load	12%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	14%
load	12%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.50 cycles. At this rate:

2% of peak load performance is reached (2.13 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (5.33 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 7.50 to 4.00 cycles (1.88x speedup).

ASM code

In the binary file, the address of the function is: 9ec40

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVQ $0,0x10(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
VMOVUPS %XMM0,(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MOV 0x70(%RSI),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CMP %RCX,0x78(%RSI)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JE 9ee4b <_ZN6Kripke12ParallelComm12getReadyListEv+0x20b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
MOV %RDI,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RSI,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JMP 9ecbc <_ZN6Kripke12ParallelComm12getReadyListEv+0x7c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LEA -0x8c275(%RIP),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
CALL a8bf0 <@plt_start@+0x120>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
JMP 9ee71 <_ZN6Kripke12ParallelComm12getReadyListEv+0x231>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
TEST %R14,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 9ee81 <_ZN6Kripke12ParallelComm12getReadyListEv+0x241>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL a8b10 <@plt_start@+0x40>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL a90e0 <@plt_start@+0x610>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3

Source file and lines	ParallelComm.cpp:254-263
Module	libkripke.so

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp:254-263
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:127,145,162
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:98,346,353,919,1046,1758-1762
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_uninitialized.h:1031
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/vector.tcc:112-117,464,502-504

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.50 to 1.17 cycles (6.43x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

28% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
25% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
42% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 3 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	50
nb uops	45
loop length	149
used x86 registers	12
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.50 cycles
front end	7.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.00	1.75	1.75	1.50	4.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.50	0.50
cycles	4.00	1.75	1.75	1.50	4.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.50
Dispatch	4.00
Overall L1	7.50

Vectorization ratios

INT

all	16%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	28%
load	0%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	42%

Vector efficiency ratios

INT

all	13%
load	12%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	14%
load	12%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.50 cycles. At this rate:

2% of peak load performance is reached (2.13 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (5.33 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 9ec40

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVQ $0,0x10(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
VMOVUPS %XMM0,(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MOV 0x70(%RSI),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CMP %RCX,0x78(%RSI)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JE 9ee4b <_ZN6Kripke12ParallelComm12getReadyListEv+0x20b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
MOV %RDI,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RSI,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JMP 9ecbc <_ZN6Kripke12ParallelComm12getReadyListEv+0x7c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LEA -0x8c275(%RIP),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
CALL a8bf0 <@plt_start@+0x120>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
JMP 9ee71 <_ZN6Kripke12ParallelComm12getReadyListEv+0x231>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
TEST %R14,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 9ee81 <_ZN6Kripke12ParallelComm12getReadyListEv+0x241>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL a8b10 <@plt_start@+0x40>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL a90e0 <@plt_start@+0x610>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> --groups 1024 --procs 2,1,1MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/run/oneview_runs/compilers/aocc_10/oneview_run_1708510900I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1.43	0	3.58	0	5.38	-0	1	0	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	1	1	1	1	0.86	0.04
2x2	1	1.43	2.87	2	0.6	0.03
2x4	1	3.58	14.33	4	0.27	0.01
2x8	1	5.38	43	8	0.1	0
2x16	2	1	1	16	0.04	0
2x32	2	1	1	32	0.07	0
2x64	1	1	1	64	0.17	0
2x96	1	1	1	96	0.31	0.01

Name	Coverage (%)	Time (s)
▼_ZN6Kripke12ParallelComm12getReadyListEv–	0.04	0.43
▼Loop 1359 - vector.tcc:112-504 - libkripke.so–	0.02	0.5
○Loop 1360 - stl_uninitialized.h:1031-1031 - libkripke.so	0	0
○Loop 1361 - new_allocator.h:162-162 - libkripke.so	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency