OV - exec - Loop 35

	Loop Id: 35	Module: exec	Source: forall.hpp:59-59 [...]	Coverage: 0.03%

0x24f940 ADD	-0xb0(%RBP),%RDX

0x24f947 ADD	-0x98(%RBP),%R12

0x24f94e INC	%R11

0x24f951 CMP	%R8,%R11

0x24f954 JE	24f840

0x24f95a MOV	-0x50(%RBP),%RAX

0x24f95e LEA	(%R11,%RAX,1),%R13

0x24f962 IMUL	-0xa0(%RBP),%R13

0x24f96a ADD	-0x150(%RBP),%R13

0x24f971 CMPB	$0,-0x29(%RBP)

0x24f975 JE	24f9c0

0x24f977 XOR	%ESI,%ESI

0x24f979 MOV	-0xa8(%RBP),%RAX

0x24f980 MOV	%R15,%R9

0x24f983 SUB	%RSI,%R9

0x24f986 ADD	%RSI,%RAX

0x24f989 ADD	%R12,%RSI

0x24f98c LEA	(%RBX,%RAX,8),%RCX

0x24f990 MOV	-0x38(%RBP),%RAX

0x24f994 LEA	(%RAX,%RSI,8),%RSI

0x24f998 XOR	%EAX,%EAX

0x24f99a NOPW	(%RAX,%RAX,1)

  (33) 0x24f9a0 VMOVSD	(%R14,%R13,8),%XMM0

  (33) 0x24f9a6 VMOVSD	(%RSI,%RAX,8),%XMM1

  (33) 0x24f9ab VFMADD213SD	(%RCX,%RAX,8),%XMM0,%XMM1

  (33) 0x24f9b1 VMOVSD	%XMM1,(%RCX,%RAX,8)

  (33) 0x24f9b6 INC	%RAX

  (33) 0x24f9b9 CMP	%RAX,%R9

  (33) 0x24f9bc JNE	24f9a0

0x24f9be JMP	24f940

0x24f9c0 MOV	-0xb0(%RBP),%RSI

0x24f9c7 MOV	-0x120(%RBP),%R8

0x24f9ce MOV	-0x128(%RBP),%RCX

0x24f9d5 MOV	-0x148(%RBP),%RAX

0x24f9dc MOV	-0x138(%RBP),%R15

0x24f9e3 IMUL	%R11,%RSI

0x24f9e7 LEA	(%RCX,%R11,8),%RCX

0x24f9eb LEA	(%RAX,%R11,8),%RAX

0x24f9ef ADD	%R14,%RCX

0x24f9f2 ADD	%R14,%RAX

0x24f9f5 LEA	(%R8,%RSI,1),%R9

0x24f9f9 MOV	-0x38(%RBP),%R8

0x24f9fd ADD	-0x140(%RBP),%RSI

0x24fa04 ADD	%R8,%R9

0x24fa07 ADD	%R8,%RSI

0x24fa0a CMP	%RCX,%R15

0x24fa0d MOV	-0x130(%RBP),%RCX

0x24fa14 SETB	%R8B

0x24fa18 CMP	%RCX,%RAX

0x24fa1b SETB	%BL

0x24fa1e CMP	%RSI,%R15

0x24fa21 SETB	%AL

0x24fa24 CMP	%RCX,%R9

0x24fa27 SETB	%CL

0x24fa2a TEST	%BL,%R8B

0x24fa2d JNE	24fa5b

0x24fa2f MOV	-0x90(%RBP),%R8

0x24fa36 MOV	-0x88(%RBP),%RBX

0x24fa3d MOV	-0x80(%RBP),%R15

0x24fa41 AND	%CL,%AL

0x24fa43 MOV	$0,%ESI

0x24fa48 JNE	24f979

0x24fa4e CMP	$0x20,%R15

0x24fa52 JAE	24fa72

0x24fa54 XOR	%EAX,%EAX

0x24fa56 JMP	24faff

0x24fa5b MOV	-0x90(%RBP),%R8

0x24fa62 MOV	-0x88(%RBP),%RBX

0x24fa69 MOV	-0x80(%RBP),%R15

0x24fa6d JMP	24f977

0x24fa72 VBROADCASTSD	(%R14,%R13,8),%ZMM0

0x24fa79 XOR	%R9D,%R9D

0x24fa7c NOPL	(%RAX)

  (36) 0x24fa80 VMOVUPD	-0xc0(%RDX,%R9,8),%ZMM1

  (36) 0x24fa88 VMOVUPD	-0x80(%RDX,%R9,8),%ZMM2

  (36) 0x24fa90 VMOVUPD	-0x40(%RDX,%R9,8),%ZMM3

  (36) 0x24fa98 VMOVUPD	(%RDX,%R9,8),%ZMM4

  (36) 0x24fa9f VFMADD213PD	-0xc0(%R10,%R9,8),%ZMM0,%ZMM1

  (36) 0x24faa7 VFMADD213PD	-0x80(%R10,%R9,8),%ZMM0,%ZMM2

  (36) 0x24faaf VFMADD213PD	-0x40(%R10,%R9,8),%ZMM0,%ZMM3

  (36) 0x24fab7 VFMADD213PD	(%R10,%R9,8),%ZMM0,%ZMM4

  (36) 0x24fabe VMOVUPD	%ZMM1,-0xc0(%R10,%R9,8)

  (36) 0x24fac6 VMOVUPD	%ZMM2,-0x80(%R10,%R9,8)

  (36) 0x24face VMOVUPD	%ZMM3,-0x40(%R10,%R9,8)

  (36) 0x24fad6 VMOVUPD	%ZMM4,(%R10,%R9,8)

  (36) 0x24fadd ADD	$0x20,%R9

  (36) 0x24fae1 CMP	%R9,%RDI

  (36) 0x24fae4 JNE	24fa80

0x24fae6 CMP	%RDI,%R15

0x24fae9 JE	24f940

0x24faef MOV	%RDI,%RAX

0x24faf2 MOV	%RDI,%RSI

0x24faf5 TEST	$0x1c,%R15B

0x24faf9 JE	24f979

0x24faff MOV	-0xa8(%RBP),%RCX

0x24fb06 MOV	-0x38(%RBP),%R9

0x24fb0a VBROADCASTSD	(%R14,%R13,8),%YMM0

0x24fb10 ADD	%RAX,%RCX

0x24fb13 LEA	(%RBX,%RCX,8),%RSI

0x24fb17 LEA	(%RAX,%R12,1),%RCX

0x24fb1b LEA	(%R9,%RCX,8),%RCX

0x24fb1f MOV	-0x78(%RBP),%R9

0x24fb23 SUB	%RAX,%R9

0x24fb26 XOR	%EAX,%EAX

0x24fb28 NOPL	(%RAX,%RAX,1)

  (37) 0x24fb30 VMOVUPD	(%RCX,%RAX,8),%YMM1

  (37) 0x24fb35 VFMADD213PD	(%RSI,%RAX,8),%YMM0,%YMM1

  (37) 0x24fb3b VMOVUPD	%YMM1,(%RSI,%RAX,8)

  (37) 0x24fb40 ADD	$0x4,%RAX

  (37) 0x24fb44 CMP	%RAX,%R9

  (37) 0x24fb47 JNE	24fb30

0x24fb49 MOV	-0x78(%RBP),%RAX

0x24fb4d MOV	%RAX,%RSI

0x24fb50 CMP	%RAX,%R15

0x24fb53 JE	24f940

0x24fb59 JMP	24f979

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/LTimes.cpp: 62 - 62

--------------------------------------------------------------------------------

62:            phi(nm,g,z) += ell(nm, d) * psi(d, g, z);

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

Path /

Metric	Value
CQA speedup if no scalar integer	3.54
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.27
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	micro-operation queue,
Function	.omp_outlined.#0x24f610
Source	forall.hpp:59-59
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.17
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	14.17
CQA cycles if fully vectorized	2.26
Front-end cycles	14.17
DIV/SQRT cycles	12.00
P0 cycles	12.00
P1 cycles	11.75
P2 cycles	11.75
P3 cycles	6.50
P4 cycles	9.33
P5 cycles	9.33
P6 cycles	9.33
P7 cycles	0.00
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	88.00
Nb uops	85.00
Nb loads	28.00
Nb stores	0.00
Nb stack references	18.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.32
Bytes prefetched	0.00
Bytes loaded	217.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.51
Vector-efficiency ratio load	9.77
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.41

Metric	Value
CQA speedup if no scalar integer	3.54
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.27
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	micro-operation queue,
Function	.omp_outlined.#0x24f610
Source	forall.hpp:59-59
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.17
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	14.17
CQA cycles if fully vectorized	2.26
Front-end cycles	14.17
DIV/SQRT cycles	12.00
P0 cycles	12.00
P1 cycles	11.75
P2 cycles	11.75
P3 cycles	6.50
P4 cycles	9.33
P5 cycles	9.33
P6 cycles	9.33
P7 cycles	0.00
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	88.00
Nb uops	85.00
Nb loads	28.00
Nb stores	0.00
Nb stack references	18.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.32
Bytes prefetched	0.00
Bytes loaded	217.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.51
Vector-efficiency ratio load	9.77
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.41

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined.#0x24f610
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/LTimes.cpp:62
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=9
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 9 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.17 to 4.00 cycles (3.54x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 14.17 to 2.26 cycles (6.27x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 217 bytes.

General properties

nb instructions	88
nb uops	85
loop length	385
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	1
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.17 cycles
front end	14.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	12.00	12.00	11.75	11.75	6.50	9.33	9.33	9.33	0.00	0.50	0.50	0.00	0.00	0.00
cycles	12.00	12.00	11.75	11.75	6.50	9.33	9.33	9.33	0.00	0.50	0.50	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.17
Dispatch	12.00
Overall L1	14.17

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	7%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	9%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.17 cycles. At this rate:

15% of peak load performance is reached (15.32 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 14.17 to 12.00 cycles (1.18x speedup).

ASM code

In the binary file, the address of the loop is: 24f95a

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	Latency	Recip. throughput
ADD -0xb0(%RBP),%RDX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
ADD -0x98(%RBP),%R12	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
INC %R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP %R8,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 24f840 <.omp_outlined.+0x230>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV -0x50(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (%R11,%RAX,1),%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
IMUL -0xa0(%RBP),%R13	1	0	1	0	0	0	0.33	0.33	0.33	0	0	3	1
ADD -0x150(%RBP),%R13	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
CMPB $0,-0x29(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
JE 24f9c0 <.omp_outlined.+0x3b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.25
MOV -0xa8(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R15,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB %RSI,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %RSI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %R12,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RBX,%RAX,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (%RAX,%RSI,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
JMP 24f940 <.omp_outlined.+0x330>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
MOV -0xb0(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x120(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x128(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x148(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x138(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
IMUL %R11,%RSI	1	0	1	0	0	0	0	0	0	0	0	3	1
LEA (%RCX,%R11,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RAX,%R11,8),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %R14,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %R14,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%R8,%RSI,1),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV -0x38(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
ADD -0x140(%RBP),%RSI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %R8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP %RCX,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV -0x130(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
SETB %R8B	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50
CMP %RCX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SETB %BL	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50
CMP %RSI,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SETB %AL	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50
CMP %RCX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SETB %CL	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50
TEST %BL,%R8B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 24fa5b <.omp_outlined.+0x44b>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV -0x90(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x88(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x80(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
AND %CL,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV $0,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 24f979 <.omp_outlined.+0x369>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
CMP $0x20,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JAE 24fa72 <.omp_outlined.+0x462>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 24faff <.omp_outlined.+0x4ef>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
MOV -0x90(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x88(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x80(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
JMP 24f977 <.omp_outlined.+0x367>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
VBROADCASTSD (%R14,%R13,8),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	5	1
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
CMP %RDI,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 24f940 <.omp_outlined.+0x330>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
TEST $0x1c,%R15B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 24f979 <.omp_outlined.+0x369>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV -0xa8(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x38(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
VBROADCASTSD (%R14,%R13,8),%YMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
ADD %RAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RBX,%RCX,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RAX,%R12,1),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%R9,%RCX,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV -0x78(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
SUB %RAX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV -0x78(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %RAX,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 24f940 <.omp_outlined.+0x330>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
JMP 24f979 <.omp_outlined.+0x369>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1

Function	.omp_outlined.#0x24f610
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/LTimes.cpp:62
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=9
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.17 to 4.00 cycles (3.54x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 217 bytes.

General properties

nb instructions	88
nb uops	85
loop length	385
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	1
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.17 cycles
front end	14.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	12.00	12.00	11.75	11.75	6.50	9.33	9.33	9.33	0.00	0.50	0.50	0.00	0.00	0.00
cycles	12.00	12.00	11.75	11.75	6.50	9.33	9.33	9.33	0.00	0.50	0.50	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.17
Dispatch	12.00
Overall L1	14.17

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	7%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	9%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.17 cycles. At this rate:

15% of peak load performance is reached (15.32 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 24f95a

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	Latency	Recip. throughput
ADD -0xb0(%RBP),%RDX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
ADD -0x98(%RBP),%R12	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
INC %R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP %R8,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 24f840 <.omp_outlined.+0x230>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV -0x50(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (%R11,%RAX,1),%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
IMUL -0xa0(%RBP),%R13	1	0	1	0	0	0	0.33	0.33	0.33	0	0	3	1
ADD -0x150(%RBP),%R13	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
CMPB $0,-0x29(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
JE 24f9c0 <.omp_outlined.+0x3b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.25
MOV -0xa8(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R15,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB %RSI,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %RSI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %R12,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RBX,%RAX,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (%RAX,%RSI,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
JMP 24f940 <.omp_outlined.+0x330>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
MOV -0xb0(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x120(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x128(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x148(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x138(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
IMUL %R11,%RSI	1	0	1	0	0	0	0	0	0	0	0	3	1
LEA (%RCX,%R11,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RAX,%R11,8),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %R14,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %R14,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%R8,%RSI,1),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV -0x38(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
ADD -0x140(%RBP),%RSI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %R8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP %RCX,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV -0x130(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
SETB %R8B	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50
CMP %RCX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SETB %BL	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50
CMP %RSI,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SETB %AL	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50
CMP %RCX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SETB %CL	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50
TEST %BL,%R8B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 24fa5b <.omp_outlined.+0x44b>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV -0x90(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x88(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x80(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
AND %CL,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV $0,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 24f979 <.omp_outlined.+0x369>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
CMP $0x20,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JAE 24fa72 <.omp_outlined.+0x462>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 24faff <.omp_outlined.+0x4ef>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
MOV -0x90(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x88(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x80(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
JMP 24f977 <.omp_outlined.+0x367>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
VBROADCASTSD (%R14,%R13,8),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	5	1
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
CMP %RDI,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 24f940 <.omp_outlined.+0x330>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
TEST $0x1c,%R15B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 24f979 <.omp_outlined.+0x369>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV -0xa8(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x38(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
VBROADCASTSD (%R14,%R13,8),%YMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
ADD %RAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RBX,%RCX,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RAX,%R12,1),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%R9,%RCX,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV -0x78(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
SUB %RAX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV -0x78(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %RAX,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 24f940 <.omp_outlined.+0x330>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
JMP 24f979 <.omp_outlined.+0x369>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code