OV - exec - Loop 26

0x264190 VMOVUPD	-0xc0(%RDX,%R8,8),%ZMM1    [2]

0x264198 VMOVUPD	-0x80(%RDX,%R8,8),%ZMM2    [2]

0x2641a0 VMOVUPD	-0x40(%RDX,%R8,8),%ZMM3    [2]

0x2641a8 VMOVUPD	(%RDX,%R8,8),%ZMM4    [2]

0x2641af VFMADD213PD	-0xc0(%RAX,%R8,8),%ZMM0,%ZMM1    [1]

0x2641b7 VFMADD213PD	-0x80(%RAX,%R8,8),%ZMM0,%ZMM2    [1]

0x2641bf VFMADD213PD	-0x40(%RAX,%R8,8),%ZMM0,%ZMM3    [1]

0x2641c7 VFMADD213PD	(%RAX,%R8,8),%ZMM0,%ZMM4    [1]

0x2641ce VMOVUPD	%ZMM1,-0xc0(%RAX,%R8,8)    [1]

0x2641d6 VMOVUPD	%ZMM2,-0x80(%RAX,%R8,8)    [1]

0x2641de VMOVUPD	%ZMM3,-0x40(%RAX,%R8,8)    [1]

0x2641e6 VMOVUPD	%ZMM4,(%RAX,%R8,8)    [1]

0x2641ed ADD	$0x20,%R8

0x2641f1 CMP	%R8,%RSI

0x2641f4 JNE	264190

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp: 57 - 57

--------------------------------------------------------------------------------

57:             rhs(d,g,z) += ell_plus(d, nm) * phi_out(nm, g, z);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.67
Bottlenecks	P5, P6, P7,
Function	.omp_outlined.#0x263d30
Source	forall.hpp:59-59,LPlusTimes.cpp:57-57
Source loop unroll info	unrolled by 32
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	32
CQA cycles	6.67
CQA cycles if no scalar integer	6.67
CQA cycles if FP arith vectorized	6.67
CQA cycles if fully vectorized	6.67
Front-end cycles	3.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	6.67
P5 cycles	6.67
P6 cycles	6.67
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	15.00
Nb uops	18.00
Nb loads	8.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	9.60
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	32.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	115.20
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.67
Bottlenecks	P5, P6, P7,
Function	.omp_outlined.#0x263d30
Source	forall.hpp:59-59,LPlusTimes.cpp:57-57
Source loop unroll info	unrolled by 32
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	32
CQA cycles	6.67
CQA cycles if no scalar integer	6.67
CQA cycles if FP arith vectorized	6.67
CQA cycles if fully vectorized	6.67
Front-end cycles	3.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	6.67
P5 cycles	6.67
P6 cycles	6.67
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	15.00
Nb uops	18.00
Nb loads	8.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	9.60
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	32.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	115.20
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined.#0x263d30
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp:57

It is main loop of related source loop which is unrolled by 32 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 6.67 to 4.00 cycles (1.67x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 32 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 4 occurrences

Type of elements and instruction set

4 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

32: addition or subtraction (all inside FMA instructions)
32: multiply (all inside FMA instructions)

The binary loop is loading 512 bytes (64 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	15
nb uops	18
loop length	102
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	5
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.00 cycles
front end	3.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	4.00	4.00	4.00	2.00	2.00	0.00	0.00	4.00	4.00
cycles	0.50	0.50	0.25	0.25	0.50	6.67	6.67	6.67	4.00	4.00	0.00	0.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.00
Dispatch	6.67
Data deps.	1.00
Overall L1	6.67

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.67 cycles. At this rate:

80% of peak load performance is reached (76.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
60% of peak store performance is reached (38.40 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 264190

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
VMOVUPD -0xc0(%RDX,%R8,8),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD -0x80(%RDX,%R8,8),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD -0x40(%RDX,%R8,8),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD (%RDX,%R8,8),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFMADD213PD -0xc0(%RAX,%R8,8),%ZMM0,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VFMADD213PD -0x80(%RAX,%R8,8),%ZMM0,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VFMADD213PD -0x40(%RAX,%R8,8),%ZMM0,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VFMADD213PD (%RAX,%R8,8),%ZMM0,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VMOVUPD %ZMM1,-0xc0(%RAX,%R8,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD %ZMM2,-0x80(%RAX,%R8,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD %ZMM3,-0x40(%RAX,%R8,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD %ZMM4,(%RAX,%R8,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x20,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 264190 <.omp_outlined.+0x460>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Function	.omp_outlined.#0x263d30
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp:57

It is main loop of related source loop which is unrolled by 32 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 6.67 to 4.00 cycles (1.67x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 32 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 4 occurrences

Type of elements and instruction set

4 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

32: addition or subtraction (all inside FMA instructions)
32: multiply (all inside FMA instructions)

The binary loop is loading 512 bytes (64 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	15
nb uops	18
loop length	102
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	5
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.00 cycles
front end	3.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	4.00	4.00	4.00	2.00	2.00	0.00	0.00	4.00	4.00
cycles	0.50	0.50	0.25	0.25	0.50	6.67	6.67	6.67	4.00	4.00	0.00	0.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.00
Dispatch	6.67
Data deps.	1.00
Overall L1	6.67

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.67 cycles. At this rate:

80% of peak load performance is reached (76.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
60% of peak store performance is reached (38.40 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 264190

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
VMOVUPD -0xc0(%RDX,%R8,8),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD -0x80(%RDX,%R8,8),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD -0x40(%RDX,%R8,8),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD (%RDX,%R8,8),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFMADD213PD -0xc0(%RAX,%R8,8),%ZMM0,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VFMADD213PD -0x80(%RAX,%R8,8),%ZMM0,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VFMADD213PD -0x40(%RAX,%R8,8),%ZMM0,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VFMADD213PD (%RAX,%R8,8),%ZMM0,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VMOVUPD %ZMM1,-0xc0(%RAX,%R8,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD %ZMM2,-0x80(%RAX,%R8,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD %ZMM3,-0x40(%RAX,%R8,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD %ZMM4,(%RAX,%R8,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x20,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 264190 <.omp_outlined.+0x460>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code