OV - exec - Loop 901 - libkripke.so

	Loop Id: 901	Module: libkripke.so	Source: forall.hpp:59-59 [...]	Coverage: 0.01%

0x5b6c0 XOR	%EAX,%EAX

0x5b6c2 TEST	%RDI,%RDI

0x5b6c5 JLE	5b86f

0x5b6cb MOV	%RDI,%R15

0x5b6ce AND	$0x7,%R15D

0x5b6d2 JE	5b7ad

0x5b6d8 CMP	$0x1,%R15

0x5b6dc JE	5b78d

0x5b6e2 CMP	$0x2,%R15

0x5b6e6 JE	5b776

0x5b6ec CMP	$0x3,%R15

0x5b6f0 JE	5b75f

0x5b6f2 CMP	$0x4,%R15

0x5b6f6 JE	5b748

0x5b6f8 CMP	$0x5,%R15

0x5b6fc JE	5b731

0x5b6fe CMP	$0x6,%R15

0x5b702 JE	5b71a

0x5b704 MOV	$0x1,%EAX

0x5b709 VMOVSD	(%RSI),%XMM0

0x5b70d VMOVSD	(%RBX),%XMM7

0x5b711 VFMADD132SD	(%RCX),%XMM7,%XMM0

0x5b716 VMOVSD	%XMM0,(%RBX)

0x5b71a VMOVSD	(%RBX,%RAX,8),%XMM2

0x5b71f VMOVSD	(%RSI),%XMM1

0x5b723 VFMADD132SD	(%RCX,%RAX,8),%XMM2,%XMM1

0x5b729 VMOVSD	%XMM1,(%RBX,%RAX,8)

0x5b72e INC	%RAX

0x5b731 VMOVSD	(%RBX,%RAX,8),%XMM6

0x5b736 VMOVSD	(%RSI),%XMM3

0x5b73a VFMADD132SD	(%RCX,%RAX,8),%XMM6,%XMM3

0x5b740 VMOVSD	%XMM3,(%RBX,%RAX,8)

0x5b745 INC	%RAX

0x5b748 VMOVSD	(%RBX,%RAX,8),%XMM5

0x5b74d VMOVSD	(%RSI),%XMM4

0x5b751 VFMADD132SD	(%RCX,%RAX,8),%XMM5,%XMM4

0x5b757 VMOVSD	%XMM4,(%RBX,%RAX,8)

0x5b75c INC	%RAX

0x5b75f VMOVSD	(%RBX,%RAX,8),%XMM9

0x5b764 VMOVSD	(%RSI),%XMM8

0x5b768 VFMADD132SD	(%RCX,%RAX,8),%XMM9,%XMM8

0x5b76e VMOVSD	%XMM8,(%RBX,%RAX,8)

0x5b773 INC	%RAX

0x5b776 VMOVSD	(%RBX,%RAX,8),%XMM11

0x5b77b VMOVSD	(%RSI),%XMM10

0x5b77f VFMADD132SD	(%RCX,%RAX,8),%XMM11,%XMM10

0x5b785 VMOVSD	%XMM10,(%RBX,%RAX,8)

0x5b78a INC	%RAX

0x5b78d VMOVSD	(%RBX,%RAX,8),%XMM13

0x5b792 VMOVSD	(%RSI),%XMM12

0x5b796 VFMADD132SD	(%RCX,%RAX,8),%XMM13,%XMM12

0x5b79c VMOVSD	%XMM12,(%RBX,%RAX,8)

0x5b7a1 INC	%RAX

0x5b7a4 CMP	%RAX,%RDI

0x5b7a7 JE	5b86f

  (902) 0x5b7ad VMOVSD	(%RSI),%XMM14

  (902) 0x5b7b1 VMOVSD	(%RBX,%RAX,8),%XMM15

  (902) 0x5b7b6 VMOVSD	0x8(%RBX,%RAX,8),%XMM7

  (902) 0x5b7bc VFMADD132SD	(%RCX,%RAX,8),%XMM15,%XMM14

  (902) 0x5b7c2 VMOVSD	0x10(%RBX,%RAX,8),%XMM2

  (902) 0x5b7c8 VMOVSD	%XMM14,(%RBX,%RAX,8)

  (902) 0x5b7cd VMOVSD	0x18(%RBX,%RAX,8),%XMM6

  (902) 0x5b7d3 VMOVSD	(%RSI),%XMM0

  (902) 0x5b7d7 VMOVSD	0x20(%RBX,%RAX,8),%XMM5

  (902) 0x5b7dd VFMADD132SD	0x8(%RCX,%RAX,8),%XMM7,%XMM0

  (902) 0x5b7e4 VMOVSD	0x28(%RBX,%RAX,8),%XMM9

  (902) 0x5b7ea VMOVSD	%XMM0,0x8(%RBX,%RAX,8)

  (902) 0x5b7f0 VMOVSD	0x30(%RBX,%RAX,8),%XMM11

  (902) 0x5b7f6 VMOVSD	(%RSI),%XMM1

  (902) 0x5b7fa VMOVSD	0x38(%RBX,%RAX,8),%XMM13

  (902) 0x5b800 VFMADD132SD	0x10(%RCX,%RAX,8),%XMM2,%XMM1

  (902) 0x5b807 VMOVSD	%XMM1,0x10(%RBX,%RAX,8)

  (902) 0x5b80d VMOVSD	(%RSI),%XMM3

  (902) 0x5b811 VFMADD132SD	0x18(%RCX,%RAX,8),%XMM6,%XMM3

  (902) 0x5b818 VMOVSD	%XMM3,0x18(%RBX,%RAX,8)

  (902) 0x5b81e VMOVSD	(%RSI),%XMM4

  (902) 0x5b822 VFMADD132SD	0x20(%RCX,%RAX,8),%XMM5,%XMM4

  (902) 0x5b829 VMOVSD	%XMM4,0x20(%RBX,%RAX,8)

  (902) 0x5b82f VMOVSD	(%RSI),%XMM8

  (902) 0x5b833 VFMADD132SD	0x28(%RCX,%RAX,8),%XMM9,%XMM8

  (902) 0x5b83a VMOVSD	%XMM8,0x28(%RBX,%RAX,8)

  (902) 0x5b840 VMOVSD	(%RSI),%XMM10

  (902) 0x5b844 VFMADD132SD	0x30(%RCX,%RAX,8),%XMM11,%XMM10

  (902) 0x5b84b VMOVSD	%XMM10,0x30(%RBX,%RAX,8)

  (902) 0x5b851 VMOVSD	(%RSI),%XMM12

  (902) 0x5b855 VFMADD132SD	0x38(%RCX,%RAX,8),%XMM13,%XMM12

  (902) 0x5b85c VMOVSD	%XMM12,0x38(%RBX,%RAX,8)

  (902) 0x5b862 ADD	$0x8,%RAX

  (902) 0x5b866 CMP	%RAX,%RDI

  (902) 0x5b869 JNE	5b7ad

0x5b86f INC	%RDX

0x5b872 ADD	$0x8,%RSI

0x5b876 ADD	%R11,%RCX

0x5b879 CMP	%R10,%RDX

0x5b87c JNE	5b6c0

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp: 57 - 57

--------------------------------------------------------------------------------

57:             rhs(d,g,z) += ell_plus(d, nm) * phi_out(nm, g, z);

Path /

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	1.05
CQA speedup if fully vectorized	4.82
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	micro-operation queue,
Function	_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0
Source	forall.hpp:59-59,LPlusTimes.cpp:57-57
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.83
CQA cycles if no scalar integer	9.33
CQA cycles if FP arith vectorized	9.33
CQA cycles if fully vectorized	2.04
Front-end cycles	9.83
DIV/SQRT cycles	6.00
P0 cycles	6.00
P1 cycles	6.00
P2 cycles	6.00
P3 cycles	5.00
P4 cycles	9.33
P5 cycles	9.33
P6 cycles	9.33
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	3.50
P12 cycles	3.50
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	59.00
Nb loads	21.00
Nb stores	7.00
Nb stack references	0.00
FLOP/cycle	1.42
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	7.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.78
Bytes prefetched	0.00
Bytes loaded	168.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.34
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.88

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	1.05
CQA speedup if fully vectorized	4.82
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	micro-operation queue,
Function	_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0
Source	forall.hpp:59-59,LPlusTimes.cpp:57-57
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.83
CQA cycles if no scalar integer	9.33
CQA cycles if FP arith vectorized	9.33
CQA cycles if fully vectorized	2.04
Front-end cycles	9.83
DIV/SQRT cycles	6.00
P0 cycles	6.00
P1 cycles	6.00
P2 cycles	6.00
P3 cycles	5.00
P4 cycles	9.33
P5 cycles	9.33
P6 cycles	9.33
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	3.50
P12 cycles	3.50
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	59.00
Nb loads	21.00
Nb stores	7.00
Nb stack references	0.00
FLOP/cycle	1.42
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	7.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.78
Bytes prefetched	0.00
Bytes loaded	168.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.34
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.88

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0
Source file and lines	forall.hpp:59-59
Module	libkripke.so

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp:57

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 16 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.83 to 9.33 cycles (1.05x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 9.83 to 2.04 cycles (4.82x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 7 FMA (fused multiply-add) operations.

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 14 FP arithmetical operations:

7: addition or subtraction (all inside FMA instructions)
7: multiply (all inside FMA instructions)

The binary loop is loading 168 bytes (21 double precision FP elements). The binary loop is storing 56 bytes (7 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	60
nb uops	59
loop length	256
used x86 registers	9
used mmx registers	0
used xmm registers	14
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.83 cycles
front end	9.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.00	6.00	6.00	6.00	5.00	9.33	9.33	9.33	3.50	3.50	0.00	0.00	3.50	3.50
cycles	6.00	6.00	6.00	6.00	5.00	9.33	9.33	9.33	3.50	3.50	0.00	0.00	3.50	3.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.83
Dispatch	9.33
Overall L1	9.83

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.83 cycles. At this rate:

17% of peak load performance is reached (17.08 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (5.69 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.83 to 9.33 cycles (1.05x speedup).

ASM code

In the binary file, the address of the loop is: 5b6c0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
TEST %RDI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JLE 5b86f <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x35f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $0x7,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 5b7ad <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x29d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x1,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 5b78d <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x27d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x2,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 5b776 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x266>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x3,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 5b75f <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x24f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x4,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 5b748 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x238>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x5,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 5b731 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x221>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x6,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 5b71a <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x20a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV $0x1,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RSI),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD (%RBX),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD (%RCX),%XMM7,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD (%RBX,%RAX,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD (%RSI),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD (%RCX,%RAX,8),%XMM2,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM1,(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RBX,%RAX,8),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD (%RSI),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD (%RCX,%RAX,8),%XMM6,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM3,(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RBX,%RAX,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD (%RSI),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD (%RCX,%RAX,8),%XMM5,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM4,(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RBX,%RAX,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD (%RSI),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD (%RCX,%RAX,8),%XMM9,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM8,(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RBX,%RAX,8),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD (%RSI),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD (%RCX,%RAX,8),%XMM11,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM10,(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RBX,%RAX,8),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD (%RSI),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD (%RCX,%RAX,8),%XMM13,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM12,(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 5b86f <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x35f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD %R11,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R10,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 5b6c0 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x1b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Function	_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0
Source file and lines	forall.hpp:59-59
Module	libkripke.so

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp:57

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.83 to 9.33 cycles (1.05x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 7 FMA (fused multiply-add) operations.

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 14 FP arithmetical operations:

7: addition or subtraction (all inside FMA instructions)
7: multiply (all inside FMA instructions)

The binary loop is loading 168 bytes (21 double precision FP elements). The binary loop is storing 56 bytes (7 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	60
nb uops	59
loop length	256
used x86 registers	9
used mmx registers	0
used xmm registers	14
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.83 cycles
front end	9.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.00	6.00	6.00	6.00	5.00	9.33	9.33	9.33	3.50	3.50	0.00	0.00	3.50	3.50
cycles	6.00	6.00	6.00	6.00	5.00	9.33	9.33	9.33	3.50	3.50	0.00	0.00	3.50	3.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.83
Dispatch	9.33
Overall L1	9.83

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.83 cycles. At this rate:

17% of peak load performance is reached (17.08 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (5.69 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 5b6c0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
TEST %RDI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JLE 5b86f <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x35f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $0x7,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 5b7ad <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x29d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x1,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 5b78d <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x27d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x2,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 5b776 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x266>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x3,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 5b75f <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x24f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x4,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 5b748 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x238>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x5,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 5b731 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x221>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x6,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 5b71a <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x20a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV $0x1,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RSI),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD (%RBX),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD (%RCX),%XMM7,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD (%RBX,%RAX,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD (%RSI),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD (%RCX,%RAX,8),%XMM2,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM1,(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RBX,%RAX,8),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD (%RSI),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD (%RCX,%RAX,8),%XMM6,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM3,(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RBX,%RAX,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD (%RSI),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD (%RCX,%RAX,8),%XMM5,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM4,(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RBX,%RAX,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD (%RSI),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD (%RCX,%RAX,8),%XMM9,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM8,(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RBX,%RAX,8),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD (%RSI),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD (%RCX,%RAX,8),%XMM11,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM10,(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RBX,%RAX,8),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD (%RSI),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD (%RCX,%RAX,8),%XMM13,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM12,(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 5b86f <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x35f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD %R11,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R10,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 5b6c0 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x1b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code