OV - exec - Loop 900 - libkripke.so

	Loop Id: 900	Module: libkripke.so	Source: RangeSegment.hpp:120-120 [...]	Coverage: 0.01%

0x5b650 TEST	%R10,%R10

0x5b653 JLE	5b889

0x5b659 MOV	-0x58(%RBP),%RAX

0x5b65d MOV	-0x40(%RBP),%RCX

0x5b661 MOV	-0x70(%RBP),%RSI

0x5b665 MOV	%R8,-0x38(%RBP)

0x5b669 MOV	-0x60(%RBP),%RBX

0x5b66d MOV	%RDX,%R8

0x5b670 ADD	%R9,%RAX

0x5b673 IMUL	%RAX,%RCX

0x5b677 LEA	(%RDX,%RBX,1),%R15

0x5b67b MOV	-0x88(%RBP),%RBX

0x5b682 IMUL	%R14,%RAX

0x5b686 ADD	%R12,%RCX

0x5b689 LEA	(%RSI,%RCX,8),%RSI

0x5b68d MOV	-0x48(%RBP),%RCX

0x5b691 IMUL	%R15,%RCX

0x5b695 ADD	%RBX,%RCX

0x5b698 MOV	-0x78(%RBP),%RBX

0x5b69c LEA	(%RBX,%RCX,8),%RCX

0x5b6a0 MOV	-0x50(%RBP),%RBX

0x5b6a4 IMUL	%RBX,%R15

0x5b6a8 ADD	%R15,%RAX

0x5b6ab MOV	-0x68(%RBP),%R15

0x5b6af ADD	%R13,%RAX

0x5b6b2 LEA	(%R15,%RAX,8),%RBX

0x5b6b6 XOR	%EAX,%EAX

0x5b6b8 MOV	%RAX,%RDX

0x5b6bb NOPL	(%RAX,%RAX,1)

  (901) 0x5b6c0 XOR	%EAX,%EAX

  (901) 0x5b6c2 TEST	%RDI,%RDI

  (901) 0x5b6c5 JLE	5b86f

  (901) 0x5b6cb MOV	%RDI,%R15

  (901) 0x5b6ce AND	$0x7,%R15D

  (901) 0x5b6d2 JE	5b7ad

  (901) 0x5b6d8 CMP	$0x1,%R15

  (901) 0x5b6dc JE	5b78d

  (901) 0x5b6e2 CMP	$0x2,%R15

  (901) 0x5b6e6 JE	5b776

  (901) 0x5b6ec CMP	$0x3,%R15

  (901) 0x5b6f0 JE	5b75f

  (901) 0x5b6f2 CMP	$0x4,%R15

  (901) 0x5b6f6 JE	5b748

  (901) 0x5b6f8 CMP	$0x5,%R15

  (901) 0x5b6fc JE	5b731

  (901) 0x5b6fe CMP	$0x6,%R15

  (901) 0x5b702 JE	5b71a

  (901) 0x5b704 MOV	$0x1,%EAX

  (901) 0x5b709 VMOVSD	(%RSI),%XMM0

  (901) 0x5b70d VMOVSD	(%RBX),%XMM7

  (901) 0x5b711 VFMADD132SD	(%RCX),%XMM7,%XMM0

  (901) 0x5b716 VMOVSD	%XMM0,(%RBX)

  (901) 0x5b71a VMOVSD	(%RBX,%RAX,8),%XMM2

  (901) 0x5b71f VMOVSD	(%RSI),%XMM1

  (901) 0x5b723 VFMADD132SD	(%RCX,%RAX,8),%XMM2,%XMM1

  (901) 0x5b729 VMOVSD	%XMM1,(%RBX,%RAX,8)

  (901) 0x5b72e INC	%RAX

  (901) 0x5b731 VMOVSD	(%RBX,%RAX,8),%XMM6

  (901) 0x5b736 VMOVSD	(%RSI),%XMM3

  (901) 0x5b73a VFMADD132SD	(%RCX,%RAX,8),%XMM6,%XMM3

  (901) 0x5b740 VMOVSD	%XMM3,(%RBX,%RAX,8)

  (901) 0x5b745 INC	%RAX

  (901) 0x5b748 VMOVSD	(%RBX,%RAX,8),%XMM5

  (901) 0x5b74d VMOVSD	(%RSI),%XMM4

  (901) 0x5b751 VFMADD132SD	(%RCX,%RAX,8),%XMM5,%XMM4

  (901) 0x5b757 VMOVSD	%XMM4,(%RBX,%RAX,8)

  (901) 0x5b75c INC	%RAX

  (901) 0x5b75f VMOVSD	(%RBX,%RAX,8),%XMM9

  (901) 0x5b764 VMOVSD	(%RSI),%XMM8

  (901) 0x5b768 VFMADD132SD	(%RCX,%RAX,8),%XMM9,%XMM8

  (901) 0x5b76e VMOVSD	%XMM8,(%RBX,%RAX,8)

  (901) 0x5b773 INC	%RAX

  (901) 0x5b776 VMOVSD	(%RBX,%RAX,8),%XMM11

  (901) 0x5b77b VMOVSD	(%RSI),%XMM10

  (901) 0x5b77f VFMADD132SD	(%RCX,%RAX,8),%XMM11,%XMM10

  (901) 0x5b785 VMOVSD	%XMM10,(%RBX,%RAX,8)

  (901) 0x5b78a INC	%RAX

  (901) 0x5b78d VMOVSD	(%RBX,%RAX,8),%XMM13

  (901) 0x5b792 VMOVSD	(%RSI),%XMM12

  (901) 0x5b796 VFMADD132SD	(%RCX,%RAX,8),%XMM13,%XMM12

  (901) 0x5b79c VMOVSD	%XMM12,(%RBX,%RAX,8)

  (901) 0x5b7a1 INC	%RAX

  (901) 0x5b7a4 CMP	%RAX,%RDI

  (901) 0x5b7a7 JE	5b86f

    (902) 0x5b7ad VMOVSD	(%RSI),%XMM14

    (902) 0x5b7b1 VMOVSD	(%RBX,%RAX,8),%XMM15

    (902) 0x5b7b6 VMOVSD	0x8(%RBX,%RAX,8),%XMM7

    (902) 0x5b7bc VFMADD132SD	(%RCX,%RAX,8),%XMM15,%XMM14

    (902) 0x5b7c2 VMOVSD	0x10(%RBX,%RAX,8),%XMM2

    (902) 0x5b7c8 VMOVSD	%XMM14,(%RBX,%RAX,8)

    (902) 0x5b7cd VMOVSD	0x18(%RBX,%RAX,8),%XMM6

    (902) 0x5b7d3 VMOVSD	(%RSI),%XMM0

    (902) 0x5b7d7 VMOVSD	0x20(%RBX,%RAX,8),%XMM5

    (902) 0x5b7dd VFMADD132SD	0x8(%RCX,%RAX,8),%XMM7,%XMM0

    (902) 0x5b7e4 VMOVSD	0x28(%RBX,%RAX,8),%XMM9

    (902) 0x5b7ea VMOVSD	%XMM0,0x8(%RBX,%RAX,8)

    (902) 0x5b7f0 VMOVSD	0x30(%RBX,%RAX,8),%XMM11

    (902) 0x5b7f6 VMOVSD	(%RSI),%XMM1

    (902) 0x5b7fa VMOVSD	0x38(%RBX,%RAX,8),%XMM13

    (902) 0x5b800 VFMADD132SD	0x10(%RCX,%RAX,8),%XMM2,%XMM1

    (902) 0x5b807 VMOVSD	%XMM1,0x10(%RBX,%RAX,8)

    (902) 0x5b80d VMOVSD	(%RSI),%XMM3

    (902) 0x5b811 VFMADD132SD	0x18(%RCX,%RAX,8),%XMM6,%XMM3

    (902) 0x5b818 VMOVSD	%XMM3,0x18(%RBX,%RAX,8)

    (902) 0x5b81e VMOVSD	(%RSI),%XMM4

    (902) 0x5b822 VFMADD132SD	0x20(%RCX,%RAX,8),%XMM5,%XMM4

    (902) 0x5b829 VMOVSD	%XMM4,0x20(%RBX,%RAX,8)

    (902) 0x5b82f VMOVSD	(%RSI),%XMM8

    (902) 0x5b833 VFMADD132SD	0x28(%RCX,%RAX,8),%XMM9,%XMM8

    (902) 0x5b83a VMOVSD	%XMM8,0x28(%RBX,%RAX,8)

    (902) 0x5b840 VMOVSD	(%RSI),%XMM10

    (902) 0x5b844 VFMADD132SD	0x30(%RCX,%RAX,8),%XMM11,%XMM10

    (902) 0x5b84b VMOVSD	%XMM10,0x30(%RBX,%RAX,8)

    (902) 0x5b851 VMOVSD	(%RSI),%XMM12

    (902) 0x5b855 VFMADD132SD	0x38(%RCX,%RAX,8),%XMM13,%XMM12

    (902) 0x5b85c VMOVSD	%XMM12,0x38(%RBX,%RAX,8)

    (902) 0x5b862 ADD	$0x8,%RAX

    (902) 0x5b866 CMP	%RAX,%RDI

    (902) 0x5b869 JNE	5b7ad

  (901) 0x5b86f INC	%RDX

  (901) 0x5b872 ADD	$0x8,%RSI

  (901) 0x5b876 ADD	%R11,%RCX

  (901) 0x5b879 CMP	%R10,%RDX

  (901) 0x5b87c JNE	5b6c0

0x5b882 MOV	%R8,%RDX

0x5b885 MOV	-0x38(%RBP),%R8

0x5b889 CMP	%R8,-0x80(%RBP)

0x5b88d JE	5b8a3

0x5b88f INC	%RDX

0x5b892 CMP	%RDX,-0x90(%RBP)

0x5b899 JLE	5b8b2

0x5b89b INC	%R8

0x5b89e JMP	5b650

0x5b8b2 INC	%R9

0x5b8b5 XOR	%EDX,%EDX

0x5b8b7 JMP	5b89b

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp: 307 - 307

--------------------------------------------------------------------------------

307:     return Ret{lhs} + rhs;

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp: 55 - 55

--------------------------------------------------------------------------------

55:     return a * b;

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/RangeSegment.hpp: 120 - 120

--------------------------------------------------------------------------------

120:   RAJA_HOST_DEVICE RAJA_INLINE ~TypedRangeSegment() {}

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp: 81 - 81

--------------------------------------------------------------------------------

81: #pragma omp parallel for private(i0, i1) firstprivate(privatizer) \

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp: 177 - 177

--------------------------------------------------------------------------------

177:     return value_type(val + rhs);

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp: 57 - 57

--------------------------------------------------------------------------------

57:             rhs(d,g,z) += ell_plus(d, nm) * phi_out(nm, g, z);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.40
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	micro-operation queue,
Function	_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0
Source	Operators.hpp:307-307,Layout.hpp:55-55,RangeSegment.hpp:120-120,Collapse.hpp:81-81,forall.hpp:59-59,Iterators.hpp:177-177
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.67
CQA cycles if no scalar integer	6.67
CQA cycles if FP arith vectorized	6.67
CQA cycles if fully vectorized	1.04
Front-end cycles	6.67
DIV/SQRT cycles	5.50
P0 cycles	5.50
P1 cycles	5.25
P2 cycles	5.25
P3 cycles	2.50
P4 cycles	4.33
P5 cycles	4.33
P6 cycles	4.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	41.00
Nb uops	40.00
Nb loads	12.00
Nb stores	1.00
Nb stack references	12.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.60
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.40
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	micro-operation queue,
Function	_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0
Source	Operators.hpp:307-307,Layout.hpp:55-55,RangeSegment.hpp:120-120,Collapse.hpp:81-81,forall.hpp:59-59,Iterators.hpp:177-177
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.67
CQA cycles if no scalar integer	6.67
CQA cycles if FP arith vectorized	6.67
CQA cycles if fully vectorized	1.04
Front-end cycles	6.67
DIV/SQRT cycles	5.50
P0 cycles	5.50
P1 cycles	5.25
P2 cycles	5.25
P3 cycles	2.50
P4 cycles	4.33
P5 cycles	4.33
P6 cycles	4.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	41.00
Nb uops	40.00
Nb loads	12.00
Nb stores	1.00
Nb stack references	12.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.60
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0
Source file and lines	RangeSegment.hpp:120-120
Module	libkripke.so

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:307
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/RangeSegment.hpp:120
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp:177
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp:57

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 34 paths individually, rerun with max-paths=34
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 34 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.67 to 1.04 cycles (6.40x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 96 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	41
nb uops	40
loop length	152
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.67 cycles
front end	6.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	5.50	5.50	5.25	5.25	2.50	4.33	4.33	4.33	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.50	5.50	5.25	5.25	2.50	4.33	4.33	4.33	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.67
Dispatch	5.50
Overall L1	6.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.67 cycles. At this rate:

14% of peak load performance is reached (14.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.20 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.67 to 5.50 cycles (1.21x speedup).

ASM code

In the binary file, the address of the loop is: 5b650

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
TEST %R10,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 5b889 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x379>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV -0x70(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %R8,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV -0x60(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %RDX,%R8	1	0	0	0	0	0	0	0	0	0	0.17
ADD %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	3	1
LEA (%RDX,%RBX,1),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x88(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
IMUL %R14,%RAX	1	0	1	0	0	0	0	0	0	3	1
ADD %R12,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%RSI,%RCX,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x48(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
IMUL %R15,%RCX	1	0	1	0	0	0	0	0	0	3	1
ADD %RBX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x78(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
LEA (%RBX,%RCX,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x50(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
IMUL %RBX,%R15	1	0	1	0	0	0	0	0	0	3	1
ADD %R15,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x68(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
ADD %R13,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%R15,%RAX,8),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0.25
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0.17
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
MOV %R8,%RDX	1	0	0	0	0	0	0	0	0	0	0.17
MOV -0x38(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CMP %R8,-0x80(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
JE 5b8a3 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x393>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP %RDX,-0x90(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
JLE 5b8b2 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x3a2>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
INC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JMP 5b650 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x140>	1	0.50	0	0	0	0.50	0	0	0	0	1
INC %R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0.25
JMP 5b89b <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x38b>	1	0.50	0	0	0	0.50	0	0	0	0	1

Function	_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0
Source file and lines	RangeSegment.hpp:120-120
Module	libkripke.so

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:307
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/RangeSegment.hpp:120
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp:177
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp:57

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 34 paths individually, rerun with max-paths=34
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.67 to 1.04 cycles (6.40x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 96 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	41
nb uops	40
loop length	152
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.67 cycles
front end	6.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	5.50	5.50	5.25	5.25	2.50	4.33	4.33	4.33	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.50	5.50	5.25	5.25	2.50	4.33	4.33	4.33	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.67
Dispatch	5.50
Overall L1	6.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.67 cycles. At this rate:

14% of peak load performance is reached (14.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.20 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 5b650

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
TEST %R10,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 5b889 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x379>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV -0x70(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %R8,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV -0x60(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %RDX,%R8	1	0	0	0	0	0	0	0	0	0	0.17
ADD %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	3	1
LEA (%RDX,%RBX,1),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x88(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
IMUL %R14,%RAX	1	0	1	0	0	0	0	0	0	3	1
ADD %R12,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%RSI,%RCX,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x48(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
IMUL %R15,%RCX	1	0	1	0	0	0	0	0	0	3	1
ADD %RBX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x78(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
LEA (%RBX,%RCX,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x50(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
IMUL %RBX,%R15	1	0	1	0	0	0	0	0	0	3	1
ADD %R15,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x68(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
ADD %R13,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%R15,%RAX,8),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0.25
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0.17
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
MOV %R8,%RDX	1	0	0	0	0	0	0	0	0	0	0.17
MOV -0x38(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CMP %R8,-0x80(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
JE 5b8a3 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x393>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP %RDX,-0x90(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
JLE 5b8b2 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x3a2>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
INC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JMP 5b650 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x140>	1	0.50	0	0	0	0.50	0	0	0	0	1
INC %R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0.25
JMP 5b89b <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x38b>	1	0.50	0	0	0	0.50	0	0	0	0	1

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code