OV - exec - Loop 1020 - libkripke.so

	Loop Id: 1020	Module: libkripke.so	Source: RangeSegment.hpp:120-120 [...]	Coverage: 0.02%

0x64410 TEST	%R10,%R10

0x64413 JLE	64665

0x64419 MOV	-0x38(%RBP),%R12

0x6441d MOV	-0x60(%RBP),%RCX

0x64421 MOV	-0x58(%RBP),%RSI

0x64425 MOV	%R8,-0x40(%RBP)

0x64429 MOV	-0x78(%RBP),%RAX

0x6442d LEA	(%R12,%RCX,1),%R13

0x64431 MOV	-0x70(%RBP),%RCX

0x64435 ADD	%RSI,%RAX

0x64438 LEA	(%R14,%RAX,1),%R12

0x6443c IMUL	%R9,%RAX

0x64440 LEA	(%RCX,%R12,8),%RSI

0x64444 MOV	-0x48(%RBP),%RCX

0x64448 MOV	-0x88(%RBP),%R12

0x6444f IMUL	%R13,%RCX

0x64453 ADD	%R12,%RCX

0x64456 MOV	-0x50(%RBP),%R12

0x6445a LEA	(%RDX,%RCX,8),%RCX

0x6445e IMUL	%R12,%R13

0x64462 ADD	%R13,%RAX

0x64465 MOV	-0x68(%RBP),%R13

0x64469 ADD	%RBX,%RAX

0x6446c LEA	(%R13,%RAX,8),%R12

0x64471 XOR	%EAX,%EAX

0x64473 MOV	%RAX,%R8

0x64476 NOPW	%CS:(%RAX,%RAX,1)

  (1021) 0x64480 XOR	%EAX,%EAX

  (1021) 0x64482 TEST	%RDI,%RDI

  (1021) 0x64485 JLE	6464f

  (1021) 0x6448b MOV	%RDI,%R13

  (1021) 0x6448e AND	$0x7,%R13D

  (1021) 0x64492 JE	6457d

  (1021) 0x64498 CMP	$0x1,%R13

  (1021) 0x6449c JE	6455b

  (1021) 0x644a2 CMP	$0x2,%R13

  (1021) 0x644a6 JE	64542

  (1021) 0x644ac CMP	$0x3,%R13

  (1021) 0x644b0 JE	64529

  (1021) 0x644b2 CMP	$0x4,%R13

  (1021) 0x644b6 JE	64510

  (1021) 0x644b8 CMP	$0x5,%R13

  (1021) 0x644bc JE	644f7

  (1021) 0x644be CMP	$0x6,%R13

  (1021) 0x644c2 JE	644de

  (1021) 0x644c4 MOV	$0x1,%EAX

  (1021) 0x644c9 VMOVSD	(%RSI),%XMM0

  (1021) 0x644cd VMOVSD	(%R12),%XMM2

  (1021) 0x644d3 VFMADD132SD	(%RCX),%XMM2,%XMM0

  (1021) 0x644d8 VMOVSD	%XMM0,(%R12)

  (1021) 0x644de VMOVSD	(%R12,%RAX,8),%XMM4

  (1021) 0x644e4 VMOVSD	(%RSI),%XMM3

  (1021) 0x644e8 VFMADD132SD	(%RCX,%RAX,8),%XMM4,%XMM3

  (1021) 0x644ee VMOVSD	%XMM3,(%R12,%RAX,8)

  (1021) 0x644f4 INC	%RAX

  (1021) 0x644f7 VMOVSD	(%R12,%RAX,8),%XMM7

  (1021) 0x644fd VMOVSD	(%RSI),%XMM5

  (1021) 0x64501 VFMADD132SD	(%RCX,%RAX,8),%XMM7,%XMM5

  (1021) 0x64507 VMOVSD	%XMM5,(%R12,%RAX,8)

  (1021) 0x6450d INC	%RAX

  (1021) 0x64510 VMOVSD	(%R12,%RAX,8),%XMM6

  (1021) 0x64516 VMOVSD	(%RSI),%XMM8

  (1021) 0x6451a VFMADD132SD	(%RCX,%RAX,8),%XMM6,%XMM8

  (1021) 0x64520 VMOVSD	%XMM8,(%R12,%RAX,8)

  (1021) 0x64526 INC	%RAX

  (1021) 0x64529 VMOVSD	(%R12,%RAX,8),%XMM10

  (1021) 0x6452f VMOVSD	(%RSI),%XMM9

  (1021) 0x64533 VFMADD132SD	(%RCX,%RAX,8),%XMM10,%XMM9

  (1021) 0x64539 VMOVSD	%XMM9,(%R12,%RAX,8)

  (1021) 0x6453f INC	%RAX

  (1021) 0x64542 VMOVSD	(%R12,%RAX,8),%XMM12

  (1021) 0x64548 VMOVSD	(%RSI),%XMM11

  (1021) 0x6454c VFMADD132SD	(%RCX,%RAX,8),%XMM12,%XMM11

  (1021) 0x64552 VMOVSD	%XMM11,(%R12,%RAX,8)

  (1021) 0x64558 INC	%RAX

  (1021) 0x6455b VMOVSD	(%R12,%RAX,8),%XMM14

  (1021) 0x64561 VMOVSD	(%RSI),%XMM13

  (1021) 0x64565 VFMADD132SD	(%RCX,%RAX,8),%XMM14,%XMM13

  (1021) 0x6456b VMOVSD	%XMM13,(%R12,%RAX,8)

  (1021) 0x64571 INC	%RAX

  (1021) 0x64574 CMP	%RAX,%RDI

  (1021) 0x64577 JE	6464f

    (1022) 0x6457d VMOVSD	(%RSI),%XMM15

    (1022) 0x64581 VMOVSD	(%R12,%RAX,8),%XMM1

    (1022) 0x64587 VMOVSD	0x8(%R12,%RAX,8),%XMM2

    (1022) 0x6458e VFMADD132SD	(%RCX,%RAX,8),%XMM1,%XMM15

    (1022) 0x64594 VMOVSD	0x10(%R12,%RAX,8),%XMM4

    (1022) 0x6459b VMOVSD	%XMM15,(%R12,%RAX,8)

    (1022) 0x645a1 VMOVSD	0x18(%R12,%RAX,8),%XMM5

    (1022) 0x645a8 VMOVSD	(%RSI),%XMM0

    (1022) 0x645ac VMOVSD	0x20(%R12,%RAX,8),%XMM6

    (1022) 0x645b3 VFMADD132SD	0x8(%RCX,%RAX,8),%XMM2,%XMM0

    (1022) 0x645ba VMOVSD	0x28(%R12,%RAX,8),%XMM10

    (1022) 0x645c1 VMOVSD	%XMM0,0x8(%R12,%RAX,8)

    (1022) 0x645c8 VMOVSD	0x30(%R12,%RAX,8),%XMM12

    (1022) 0x645cf VMOVSD	(%RSI),%XMM3

    (1022) 0x645d3 VMOVSD	0x38(%R12,%RAX,8),%XMM14

    (1022) 0x645da VFMADD132SD	0x10(%RCX,%RAX,8),%XMM4,%XMM3

    (1022) 0x645e1 VMOVSD	%XMM3,0x10(%R12,%RAX,8)

    (1022) 0x645e8 VMOVSD	(%RSI),%XMM7

    (1022) 0x645ec VFMADD132SD	0x18(%RCX,%RAX,8),%XMM5,%XMM7

    (1022) 0x645f3 VMOVSD	%XMM7,0x18(%R12,%RAX,8)

    (1022) 0x645fa VMOVSD	(%RSI),%XMM8

    (1022) 0x645fe VFMADD132SD	0x20(%RCX,%RAX,8),%XMM6,%XMM8

    (1022) 0x64605 VMOVSD	%XMM8,0x20(%R12,%RAX,8)

    (1022) 0x6460c VMOVSD	(%RSI),%XMM9

    (1022) 0x64610 VFMADD132SD	0x28(%RCX,%RAX,8),%XMM10,%XMM9

    (1022) 0x64617 VMOVSD	%XMM9,0x28(%R12,%RAX,8)

    (1022) 0x6461e VMOVSD	(%RSI),%XMM11

    (1022) 0x64622 VFMADD132SD	0x30(%RCX,%RAX,8),%XMM12,%XMM11

    (1022) 0x64629 VMOVSD	%XMM11,0x30(%R12,%RAX,8)

    (1022) 0x64630 VMOVSD	(%RSI),%XMM13

    (1022) 0x64634 VFMADD132SD	0x38(%RCX,%RAX,8),%XMM14,%XMM13

    (1022) 0x6463b VMOVSD	%XMM13,0x38(%R12,%RAX,8)

    (1022) 0x64642 ADD	$0x8,%RAX

    (1022) 0x64646 CMP	%RAX,%RDI

    (1022) 0x64649 JNE	6457d

  (1021) 0x6464f INC	%R8

  (1021) 0x64652 ADD	%R15,%RSI

  (1021) 0x64655 ADD	%R11,%RCX

  (1021) 0x64658 CMP	%R10,%R8

  (1021) 0x6465b JNE	64480

0x64661 MOV	-0x40(%RBP),%R8

0x64665 MOV	-0x80(%RBP),%RSI

0x64669 CMP	%RSI,%R8

0x6466c JE	64687

0x6466e INCQ	-0x38(%RBP)

0x64672 MOV	-0x38(%RBP),%RCX

0x64676 CMP	%RCX,-0x90(%RBP)

0x6467d JLE	64696

0x6467f INC	%R8

0x64682 JMP	64410

0x64696 INCQ	-0x78(%RBP)

0x6469a MOVQ	$0,-0x38(%RBP)

0x646a2 JMP	6467f

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp: 307 - 307

--------------------------------------------------------------------------------

307:     return Ret{lhs} + rhs;

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp: 55 - 55

--------------------------------------------------------------------------------

55:     return a * b;

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/RangeSegment.hpp: 120 - 120

--------------------------------------------------------------------------------

120:   RAJA_HOST_DEVICE RAJA_INLINE ~TypedRangeSegment() {}

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp: 81 - 81

--------------------------------------------------------------------------------

81: #pragma omp parallel for private(i0, i1) firstprivate(privatizer) \

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/LTimes.cpp: 62 - 62

--------------------------------------------------------------------------------

62:            phi(nm,g,z) += ell(nm, d) * psi(d, g, z);

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp: 177 - 177

--------------------------------------------------------------------------------

177:     return value_type(val + rhs);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.66
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	micro-operation queue,
Function	_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_9DirectionElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK10LTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0
Source	Operators.hpp:307-307,Layout.hpp:55-55,RangeSegment.hpp:120-120,Collapse.hpp:81-81,forall.hpp:59-59,Iterators.hpp:177-177
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.83
CQA cycles if no scalar integer	6.83
CQA cycles if FP arith vectorized	6.83
CQA cycles if fully vectorized	1.21
Front-end cycles	6.83
DIV/SQRT cycles	5.25
P0 cycles	5.25
P1 cycles	5.00
P2 cycles	5.00
P3 cycles	2.50
P4 cycles	5.67
P5 cycles	5.67
P6 cycles	5.67
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	41.00
Nb loads	15.00
Nb stores	4.00
Nb stack references	12.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.24
Bytes prefetched	0.00
Bytes loaded	120.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.93
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	10.42
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.66
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	micro-operation queue,
Function	_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_9DirectionElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK10LTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0
Source	Operators.hpp:307-307,Layout.hpp:55-55,RangeSegment.hpp:120-120,Collapse.hpp:81-81,forall.hpp:59-59,Iterators.hpp:177-177
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.83
CQA cycles if no scalar integer	6.83
CQA cycles if FP arith vectorized	6.83
CQA cycles if fully vectorized	1.21
Front-end cycles	6.83
DIV/SQRT cycles	5.25
P0 cycles	5.25
P1 cycles	5.00
P2 cycles	5.00
P3 cycles	2.50
P4 cycles	5.67
P5 cycles	5.67
P6 cycles	5.67
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	41.00
Nb loads	15.00
Nb stores	4.00
Nb stack references	12.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.24
Bytes prefetched	0.00
Bytes loaded	120.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.93
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	10.42
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_9DirectionElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK10LTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0
Source file and lines	RangeSegment.hpp:120-120
Module	libkripke.so

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:307
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/RangeSegment.hpp:120
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/LTimes.cpp:62
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp:177

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 34 paths individually, rerun with max-paths=34
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 34 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.83 to 1.21 cycles (5.66x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

INC: 2 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 120 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	40
nb uops	41
loop length	164
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.83 cycles
front end	6.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	5.25	5.25	5.00	5.00	2.50	5.67	5.67	5.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.25	5.25	5.00	5.00	2.50	5.67	5.67	5.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.83
Dispatch	5.67
Overall L1	6.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.83 cycles. At this rate:

18% of peak load performance is reached (17.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.68 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.83 to 5.67 cycles (1.21x speedup).

ASM code

In the binary file, the address of the loop is: 64410

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
TEST %R10,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 64665 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_9DirectionElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK10LTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x3b5>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV -0x38(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV -0x60(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV -0x58(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %R8,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV -0x78(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
LEA (%R12,%RCX,1),%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x70(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
ADD %RSI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%R14,%RAX,1),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
IMUL %R9,%RAX	1	0	1	0	0	0	0	0	0	3	1
LEA (%RCX,%R12,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x48(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV -0x88(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
IMUL %R13,%RCX	1	0	1	0	0	0	0	0	0	3	1
ADD %R12,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x50(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
LEA (%RDX,%RCX,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
IMUL %R12,%R13	1	0	1	0	0	0	0	0	0	3	1
ADD %R13,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x68(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
ADD %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%R13,%RAX,8),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0.25
MOV %RAX,%R8	1	0	0	0	0	0	0	0	0	0	0.17
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
MOV -0x40(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV -0x80(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CMP %RSI,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JE 64687 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_9DirectionElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK10LTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x3d7>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
INCQ -0x38(%RBP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.50
MOV -0x38(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CMP %RCX,-0x90(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
JLE 64696 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_9DirectionElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK10LTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x3e6>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
INC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JMP 64410 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_9DirectionElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK10LTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x160>	1	0.50	0	0	0	0.50	0	0	0	0	1
INCQ -0x78(%RBP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.50
MOVQ $0,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
JMP 6467f <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_9DirectionElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK10LTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x3cf>	1	0.50	0	0	0	0.50	0	0	0	0	1

Function	_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_9DirectionElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK10LTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0
Source file and lines	RangeSegment.hpp:120-120
Module	libkripke.so

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:307
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/RangeSegment.hpp:120
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/LTimes.cpp:62
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp:177

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 34 paths individually, rerun with max-paths=34
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

INC: 2 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 120 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	40
nb uops	41
loop length	164
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.83 cycles
front end	6.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	5.25	5.25	5.00	5.00	2.50	5.67	5.67	5.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.25	5.25	5.00	5.00	2.50	5.67	5.67	5.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.83
Dispatch	5.67
Overall L1	6.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.83 cycles. At this rate:

18% of peak load performance is reached (17.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.68 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 64410

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
TEST %R10,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 64665 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_9DirectionElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK10LTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x3b5>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV -0x38(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV -0x60(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV -0x58(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %R8,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV -0x78(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
LEA (%R12,%RCX,1),%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x70(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
ADD %RSI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%R14,%RAX,1),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
IMUL %R9,%RAX	1	0	1	0	0	0	0	0	0	3	1
LEA (%RCX,%R12,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x48(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV -0x88(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
IMUL %R13,%RCX	1	0	1	0	0	0	0	0	0	3	1
ADD %R12,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x50(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
LEA (%RDX,%RCX,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
IMUL %R12,%R13	1	0	1	0	0	0	0	0	0	3	1
ADD %R13,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x68(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
ADD %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%R13,%RAX,8),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0.25
MOV %RAX,%R8	1	0	0	0	0	0	0	0	0	0	0.17
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
MOV -0x40(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV -0x80(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CMP %RSI,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JE 64687 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_9DirectionElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK10LTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x3d7>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
INCQ -0x38(%RBP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.50
MOV -0x38(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CMP %RCX,-0x90(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
JLE 64696 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_9DirectionElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK10LTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x3e6>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
INC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JMP 64410 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_9DirectionElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK10LTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x160>	1	0.50	0	0	0	0.50	0	0	0	0	1
INCQ -0x78(%RBP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.50
MOVQ $0,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
JMP 6467f <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke6MomentElPSS_EESS_EENSO_INSQ_INSR_9DirectionElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK10LTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x3cf>	1	0.50	0	0	0	0.50	0	0	0	0	1

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

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Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

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Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code