OV - exec - Function _ZZNK9SweepSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_RNS1_4Core9DataStoreENS1_6SdomIdEENKUlNS1_9DirectionENS1_5GroupENS1_5ZoneKENS1_5ZoneJENS1_5ZoneIEE_clESB_SC_SD_SE_SF

	Function: _ZZNK9SweepSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_RNS1_4 ...	Module: libkripke.so	Source: SweepSubdomain.cpp:85-105 [...]	Coverage: 2.59%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp: 307 - 307

--------------------------------------------------------------------------------

307:     return Ret{lhs} + rhs;

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp: 85 - 105

--------------------------------------------------------------------------------

85:         KRIPKE_LAMBDA (Direction d, Group g, ZoneK k, ZoneJ j, ZoneI i) {

86:

87:             double xcos_dxi = 2.0 * xcos(d) / dx(i);

88:             double ycos_dyj = 2.0 * ycos(d) / dy(j);

89:             double zcos_dzk = 2.0 * zcos(d) / dz(k);

90:

91:             Zone z(zone_layout(*i, *j, *k));

92:

93:             /* Calculate new zonal flux */

94:             double psi_d_g_z = (rhs(d,g,z)

95:                 + psi_lf(d, g, j, k) * xcos_dxi

96:                 + psi_fr(d, g, i, k) * ycos_dyj

97:                 + psi_bo(d, g, i, j) * zcos_dzk)

98:                 / (xcos_dxi + ycos_dyj + zcos_dzk + sigt(g, z));

99:

100:             psi(d, g, z) = psi_d_g_z;

101:

102:             /* Apply diamond-difference relationships */

103:             psi_lf(d, g, j, k) = 2.0 * psi_d_g_z - psi_lf(d, g, j, k);

104:             psi_fr(d, g, i, k) = 2.0 * psi_d_g_z - psi_fr(d, g, i, k);

105:             psi_bo(d, g, i, j) = 2.0 * psi_d_g_z - psi_bo(d, g, i, j);

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp: 55 - 55

--------------------------------------------------------------------------------

55:     return a * b;

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp: 110 - 110

--------------------------------------------------------------------------------

110:     return data[idx];

0x706c0 PUSH	%RBP

0x706c1 MOV	%RDI,%RAX

0x706c4 MOV	%RCX,%RDI

0x706c7 MOV	%RSI,%R10

0x706ca MOV	%RSP,%RBP

0x706cd PUSH	%R12

0x706cf PUSH	%RBX

0x706d0 MOV	0x20(%RAX),%RCX

0x706d4 MOV	%RDX,%RSI

0x706d7 LEA	(,%R10,8),%RDX

0x706df MOV	0x70(%RAX),%R11

0x706e3 MOV	0x48(%RAX),%RBX

0x706e7 MOV	0x98(%RAX),%R12

0x706ee VMOVSD	(%RCX,%RDX,1),%XMM0

0x706f3 MOV	0xc0(%RAX),%RCX

0x706fa VADDSD	%XMM0,%XMM0,%XMM1

0x706fe VMOVSD	(%R11,%RDX,1),%XMM2

0x70704 VDIVSD	(%RBX,%R9,8),%XMM1,%XMM4

0x7070a MOV	0x108(%RAX),%RBX

0x70711 MOV	0x118(%RAX),%R11

0x70718 VADDSD	%XMM2,%XMM2,%XMM3

0x7071c VDIVSD	(%R12,%R8,8),%XMM3,%XMM5

0x70722 MOV	0x168(%RAX),%R12

0x70729 VADDSD	%XMM5,%XMM4,%XMM6

0x7072d VMOVSD	(%RCX,%RDX,1),%XMM7

0x70732 MOV	0xe8(%RAX),%RDX

0x70739 VADDSD	%XMM7,%XMM7,%XMM8

0x7073d MOV	0x1e0(%RAX),%RCX

0x70744 IMUL	%R9,%RBX

0x70748 IMUL	%RDI,%R11

0x7074c IMUL	%R10,%R12

0x70750 VDIVSD	(%RDX,%RDI,8),%XMM8,%XMM9

0x70755 MOV	0x110(%RAX),%RDX

0x7075c IMUL	%RSI,%RCX

0x70760 IMUL	%R8,%RDX

0x70764 ADD	%RBX,%RDX

0x70767 MOV	0x1d8(%RAX),%RBX

0x7076e ADD	%R11,%RDX

0x70771 MOV	0x170(%RAX),%R11

0x70778 IMUL	%R10,%RBX

0x7077c IMUL	%RSI,%R11

0x70780 ADD	%RBX,%RCX

0x70783 MOV	0x238(%RAX),%RBX

0x7078a ADD	%RDX,%R11

0x7078d ADD	%R8,%RCX

0x70790 ADD	%R12,%R11

0x70793 MOV	0x1f0(%RAX),%R12

0x7079a IMUL	%RDI,%R12

0x7079e IMUL	0x278(%RAX),%RDI

0x707a6 ADD	%R12,%RCX

0x707a9 LEA	(%RBX,%RCX,8),%R12

0x707ad MOV	0x268(%RAX),%RCX

0x707b4 MOV	0x260(%RAX),%RBX

0x707bb IMUL	%RSI,%RCX

0x707bf IMUL	%R10,%RBX

0x707c3 ADD	%RBX,%RCX

0x707c6 ADD	%R9,%RCX

0x707c9 ADD	%RCX,%RDI

0x707cc MOV	0x2c0(%RAX),%RCX

0x707d3 LEA	(%RCX,%RDI,8),%RBX

0x707d7 MOV	0x2f0(%RAX),%RCX

0x707de MOV	0x2e8(%RAX),%RDI

0x707e5 VMULSD	(%RBX),%XMM5,%XMM10

0x707e9 VFMADD132SD	(%R12),%XMM10,%XMM4

0x707ef IMUL	0x300(%RAX),%R8

0x707f7 VMOVSD	0x873a9(%RIP),%XMM0

0x707ff IMUL	%RSI,%RCX

0x70803 IMUL	%R10,%RDI

0x70807 ADD	%RDI,%RCX

0x7080a ADD	%RCX,%R9

0x7080d MOV	0x390(%RAX),%RCX

0x70814 ADD	%R9,%R8

0x70817 MOV	0x348(%RAX),%R9

0x7081e LEA	(%R9,%R8,8),%RDI

0x70822 MOV	0x1b0(%RAX),%R8

0x70829 MOV	0x3b0(%RAX),%R9

0x70830 VMOVSD	(%RDI),%XMM11

0x70834 VFMADD213SD	(%R8,%R11,8),%XMM9,%XMM11

0x7083a MOV	0x360(%RAX),%R11

0x70841 IMUL	%R10,%R9

0x70845 VADDSD	%XMM11,%XMM4,%XMM12

0x7084a IMUL	%RSI,%R11

0x7084e IMUL	0x3b8(%RAX),%RSI

0x70856 MOV	0x3f8(%RAX),%RAX

0x7085d ADD	%RDX,%R11

0x70860 VADDSD	(%RCX,%R11,8),%XMM9,%XMM13

0x70866 VADDSD	%XMM6,%XMM13,%XMM14

0x7086a VDIVSD	%XMM14,%XMM12,%XMM15

0x7086f VMOVSD	%XMM15,%XMM15,%XMM1

0x70873 VMOVSD	%XMM15,%XMM15,%XMM4

0x70877 ADD	%RSI,%RDX

0x7087a ADD	%R9,%RDX

0x7087d VMOVSD	%XMM15,(%RAX,%RDX,8)

0x70882 VFMSUB213SD	(%R12),%XMM0,%XMM1

0x70888 VMOVSD	%XMM1,(%R12)

0x7088e VFMSUB213SD	(%RBX),%XMM0,%XMM4

0x70893 VMOVSD	%XMM4,(%RBX)

0x70897 VFMSUB213SD	(%RDI),%XMM0,%XMM15

0x7089c VMOVSD	%XMM15,(%RDI)

0x708a0 POP	%RBX

0x708a1 POP	%R12

0x708a3 POP	%RBP

0x708a4 RET

0x708a5 NOPW	%CS:(%RAX,%RAX,1)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	SweepSubdomain.cpp:85-105
Module	libkripke.so

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:307
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp:85-105
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp:110

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your function, you can lower the cost of an iteration from 20.00 to 5.00 cycles (4.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 20.00 to 17.17 cycles (1.17x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 17.17 cycles (1.17x speedup).

FMA

Detected 5 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Type of elements and instruction set

17 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 22 FP arithmetical operations:

12: addition or subtraction (5 inside FMA instructions)
6: multiply (5 inside FMA instructions)
4: divide

The binary function is loading 352 bytes (44 double precision FP elements). The binary function is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	103
nb uops	103
loop length	485
used x86 registers	13
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	7.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.17 cycles
front end	17.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	7.00	17.00	6.75	6.75	0.50	16.00	16.00	16.00	5.00	5.00	4.50	4.50	2.00	2.00
cycles	7.00	17.00	6.75	6.75	0.50	16.00	16.00	16.00	5.00	5.00	4.50	4.50	2.00	2.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

20.00

Cycles summary

Front-end	17.17
Dispatch	17.00
DIV/SQRT	20.00
Overall L1	20.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	12%

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

18% of peak load performance is reached (17.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.60 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 706c0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RSI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV 0x20(%RAX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA (,%R10,8),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x70(%RAX),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x48(%RAX),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x98(%RAX),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RCX,%RDX,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0xc0(%RAX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VADDSD %XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSD (%R11,%RDX,1),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VDIVSD (%RBX,%R9,8),%XMM1,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	13	5
MOV 0x108(%RAX),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x118(%RAX),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VADDSD %XMM2,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VDIVSD (%R12,%R8,8),%XMM3,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	13	5
MOV 0x168(%RAX),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VADDSD %XMM5,%XMM4,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSD (%RCX,%RDX,1),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0xe8(%RAX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VADDSD %XMM7,%XMM7,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOV 0x1e0(%RAX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R9,%RBX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %RDI,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %R10,%R12	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
VDIVSD (%RDX,%RDI,8),%XMM8,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	13	5
MOV 0x110(%RAX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RSI,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %R8,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RBX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x1d8(%RAX),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R11,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x170(%RAX),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R10,%RBX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %RSI,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RBX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x238(%RAX),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %RDX,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R12,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x1f0(%RAX),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RDI,%R12	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL 0x278(%RAX),%RDI	1	0	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
ADD %R12,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%RBX,%RCX,8),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x268(%RAX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x260(%RAX),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RSI,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %R10,%RBX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RBX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R9,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RCX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x2c0(%RAX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%RCX,%RDI,8),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x2f0(%RAX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x2e8(%RAX),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMULSD (%RBX),%XMM5,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
VFMADD132SD (%R12),%XMM10,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
IMUL 0x300(%RAX),%R8	1	0	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVSD 0x873a9(%RIP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
IMUL %RSI,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %R10,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RCX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x390(%RAX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R9,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x348(%RAX),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%R9,%R8,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x1b0(%RAX),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x3b0(%RAX),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RDI),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD213SD (%R8,%R11,8),%XMM9,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
MOV 0x360(%RAX),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R10,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
VADDSD %XMM11,%XMM4,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
IMUL %RSI,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL 0x3b8(%RAX),%RSI	1	0	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
MOV 0x3f8(%RAX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %RDX,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VADDSD (%RCX,%R11,8),%XMM9,%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VADDSD %XMM6,%XMM13,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VDIVSD %XMM14,%XMM12,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VMOVSD %XMM15,%XMM15,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVSD %XMM15,%XMM15,%XMM4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
ADD %RSI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R9,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM15,(%RAX,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VFMSUB213SD (%R12),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM1,(%R12)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VFMSUB213SD (%RBX),%XMM0,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM4,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VFMSUB213SD (%RDI),%XMM0,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM15,(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	SweepSubdomain.cpp:85-105
Module	libkripke.so

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:307
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp:85-105
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-6313/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp:110

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your function, you can lower the cost of an iteration from 20.00 to 5.00 cycles (4.00x speedup).

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 17.17 cycles (1.17x speedup).

FMA

Detected 5 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Type of elements and instruction set

17 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 22 FP arithmetical operations:

12: addition or subtraction (5 inside FMA instructions)
6: multiply (5 inside FMA instructions)
4: divide

The binary function is loading 352 bytes (44 double precision FP elements). The binary function is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	103
nb uops	103
loop length	485
used x86 registers	13
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	7.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.17 cycles
front end	17.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	7.00	17.00	6.75	6.75	0.50	16.00	16.00	16.00	5.00	5.00	4.50	4.50	2.00	2.00
cycles	7.00	17.00	6.75	6.75	0.50	16.00	16.00	16.00	5.00	5.00	4.50	4.50	2.00	2.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

20.00

Cycles summary

Front-end	17.17
Dispatch	17.00
DIV/SQRT	20.00
Overall L1	20.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	12%

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

18% of peak load performance is reached (17.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.60 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 706c0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RSI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV 0x20(%RAX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA (,%R10,8),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x70(%RAX),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x48(%RAX),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x98(%RAX),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RCX,%RDX,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0xc0(%RAX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VADDSD %XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSD (%R11,%RDX,1),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VDIVSD (%RBX,%R9,8),%XMM1,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	13	5
MOV 0x108(%RAX),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x118(%RAX),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VADDSD %XMM2,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VDIVSD (%R12,%R8,8),%XMM3,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	13	5
MOV 0x168(%RAX),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VADDSD %XMM5,%XMM4,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSD (%RCX,%RDX,1),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0xe8(%RAX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VADDSD %XMM7,%XMM7,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOV 0x1e0(%RAX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R9,%RBX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %RDI,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %R10,%R12	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
VDIVSD (%RDX,%RDI,8),%XMM8,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	13	5
MOV 0x110(%RAX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RSI,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %R8,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RBX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x1d8(%RAX),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R11,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x170(%RAX),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R10,%RBX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %RSI,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RBX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x238(%RAX),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %RDX,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R12,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x1f0(%RAX),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RDI,%R12	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL 0x278(%RAX),%RDI	1	0	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
ADD %R12,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%RBX,%RCX,8),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x268(%RAX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x260(%RAX),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RSI,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %R10,%RBX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RBX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R9,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RCX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x2c0(%RAX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%RCX,%RDI,8),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x2f0(%RAX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x2e8(%RAX),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMULSD (%RBX),%XMM5,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
VFMADD132SD (%R12),%XMM10,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
IMUL 0x300(%RAX),%R8	1	0	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVSD 0x873a9(%RIP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
IMUL %RSI,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %R10,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RCX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x390(%RAX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R9,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x348(%RAX),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%R9,%R8,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x1b0(%RAX),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x3b0(%RAX),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RDI),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD213SD (%R8,%R11,8),%XMM9,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
MOV 0x360(%RAX),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R10,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
VADDSD %XMM11,%XMM4,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
IMUL %RSI,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL 0x3b8(%RAX),%RSI	1	0	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
MOV 0x3f8(%RAX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %RDX,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VADDSD (%RCX,%R11,8),%XMM9,%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VADDSD %XMM6,%XMM13,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VDIVSD %XMM14,%XMM12,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VMOVSD %XMM15,%XMM15,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVSD %XMM15,%XMM15,%XMM4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
ADD %RSI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R9,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM15,(%RAX,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VFMSUB213SD (%R12),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM1,(%R12)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VFMSUB213SD (%RBX),%XMM0,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM4,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VFMSUB213SD (%RDI),%XMM0,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM15,(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
○_ZZNK9SweepSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_RNS1_4Core9DataStoreENS1_6SdomIdEENKUlNS1_9DirectionENS1_5GroupENS1_5ZoneKENS1_5ZoneJENS1_5ZoneIEE_clESB_SC_SD_SE_SF_	2.59	0.5

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code